1 From c382babccba2c82fe57f9e647f290fb7bf4d130d Mon Sep 17 00:00:00 2001
2 From: Azhar Shaikh <azhar.shaikh@intel.com>
3 Date: Fri, 22 Dec 2017 12:13:43 -0800
4 Subject: tpm_tis: Move ilb_base_addr to tpm_tis_data
6 From: Azhar Shaikh <azhar.shaikh@intel.com>
8 commit c382babccba2c82fe57f9e647f290fb7bf4d130d upstream.
10 Move static variable ilb_base_addr to tpm_tis_data.
12 Cc: stable@vger.kernel.org
13 Signed-off-by: Azhar Shaikh <azhar.shaikh@intel.com>
14 Reviewed-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
15 Tested-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
16 Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
17 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
20 drivers/char/tpm/tpm_tis.c | 75 ++++++++++++++--------------------------
21 drivers/char/tpm/tpm_tis_core.c | 16 ++++++++
22 drivers/char/tpm/tpm_tis_core.h | 13 ++++++
23 3 files changed, 56 insertions(+), 48 deletions(-)
25 --- a/drivers/char/tpm/tpm_tis.c
26 +++ b/drivers/char/tpm/tpm_tis.c
27 @@ -134,33 +134,24 @@ static int check_acpi_tpm2(struct device
31 -#define INTEL_LEGACY_BLK_BASE_ADDR 0xFED08000
32 -#define ILB_REMAP_SIZE 0x100
33 -#define LPC_CNTRL_REG_OFFSET 0x84
34 -#define LPC_CLKRUN_EN (1 << 2)
36 -static void __iomem *ilb_base_addr;
38 -static inline bool is_bsw(void)
40 - return ((boot_cpu_data.x86_model == INTEL_FAM6_ATOM_AIRMONT) ? 1 : 0);
42 +#define LPC_CNTRL_OFFSET 0x84
43 +#define LPC_CLKRUN_EN (1 << 2)
46 * tpm_platform_begin_xfer() - clear LPC CLKRUN_EN i.e. clocks will be running
48 -static void tpm_platform_begin_xfer(void)
49 +static void tpm_platform_begin_xfer(struct tpm_tis_data *data)
56 - clkrun_val = ioread32(ilb_base_addr + LPC_CNTRL_REG_OFFSET);
57 + clkrun_val = ioread32(data->ilb_base_addr + LPC_CNTRL_OFFSET);
59 /* Disable LPC CLKRUN# */
60 clkrun_val &= ~LPC_CLKRUN_EN;
61 - iowrite32(clkrun_val, ilb_base_addr + LPC_CNTRL_REG_OFFSET);
62 + iowrite32(clkrun_val, data->ilb_base_addr + LPC_CNTRL_OFFSET);
65 * Write any random value on port 0x80 which is on LPC, to make
66 @@ -173,18 +164,18 @@ static void tpm_platform_begin_xfer(void
68 * tpm_platform_end_xfer() - set LPC CLKRUN_EN i.e. clocks can be turned off
70 -static void tpm_platform_end_xfer(void)
71 +static void tpm_platform_end_xfer(struct tpm_tis_data *data)
78 - clkrun_val = ioread32(ilb_base_addr + LPC_CNTRL_REG_OFFSET);
79 + clkrun_val = ioread32(data->ilb_base_addr + LPC_CNTRL_OFFSET);
81 /* Enable LPC CLKRUN# */
82 clkrun_val |= LPC_CLKRUN_EN;
83 - iowrite32(clkrun_val, ilb_base_addr + LPC_CNTRL_REG_OFFSET);
84 + iowrite32(clkrun_val, data->ilb_base_addr + LPC_CNTRL_OFFSET);
87 * Write any random value on port 0x80 which is on LPC, to make
88 @@ -194,16 +185,11 @@ static void tpm_platform_end_xfer(void)
92 -static inline bool is_bsw(void)
97 -static void tpm_platform_begin_xfer(void)
98 +static void tpm_platform_begin_xfer(struct tpm_tis_data *data)
102 -static void tpm_platform_end_xfer(void)
103 +static void tpm_platform_end_xfer(struct tpm_tis_data *data)
107 @@ -213,12 +199,12 @@ static int tpm_tcg_read_bytes(struct tpm
109 struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
111 - tpm_platform_begin_xfer();
112 + tpm_platform_begin_xfer(data);
115 *result++ = ioread8(phy->iobase + addr);
117 - tpm_platform_end_xfer();
118 + tpm_platform_end_xfer(data);
122 @@ -228,12 +214,12 @@ static int tpm_tcg_write_bytes(struct tp
124 struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
126 - tpm_platform_begin_xfer();
127 + tpm_platform_begin_xfer(data);
130 iowrite8(*value++, phy->iobase + addr);
132 - tpm_platform_end_xfer();
133 + tpm_platform_end_xfer(data);
137 @@ -242,11 +228,11 @@ static int tpm_tcg_read16(struct tpm_tis
139 struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
141 - tpm_platform_begin_xfer();
142 + tpm_platform_begin_xfer(data);
144 *result = ioread16(phy->iobase + addr);
146 - tpm_platform_end_xfer();
147 + tpm_platform_end_xfer(data);
151 @@ -255,11 +241,11 @@ static int tpm_tcg_read32(struct tpm_tis
153 struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
155 - tpm_platform_begin_xfer();
156 + tpm_platform_begin_xfer(data);
158 *result = ioread32(phy->iobase + addr);
160 - tpm_platform_end_xfer();
161 + tpm_platform_end_xfer(data);
165 @@ -268,11 +254,11 @@ static int tpm_tcg_write32(struct tpm_ti
167 struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
169 - tpm_platform_begin_xfer();
170 + tpm_platform_begin_xfer(data);
172 iowrite32(value, phy->iobase + addr);
174 - tpm_platform_end_xfer();
175 + tpm_platform_end_xfer(data);
179 @@ -351,9 +337,13 @@ MODULE_DEVICE_TABLE(pnp, tpm_pnp_tbl);
180 static void tpm_tis_pnp_remove(struct pnp_dev *dev)
182 struct tpm_chip *chip = pnp_get_drvdata(dev);
183 + struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
185 tpm_chip_unregister(chip);
186 tpm_tis_remove(chip);
188 + iounmap(priv->ilb_base_addr);
192 static struct pnp_driver tis_pnp_driver = {
193 @@ -400,10 +390,14 @@ static int tpm_tis_plat_probe(struct pla
194 static int tpm_tis_plat_remove(struct platform_device *pdev)
196 struct tpm_chip *chip = dev_get_drvdata(&pdev->dev);
197 + struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
199 tpm_chip_unregister(chip);
200 tpm_tis_remove(chip);
203 + iounmap(priv->ilb_base_addr);
208 @@ -461,11 +455,6 @@ static int __init init_tis(void)
214 - ilb_base_addr = ioremap(INTEL_LEGACY_BLK_BASE_ADDR,
217 rc = platform_driver_register(&tis_drv);
220 @@ -484,10 +473,6 @@ err_pnp:
223 platform_device_unregister(force_pdev);
226 - iounmap(ilb_base_addr);
231 @@ -497,10 +482,6 @@ static void __exit cleanup_tis(void)
232 pnp_unregister_driver(&tis_pnp_driver);
233 platform_driver_unregister(&tis_drv);
237 - iounmap(ilb_base_addr);
240 platform_device_unregister(force_pdev);
242 --- a/drivers/char/tpm/tpm_tis_core.c
243 +++ b/drivers/char/tpm/tpm_tis_core.c
244 @@ -701,6 +701,13 @@ int tpm_tis_core_init(struct device *dev
245 priv->phy_ops = phy_ops;
246 dev_set_drvdata(&chip->dev, priv);
249 + priv->ilb_base_addr = ioremap(INTEL_LEGACY_BLK_BASE_ADDR,
251 + if (!priv->ilb_base_addr)
255 if (wait_startup(chip, 0) != 0) {
258 @@ -791,9 +798,16 @@ int tpm_tis_core_init(struct device *dev
262 - return tpm_chip_register(chip);
263 + rc = tpm_chip_register(chip);
264 + if (rc && is_bsw())
265 + iounmap(priv->ilb_base_addr);
269 tpm_tis_remove(chip);
271 + iounmap(priv->ilb_base_addr);
275 EXPORT_SYMBOL_GPL(tpm_tis_core_init);
276 --- a/drivers/char/tpm/tpm_tis_core.h
277 +++ b/drivers/char/tpm/tpm_tis_core.h
278 @@ -79,6 +79,9 @@ enum tis_defaults {
279 #define TPM_DID_VID(l) (0x0F00 | ((l) << 12))
280 #define TPM_RID(l) (0x0F04 | ((l) << 12))
282 +#define INTEL_LEGACY_BLK_BASE_ADDR 0xFED08000
283 +#define ILB_REMAP_SIZE 0x100
286 TPM_TIS_ITPM_WORKAROUND = BIT(0),
288 @@ -89,6 +92,7 @@ struct tpm_tis_data {
292 + void __iomem *ilb_base_addr;
293 wait_queue_head_t int_queue;
294 wait_queue_head_t read_queue;
295 const struct tpm_tis_phy_ops *phy_ops;
296 @@ -144,6 +148,15 @@ static inline int tpm_tis_write32(struct
297 return data->phy_ops->write32(data, addr, value);
300 +static inline bool is_bsw(void)
303 + return ((boot_cpu_data.x86_model == INTEL_FAM6_ATOM_AIRMONT) ? 1 : 0);
309 void tpm_tis_remove(struct tpm_chip *chip);
310 int tpm_tis_core_init(struct device *dev, struct tpm_tis_data *priv, int irq,
311 const struct tpm_tis_phy_ops *phy_ops,