1 From 8a331f4a0863bea758561c921b94b4d28f7c4029 Mon Sep 17 00:00:00 2001
2 From: Yazen Ghannam <yazen.ghannam@amd.com>
3 Date: Wed, 21 Feb 2018 11:19:00 +0100
4 Subject: x86/mce/AMD: Carve out SMCA get_block_address() code
6 From: Yazen Ghannam <yazen.ghannam@amd.com>
8 commit 8a331f4a0863bea758561c921b94b4d28f7c4029 upstream.
10 Carve out the SMCA code in get_block_address() into a separate helper
15 Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
16 [ Save an indentation level. ]
17 Signed-off-by: Borislav Petkov <bp@suse.de>
18 Cc: Borislav Petkov <bp@alien8.de>
19 Cc: Linus Torvalds <torvalds@linux-foundation.org>
20 Cc: Peter Zijlstra <peterz@infradead.org>
21 Cc: Thomas Gleixner <tglx@linutronix.de>
22 Cc: Tony Luck <tony.luck@intel.com>
23 Cc: linux-edac <linux-edac@vger.kernel.org>
24 Link: http://lkml.kernel.org/r/20180215210943.11530-4-Yazen.Ghannam@amd.com
25 Signed-off-by: Ingo Molnar <mingo@kernel.org>
26 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
29 arch/x86/kernel/cpu/mcheck/mce_amd.c | 57 +++++++++++++++++++----------------
30 1 file changed, 31 insertions(+), 26 deletions(-)
32 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
33 +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
34 @@ -431,6 +431,35 @@ static void deferred_error_interrupt_ena
35 wrmsr(MSR_CU_DEF_ERR, low, high);
38 +static u32 smca_get_block_address(unsigned int cpu, unsigned int bank,
44 + if (smca_get_bank_type(bank) == SMCA_RESERVED)
48 + return MSR_AMD64_SMCA_MCx_MISC(bank);
51 + * For SMCA enabled processors, BLKPTR field of the first MISC register
52 + * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4).
54 + if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
57 + if (!(low & MCI_CONFIG_MCAX))
60 + if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) &&
61 + (low & MASK_BLKPTR_LO))
62 + return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
67 static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 high,
68 unsigned int bank, unsigned int block)
70 @@ -451,32 +480,8 @@ static u32 get_block_address(unsigned in
74 - if (mce_flags.smca) {
75 - if (smca_get_bank_type(bank) == SMCA_RESERVED)
79 - addr = MSR_AMD64_SMCA_MCx_MISC(bank);
82 - * For SMCA enabled processors, BLKPTR field of the
83 - * first MISC register (MCx_MISC0) indicates presence of
84 - * additional MISC register set (MISC1-4).
88 - if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
91 - if (!(low & MCI_CONFIG_MCAX))
94 - if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) &&
95 - (low & MASK_BLKPTR_LO))
96 - addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
100 + if (mce_flags.smca)
101 + return smca_get_block_address(cpu, bank, block);
103 /* Fall back to method we used for older processors: */