releases/4.16.4/clk-mediatek-fix-pwm-clock-source-by-adding-a-fixed-factor-clock.patch

   1 From 89cd7aec21af26fd0c117bfc4bfc781724f201de Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Thu, 1 Mar 2018 11:27:51 +0800
   4 Subject: clk: mediatek: fix PWM clock source by adding a fixed-factor clock
   5
   6 From: Sean Wang <sean.wang@mediatek.com>
   7
   8 commit 89cd7aec21af26fd0c117bfc4bfc781724f201de upstream.
   9
  10 The clock for which all PWM devices on MT7623 or MT2701 actually depending
  11 on has to be divided by four from its parent clock axi_sel in the clock
  12 path prior to PWM devices.
  13
  14 Consequently, adding a fixed-factor clock axisel_d4 as one-fourth of
  15 clock axi_sel allows that PWM devices can have the correct resolution
  16 calculation.
  17
  18 Cc: stable@vger.kernel.org
  19 Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support")
  20 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  21 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  22 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  23
  24 ---
  25  drivers/clk/mediatek/clk-mt2701.c |   15 ++++++++-------
  26  1 file changed, 8 insertions(+), 7 deletions(-)
  27
  28 --- a/drivers/clk/mediatek/clk-mt2701.c
  29 +++ b/drivers/clk/mediatek/clk-mt2701.c
  30 @@ -148,6 +148,7 @@ static const struct mtk_fixed_factor top
  31         FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8),
  32         FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793),
  33         FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1),
  34 +       FACTOR(CLK_TOP_AXISEL_D4, "axisel_d4", "axi_sel", 1, 4),
  35  };
  36
  37  static const char * const axi_parents[] = {
  38 @@ -857,13 +858,13 @@ static const struct mtk_gate peri_clks[]
  39         GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
  40         GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
  41         GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
  42 -       GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
  43 -       GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
  44 -       GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
  45 -       GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
  46 -       GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
  47 -       GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
  48 -       GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
  49 +       GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axisel_d4", 8),
  50 +       GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axisel_d4", 7),
  51 +       GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6),
  52 +       GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axisel_d4", 5),
  53 +       GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axisel_d4", 4),
  54 +       GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axisel_d4", 3),
  55 +       GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axisel_d4", 2),
  56         GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
  57         GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),
  58