releases/4.19.27/asoc-rt5682-fix-pll-source-register-definitions.patch

   1 From 6b892c85b53a5884bd362ba3ef06cbe5363240b0 Mon Sep 17 00:00:00 2001
   2 From: Shuming Fan <shumingf@realtek.com>
   3 Date: Tue, 15 Jan 2019 11:27:39 +0800
   4 Subject: ASoC: rt5682: Fix PLL source register definitions
   5
   6 [ Upstream commit ee7ea2a9a318a89d21b156dc75e54d53904bdbe5 ]
   7
   8 Fix typo which causes headphone no sound while using BCLK
   9 as PLL source.
  10
  11 Signed-off-by: Shuming Fan <shumingf@realtek.com>
  12 Signed-off-by: Mark Brown <broonie@kernel.org>
  13 Signed-off-by: Sasha Levin <sashal@kernel.org>
  14 ---
  15  sound/soc/codecs/rt5682.h | 24 ++++++++++++------------
  16  1 file changed, 12 insertions(+), 12 deletions(-)
  17
  18 diff --git a/sound/soc/codecs/rt5682.h b/sound/soc/codecs/rt5682.h
  19 index 8068140ebe3f1..cdd659f4df93d 100644
  20 --- a/sound/soc/codecs/rt5682.h
  21 +++ b/sound/soc/codecs/rt5682.h
  22 @@ -849,18 +849,18 @@
  23  #define RT5682_SCLK_SRC_PLL2                   (0x2 << 13)
  24  #define RT5682_SCLK_SRC_SDW                    (0x3 << 13)
  25  #define RT5682_SCLK_SRC_RCCLK                  (0x4 << 13)
  26 -#define RT5682_PLL1_SRC_MASK                   (0x3 << 10)
  27 -#define RT5682_PLL1_SRC_SFT                    10
  28 -#define RT5682_PLL1_SRC_MCLK                   (0x0 << 10)
  29 -#define RT5682_PLL1_SRC_BCLK1                  (0x1 << 10)
  30 -#define RT5682_PLL1_SRC_SDW                    (0x2 << 10)
  31 -#define RT5682_PLL1_SRC_RC                     (0x3 << 10)
  32 -#define RT5682_PLL2_SRC_MASK                   (0x3 << 8)
  33 -#define RT5682_PLL2_SRC_SFT                    8
  34 -#define RT5682_PLL2_SRC_MCLK                   (0x0 << 8)
  35 -#define RT5682_PLL2_SRC_BCLK1                  (0x1 << 8)
  36 -#define RT5682_PLL2_SRC_SDW                    (0x2 << 8)
  37 -#define RT5682_PLL2_SRC_RC                     (0x3 << 8)
  38 +#define RT5682_PLL2_SRC_MASK                   (0x3 << 10)
  39 +#define RT5682_PLL2_SRC_SFT                    10
  40 +#define RT5682_PLL2_SRC_MCLK                   (0x0 << 10)
  41 +#define RT5682_PLL2_SRC_BCLK1                  (0x1 << 10)
  42 +#define RT5682_PLL2_SRC_SDW                    (0x2 << 10)
  43 +#define RT5682_PLL2_SRC_RC                     (0x3 << 10)
  44 +#define RT5682_PLL1_SRC_MASK                   (0x3 << 8)
  45 +#define RT5682_PLL1_SRC_SFT                    8
  46 +#define RT5682_PLL1_SRC_MCLK                   (0x0 << 8)
  47 +#define RT5682_PLL1_SRC_BCLK1                  (0x1 << 8)
  48 +#define RT5682_PLL1_SRC_SDW                    (0x2 << 8)
  49 +#define RT5682_PLL1_SRC_RC                     (0x3 << 8)
  50
  51
  52
  53 --
  54 2.19.1
  55