releases/4.19.29/x86-pci-fixup-rtit_bar-of-intel-denverton-trace-hub.patch

   1 From 2e095ce7b6ecce2f3e2ff330527f12056ed1e1a1 Mon Sep 17 00:00:00 2001
   2 From: Alexander Shishkin <alexander.shishkin@linux.intel.com>
   3 Date: Thu, 7 Feb 2019 15:30:05 +0200
   4 Subject: x86/PCI: Fixup RTIT_BAR of Intel Denverton Trace Hub
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   8
   9 From: Alexander Shishkin <alexander.shishkin@linux.intel.com>
  10
  11 commit 2e095ce7b6ecce2f3e2ff330527f12056ed1e1a1 upstream.
  12
  13 On Denverton's integration of the Intel(R) Trace Hub (for a reference and
  14 overview see Documentation/trace/intel_th.rst) the reported size of one of
  15 its resources (RTIT_BAR) doesn't match its actual size, which leads to
  16 overlaps with other devices' resources.
  17
  18 In practice, it overlaps with XHCI MMIO space, which results in the xhci
  19 driver bailing out after seeing its registers as 0xffffffff, and perceived
  20 disappearance of all USB devices:
  21
  22   intel_th_pci 0000:00:1f.7: enabling device (0004 -> 0006)
  23   xhci_hcd 0000:00:15.0: xHCI host controller not responding, assume dead
  24   xhci_hcd 0000:00:15.0: xHC not responding in xhci_irq, assume controller is dead
  25   xhci_hcd 0000:00:15.0: HC died; cleaning up
  26   usb 1-1: USB disconnect, device number 2
  27
  28 For this reason, we need to resize the RTIT_BAR on Denverton to its actual
  29 size, which in this case is 4MB.  The corresponding erratum is DNV36 at the
  30 link below:
  31
  32   DNV36.       Processor Host Root Complex May Incorrectly Route Memory
  33                Accesses to Intel® Trace Hub
  34
  35   Problem:     The Intel® Trace Hub RTIT_BAR (B0:D31:F7 offset 20h) is
  36                reported as a 2KB memory range.  Due to this erratum, the
  37                processor Host Root Complex will forward addresses from
  38                RTIT_BAR to RTIT_BAR + 4MB -1 to Intel® Trace Hub.
  39
  40   Implication: Devices assigned within the RTIT_BAR to RTIT_BAR + 4MB -1
  41                space may not function correctly.
  42
  43   Workaround:  A BIOS code change has been identified and may be
  44                implemented as a workaround for this erratum.
  45
  46   Status:      No Fix.
  47
  48 Note that 5118ccd34780 ("intel_th: pci: Add Denverton SOC support") updates
  49 the Trace Hub driver so it claims the Denverton device, but the resource
  50 overlap exists regardless of whether that driver is loaded or that commit
  51 is included.
  52
  53 Link: https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/atom-c3000-family-spec-update.pdf
  54 Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
  55 [bhelgaas: include erratum text, clarify relationship with 5118ccd34780]
  56 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  57 Cc: stable@vger.kernel.org
  58 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  59
  60 ---
  61  arch/x86/pci/fixup.c |   16 ++++++++++++++++
  62  1 file changed, 16 insertions(+)
  63
  64 --- a/arch/x86/pci/fixup.c
  65 +++ b/arch/x86/pci/fixup.c
  66 @@ -641,6 +641,22 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IN
  67  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x334c, quirk_no_aersid);
  68  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x334d, quirk_no_aersid);
  69
  70 +static void quirk_intel_th_dnv(struct pci_dev *dev)
  71 +{
  72 +       struct resource *r = &dev->resource[4];
  73 +
  74 +       /*
  75 +        * Denverton reports 2k of RTIT_BAR (intel_th resource 4), which
  76 +        * appears to be 4 MB in reality.
  77 +        */
  78 +       if (r->end == r->start + 0x7ff) {
  79 +               r->start = 0;
  80 +               r->end   = 0x3fffff;
  81 +               r->flags |= IORESOURCE_UNSET;
  82 +       }
  83 +}
  84 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x19e1, quirk_intel_th_dnv);
  85 +
  86  #ifdef CONFIG_PHYS_ADDR_T_64BIT
  87
  88  #define AMD_141b_MMIO_BASE(x)  (0x80 + (x) * 0x8)