releases/4.19.31/clk-sunxi-a31-fix-wrong-ahb-gate-number.patch

   1 From 0221ed8b0b7d667426042d4ce134581308f8d44d Mon Sep 17 00:00:00 2001
   2 From: Andre Przywara <andre.przywara@arm.com>
   3 Date: Wed, 23 Jan 2019 00:59:11 +0000
   4 Subject: clk: sunxi: A31: Fix wrong AHB gate number
   5
   6 [ Upstream commit ee0b27a3a4da0b0ed2318aa092f8856896e9450b ]
   7
   8 According to the manual the gate clock for MMC3 is at bit 11, and NAND1
   9 is controlled by bit 12.
  10
  11 Fix the gate bit definitions in the clock driver.
  12
  13 Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
  14 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
  15 Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
  16 Signed-off-by: Sasha Levin <sashal@kernel.org>
  17 ---
  18  drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 4 ++--
  19  1 file changed, 2 insertions(+), 2 deletions(-)
  20
  21 diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
  22 index 3b97f60540ad..609970c0b666 100644
  23 --- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
  24 +++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
  25 @@ -264,9 +264,9 @@ static SUNXI_CCU_GATE(ahb1_mmc1_clk,        "ahb1-mmc1",    "ahb1",
  26  static SUNXI_CCU_GATE(ahb1_mmc2_clk,   "ahb1-mmc2",    "ahb1",
  27                       0x060, BIT(10), 0);
  28  static SUNXI_CCU_GATE(ahb1_mmc3_clk,   "ahb1-mmc3",    "ahb1",
  29 -                     0x060, BIT(12), 0);
  30 +                     0x060, BIT(11), 0);
  31  static SUNXI_CCU_GATE(ahb1_nand1_clk,  "ahb1-nand1",   "ahb1",
  32 -                     0x060, BIT(13), 0);
  33 +                     0x060, BIT(12), 0);
  34  static SUNXI_CCU_GATE(ahb1_nand0_clk,  "ahb1-nand0",   "ahb1",
  35                       0x060, BIT(13), 0);
  36  static SUNXI_CCU_GATE(ahb1_sdram_clk,  "ahb1-sdram",   "ahb1",
  37 --
  38 2.19.1
  39