releases/4.19.9/mtd-rawnand-qcom-namespace-prefix-some-commands.patch

   1 From 89e82b8c703c04f875fac0d9ef72ea64fd71e3b6 Mon Sep 17 00:00:00 2001
   2 From: Olof Johansson <olof@lixom.net>
   3 Date: Fri, 16 Nov 2018 19:43:27 -0800
   4 Subject: mtd: rawnand: qcom: Namespace prefix some commands
   5
   6 [ Upstream commit 33bf5519ae5dd356b182a94e3622f42860274a38 ]
   7
   8 PAGE_READ is used by RISC-V arch code included through mm headers,
   9 and it makes sense to bring in a prefix on these in the driver.
  10
  11 drivers/mtd/nand/raw/qcom_nandc.c:153: warning: "PAGE_READ" redefined
  12  #define PAGE_READ   0x2
  13 In file included from include/linux/memremap.h:7,
  14                  from include/linux/mm.h:27,
  15                  from include/linux/scatterlist.h:8,
  16                  from include/linux/dma-mapping.h:11,
  17                  from drivers/mtd/nand/raw/qcom_nandc.c:17:
  18 arch/riscv/include/asm/pgtable.h:48: note: this is the location of the previous definition
  19
  20 Caught by riscv allmodconfig.
  21
  22 Signed-off-by: Olof Johansson <olof@lixom.net>
  23 Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
  24 Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
  25 Signed-off-by: Sasha Levin <sashal@kernel.org>
  26 ---
  27  drivers/mtd/nand/raw/qcom_nandc.c | 32 +++++++++++++++----------------
  28  1 file changed, 16 insertions(+), 16 deletions(-)
  29
  30 diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
  31 index d1d470bb32e4..8815f3e2b718 100644
  32 --- a/drivers/mtd/nand/raw/qcom_nandc.c
  33 +++ b/drivers/mtd/nand/raw/qcom_nandc.c
  34 @@ -151,15 +151,15 @@
  35  #define        NAND_VERSION_MINOR_SHIFT        16
  36
  37  /* NAND OP_CMDs */
  38 -#define        PAGE_READ                       0x2
  39 -#define        PAGE_READ_WITH_ECC              0x3
  40 -#define        PAGE_READ_WITH_ECC_SPARE        0x4
  41 -#define        PROGRAM_PAGE                    0x6
  42 -#define        PAGE_PROGRAM_WITH_ECC           0x7
  43 -#define        PROGRAM_PAGE_SPARE              0x9
  44 -#define        BLOCK_ERASE                     0xa
  45 -#define        FETCH_ID                        0xb
  46 -#define        RESET_DEVICE                    0xd
  47 +#define        OP_PAGE_READ                    0x2
  48 +#define        OP_PAGE_READ_WITH_ECC           0x3
  49 +#define        OP_PAGE_READ_WITH_ECC_SPARE     0x4
  50 +#define        OP_PROGRAM_PAGE                 0x6
  51 +#define        OP_PAGE_PROGRAM_WITH_ECC        0x7
  52 +#define        OP_PROGRAM_PAGE_SPARE           0x9
  53 +#define        OP_BLOCK_ERASE                  0xa
  54 +#define        OP_FETCH_ID                     0xb
  55 +#define        OP_RESET_DEVICE                 0xd
  56
  57  /* Default Value for NAND_DEV_CMD_VLD */
  58  #define NAND_DEV_CMD_VLD_VAL           (READ_START_VLD | WRITE_START_VLD | \
  59 @@ -692,11 +692,11 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
  60
  61         if (read) {
  62                 if (host->use_ecc)
  63 -                       cmd = PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
  64 +                       cmd = OP_PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
  65                 else
  66 -                       cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
  67 +                       cmd = OP_PAGE_READ | PAGE_ACC | LAST_PAGE;
  68         } else {
  69 -                       cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
  70 +               cmd = OP_PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
  71         }
  72
  73         if (host->use_ecc) {
  74 @@ -1170,7 +1170,7 @@ static int nandc_param(struct qcom_nand_host *host)
  75          * in use. we configure the controller to perform a raw read of 512
  76          * bytes to read onfi params
  77          */
  78 -       nandc_set_reg(nandc, NAND_FLASH_CMD, PAGE_READ | PAGE_ACC | LAST_PAGE);
  79 +       nandc_set_reg(nandc, NAND_FLASH_CMD, OP_PAGE_READ | PAGE_ACC | LAST_PAGE);
  80         nandc_set_reg(nandc, NAND_ADDR0, 0);
  81         nandc_set_reg(nandc, NAND_ADDR1, 0);
  82         nandc_set_reg(nandc, NAND_DEV0_CFG0, 0 << CW_PER_PAGE
  83 @@ -1224,7 +1224,7 @@ static int erase_block(struct qcom_nand_host *host, int page_addr)
  84         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
  85
  86         nandc_set_reg(nandc, NAND_FLASH_CMD,
  87 -                     BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
  88 +                     OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
  89         nandc_set_reg(nandc, NAND_ADDR0, page_addr);
  90         nandc_set_reg(nandc, NAND_ADDR1, 0);
  91         nandc_set_reg(nandc, NAND_DEV0_CFG0,
  92 @@ -1255,7 +1255,7 @@ static int read_id(struct qcom_nand_host *host, int column)
  93         if (column == -1)
  94                 return 0;
  95
  96 -       nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);
  97 +       nandc_set_reg(nandc, NAND_FLASH_CMD, OP_FETCH_ID);
  98         nandc_set_reg(nandc, NAND_ADDR0, column);
  99         nandc_set_reg(nandc, NAND_ADDR1, 0);
 100         nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
 101 @@ -1276,7 +1276,7 @@ static int reset(struct qcom_nand_host *host)
 102         struct nand_chip *chip = &host->chip;
 103         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
 104
 105 -       nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
 106 +       nandc_set_reg(nandc, NAND_FLASH_CMD, OP_RESET_DEVICE);
 107         nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
 108
 109         write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
 110 --
 111 2.19.1
 112