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[thirdparty/kernel/stable-queue.git] / releases / 4.4.13 / mips-use-copy_s.fmt-rather-than-copy_u.fmt.patch
1 From 8a3c8b48aca8771bff3536e40aa26ffb311699d1 Mon Sep 17 00:00:00 2001
2 From: Paul Burton <paul.burton@imgtec.com>
3 Date: Fri, 15 Apr 2016 10:07:23 +0100
4 Subject: MIPS: Use copy_s.fmt rather than copy_u.fmt
5
6 From: Paul Burton <paul.burton@imgtec.com>
7
8 commit 8a3c8b48aca8771bff3536e40aa26ffb311699d1 upstream.
9
10 In revision 1.12 of the MSA specification, the copy_u.w instruction has
11 been removed for MIPS32 & the copy_u.d instruction has been removed for
12 MIPS64. Newer toolchains (eg. Codescape SDK essentials 2015.10) will
13 complain about this like so:
14
15 arch/mips/kernel/r4k_fpu.S:290: Error: opcode not supported on this
16 processor: mips32r2 (mips32r2) `copy_u.w $1,$w26[3]'
17
18 Since we always copy to the width of a GPR, simply use copy_s instead of
19 copy_u to fix this.
20
21 Signed-off-by: Paul Burton <paul.burton@imgtec.com>
22 Signed-off-by: James Hogan <james.hogan@imgtec.com>
23 Cc: linux-mips@linux-mips.org
24 Patchwork: https://patchwork.linux-mips.org/patch/13061/
25 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
26 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
27
28 ---
29 arch/mips/include/asm/asmmacro.h | 24 ++++++++++++------------
30 arch/mips/kernel/r4k_fpu.S | 10 +++++-----
31 2 files changed, 17 insertions(+), 17 deletions(-)
32
33 --- a/arch/mips/include/asm/asmmacro.h
34 +++ b/arch/mips/include/asm/asmmacro.h
35 @@ -298,21 +298,21 @@
36 .set pop
37 .endm
38
39 - .macro copy_u_w ws, n
40 + .macro copy_s_w ws, n
41 .set push
42 .set mips32r2
43 .set fp=64
44 .set msa
45 - copy_u.w $1, $w\ws[\n]
46 + copy_s.w $1, $w\ws[\n]
47 .set pop
48 .endm
49
50 - .macro copy_u_d ws, n
51 + .macro copy_s_d ws, n
52 .set push
53 .set mips64r2
54 .set fp=64
55 .set msa
56 - copy_u.d $1, $w\ws[\n]
57 + copy_s.d $1, $w\ws[\n]
58 .set pop
59 .endm
60
61 @@ -346,8 +346,8 @@
62 #define STH_MSA_INSN 0x5800081f
63 #define STW_MSA_INSN 0x5800082f
64 #define STD_MSA_INSN 0x5800083f
65 -#define COPY_UW_MSA_INSN 0x58f00056
66 -#define COPY_UD_MSA_INSN 0x58f80056
67 +#define COPY_SW_MSA_INSN 0x58b00056
68 +#define COPY_SD_MSA_INSN 0x58b80056
69 #define INSERT_W_MSA_INSN 0x59300816
70 #define INSERT_D_MSA_INSN 0x59380816
71 #else
72 @@ -361,8 +361,8 @@
73 #define STH_MSA_INSN 0x78000825
74 #define STW_MSA_INSN 0x78000826
75 #define STD_MSA_INSN 0x78000827
76 -#define COPY_UW_MSA_INSN 0x78f00059
77 -#define COPY_UD_MSA_INSN 0x78f80059
78 +#define COPY_SW_MSA_INSN 0x78b00059
79 +#define COPY_SD_MSA_INSN 0x78b80059
80 #define INSERT_W_MSA_INSN 0x79300819
81 #define INSERT_D_MSA_INSN 0x79380819
82 #endif
83 @@ -461,21 +461,21 @@
84 .set pop
85 .endm
86
87 - .macro copy_u_w ws, n
88 + .macro copy_s_w ws, n
89 .set push
90 .set noat
91 SET_HARDFLOAT
92 .insn
93 - .word COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11)
94 + .word COPY_SW_MSA_INSN | (\n << 16) | (\ws << 11)
95 .set pop
96 .endm
97
98 - .macro copy_u_d ws, n
99 + .macro copy_s_d ws, n
100 .set push
101 .set noat
102 SET_HARDFLOAT
103 .insn
104 - .word COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11)
105 + .word COPY_SD_MSA_INSN | (\n << 16) | (\ws << 11)
106 .set pop
107 .endm
108
109 --- a/arch/mips/kernel/r4k_fpu.S
110 +++ b/arch/mips/kernel/r4k_fpu.S
111 @@ -244,17 +244,17 @@ LEAF(\name)
112 .set push
113 .set noat
114 #ifdef CONFIG_64BIT
115 - copy_u_d \wr, 1
116 + copy_s_d \wr, 1
117 EX sd $1, \off(\base)
118 #elif defined(CONFIG_CPU_LITTLE_ENDIAN)
119 - copy_u_w \wr, 2
120 + copy_s_w \wr, 2
121 EX sw $1, \off(\base)
122 - copy_u_w \wr, 3
123 + copy_s_w \wr, 3
124 EX sw $1, (\off+4)(\base)
125 #else /* CONFIG_CPU_BIG_ENDIAN */
126 - copy_u_w \wr, 2
127 + copy_s_w \wr, 2
128 EX sw $1, (\off+4)(\base)
129 - copy_u_w \wr, 3
130 + copy_s_w \wr, 3
131 EX sw $1, \off(\base)
132 #endif
133 .set pop