releases/4.4.160/arm64-cpufeature-track-32bit-el0-support.patch

   1 From 042446a31e3803d81c7e618dd80928dc3dce70c5 Mon Sep 17 00:00:00 2001
   2 From: Suzuki K Poulose <suzuki.poulose@arm.com>
   3 Date: Mon, 18 Apr 2016 10:28:36 +0100
   4 Subject: arm64: cpufeature: Track 32bit EL0 support
   5
   6 From: Suzuki K Poulose <suzuki.poulose@arm.com>
   7
   8 commit 042446a31e3803d81c7e618dd80928dc3dce70c5 upstream.
   9
  10 Add cpu_hwcap bit for keeping track of the support for 32bit EL0.
  11
  12 Tested-by: Yury Norov <ynorov@caviumnetworks.com>
  13 Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
  14 Signed-off-by: Will Deacon <will.deacon@arm.com>
  15 Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
  16 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  17 ---
  18  arch/arm64/include/asm/cpufeature.h |    8 +++++++-
  19  arch/arm64/include/asm/sysreg.h     |    1 +
  20  arch/arm64/kernel/cpufeature.c      |    8 ++++++++
  21  3 files changed, 16 insertions(+), 1 deletion(-)
  22
  23 --- a/arch/arm64/include/asm/cpufeature.h
  24 +++ b/arch/arm64/include/asm/cpufeature.h
  25 @@ -31,8 +31,9 @@
  26  #define ARM64_WORKAROUND_CAVIUM_23154          6
  27  #define ARM64_WORKAROUND_834220                        7
  28  #define ARM64_WORKAROUND_CAVIUM_27456          8
  29 +#define ARM64_HAS_32BIT_EL0                    9
  30
  31 -#define ARM64_NCAPS                            9
  32 +#define ARM64_NCAPS                            10
  33
  34  #ifndef __ASSEMBLY__
  35
  36 @@ -180,6 +181,11 @@ static inline bool cpu_supports_mixed_en
  37         return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
  38  }
  39
  40 +static inline bool system_supports_32bit_el0(void)
  41 +{
  42 +       return cpus_have_cap(ARM64_HAS_32BIT_EL0);
  43 +}
  44 +
  45  static inline bool system_supports_mixed_endian_el0(void)
  46  {
  47         return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1));
  48 --- a/arch/arm64/include/asm/sysreg.h
  49 +++ b/arch/arm64/include/asm/sysreg.h
  50 @@ -109,6 +109,7 @@
  51  #define ID_AA64PFR0_ASIMD_SUPPORTED    0x0
  52  #define ID_AA64PFR0_EL1_64BIT_ONLY     0x1
  53  #define ID_AA64PFR0_EL0_64BIT_ONLY     0x1
  54 +#define ID_AA64PFR0_EL0_32BIT_64BIT    0x2
  55
  56  /* id_aa64mmfr0 */
  57  #define ID_AA64MMFR0_TGRAN4_SHIFT      28
  58 --- a/arch/arm64/kernel/cpufeature.c
  59 +++ b/arch/arm64/kernel/cpufeature.c
  60 @@ -653,6 +653,14 @@ static const struct arm64_cpu_capabiliti
  61                 .min_field_value = 2,
  62         },
  63  #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
  64 +       {
  65 +               .desc = "32-bit EL0 Support",
  66 +               .capability = ARM64_HAS_32BIT_EL0,
  67 +               .matches = has_cpuid_feature,
  68 +               .sys_reg = SYS_ID_AA64PFR0_EL1,
  69 +               .field_pos = ID_AA64PFR0_EL0_SHIFT,
  70 +               .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
  71 +       },
  72         {},
  73  };
  74