releases/4.5.7/clk-bcm2835-correctly-enable-fractional-clock-support.patch

   1 From 959ca92a3235fc4b17c1e18483fc390b3d612254 Mon Sep 17 00:00:00 2001
   2 From: Martin Sperl <kernel@martin.sperl.org>
   3 Date: Mon, 29 Feb 2016 11:39:21 +0000
   4 Subject: clk: bcm2835: correctly enable fractional clock support
   5
   6 From: Martin Sperl <kernel@martin.sperl.org>
   7
   8 commit 959ca92a3235fc4b17c1e18483fc390b3d612254 upstream.
   9
  10 The current driver calculates the clock divider with
  11 fractional support enabled.
  12
  13 But it does not enable fractional support in the
  14 control register itself resulting in an integer only divider,
  15 but in clk_set_rate responds back the fractionally divided
  16 clock frequency.
  17
  18 This patch enables fractional support in the control register
  19 whenever there is a fractional bit set in the requested clock divider.
  20
  21 Mash clock limits are are also handled for the PWM clock
  22 applying the correct divider limits (2 and max_int) applicable to
  23 basic fractional divider support (mash order of 1).
  24
  25 It also adds locking to protect the read/modify/write cycle of
  26 the register modification.
  27
  28 Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
  29 audio domain clocks")
  30
  31 Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
  32 Signed-off-by: Eric Anholt <eric@anholt.net>
  33 Reviewed-by: Eric Anholt <eric@anholt.net>
  34 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  35
  36 ---
  37  drivers/clk/bcm/clk-bcm2835.c |   45 ++++++++++++++++++++++++++++++++++++------
  38  1 file changed, 39 insertions(+), 6 deletions(-)
  39
  40 --- a/drivers/clk/bcm/clk-bcm2835.c
  41 +++ b/drivers/clk/bcm/clk-bcm2835.c
  42 @@ -51,6 +51,7 @@
  43  #define CM_GNRICCTL            0x000
  44  #define CM_GNRICDIV            0x004
  45  # define CM_DIV_FRAC_BITS      12
  46 +# define CM_DIV_FRAC_MASK      GENMASK(CM_DIV_FRAC_BITS - 1, 0)
  47
  48  #define CM_VPUCTL              0x008
  49  #define CM_VPUDIV              0x00c
  50 @@ -115,6 +116,7 @@
  51  # define CM_GATE                       BIT(CM_GATE_BIT)
  52  # define CM_BUSY                       BIT(7)
  53  # define CM_BUSYD                      BIT(8)
  54 +# define CM_FRAC                       BIT(9)
  55  # define CM_SRC_SHIFT                  0
  56  # define CM_SRC_BITS                   4
  57  # define CM_SRC_MASK                   0xf
  58 @@ -634,6 +636,7 @@ struct bcm2835_clock_data {
  59         u32 frac_bits;
  60
  61         bool is_vpu_clock;
  62 +       bool is_mash_clock;
  63  };
  64
  65  static const char *const bcm2835_clock_per_parents[] = {
  66 @@ -815,6 +818,7 @@ static const struct bcm2835_clock_data b
  67         .div_reg = CM_PWMDIV,
  68         .int_bits = 12,
  69         .frac_bits = 12,
  70 +       .is_mash_clock = true,
  71  };
  72
  73  struct bcm2835_pll {
  74 @@ -1183,7 +1187,7 @@ static u32 bcm2835_clock_choose_div(stru
  75                 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
  76         u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
  77         u64 rem;
  78 -       u32 div;
  79 +       u32 div, mindiv, maxdiv;
  80
  81         rem = do_div(temp, rate);
  82         div = temp;
  83 @@ -1193,11 +1197,23 @@ static u32 bcm2835_clock_choose_div(stru
  84                 div += unused_frac_mask + 1;
  85         div &= ~unused_frac_mask;
  86
  87 -       /* clamp to min divider of 1 */
  88 -       div = max_t(u32, div, 1 << CM_DIV_FRAC_BITS);
  89 -       /* clamp to the highest possible fractional divider */
  90 -       div = min_t(u32, div, GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
  91 -                                     CM_DIV_FRAC_BITS - data->frac_bits));
  92 +       /* different clamping limits apply for a mash clock */
  93 +       if (data->is_mash_clock) {
  94 +               /* clamp to min divider of 2 */
  95 +               mindiv = 2 << CM_DIV_FRAC_BITS;
  96 +               /* clamp to the highest possible integer divider */
  97 +               maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS;
  98 +       } else {
  99 +               /* clamp to min divider of 1 */
 100 +               mindiv = 1 << CM_DIV_FRAC_BITS;
 101 +               /* clamp to the highest possible fractional divider */
 102 +               maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
 103 +                                CM_DIV_FRAC_BITS - data->frac_bits);
 104 +       }
 105 +
 106 +       /* apply the clamping  limits */
 107 +       div = max_t(u32, div, mindiv);
 108 +       div = min_t(u32, div, maxdiv);
 109
 110         return div;
 111  }
 112 @@ -1291,9 +1307,26 @@ static int bcm2835_clock_set_rate(struct
 113         struct bcm2835_cprman *cprman = clock->cprman;
 114         const struct bcm2835_clock_data *data = clock->data;
 115         u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false);
 116 +       u32 ctl;
 117 +
 118 +       spin_lock(&cprman->regs_lock);
 119 +
 120 +       /*
 121 +        * Setting up frac support
 122 +        *
 123 +        * In principle it is recommended to stop/start the clock first,
 124 +        * but as we set CLK_SET_RATE_GATE during registration of the
 125 +        * clock this requirement should be take care of by the
 126 +        * clk-framework.
 127 +        */
 128 +       ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
 129 +       ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
 130 +       cprman_write(cprman, data->ctl_reg, ctl);
 131
 132         cprman_write(cprman, data->div_reg, div);
 133
 134 +       spin_unlock(&cprman->regs_lock);
 135 +
 136         return 0;
 137  }
 138