releases/4.8.5/arm64-kernel-init-mdcr_el2-even-in-the-absence-of-a-pmu.patch

   1 From 850540351bb1a4fa5f192e5ce55b89928cc57f42 Mon Sep 17 00:00:00 2001
   2 From: Marc Zyngier <marc.zyngier@arm.com>
   3 Date: Mon, 17 Oct 2016 13:47:34 +0100
   4 Subject: arm64: kernel: Init MDCR_EL2 even in the absence of a PMU
   5
   6 From: Marc Zyngier <marc.zyngier@arm.com>
   7
   8 commit 850540351bb1a4fa5f192e5ce55b89928cc57f42 upstream.
   9
  10 Commit f436b2ac90a0 ("arm64: kernel: fix architected PMU registers
  11 unconditional access") made sure we wouldn't access unimplemented
  12 PMU registers, but also left MDCR_EL2 uninitialized in that case,
  13 leading to trap bits being potentially left set.
  14
  15 Make sure we always write something in that register.
  16
  17 Fixes: f436b2ac90a0 ("arm64: kernel: fix architected PMU registers unconditional access")
  18 Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  19 Cc: Will Deacon <will.deacon@arm.com>
  20 Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
  21 Signed-off-by: Will Deacon <will.deacon@arm.com>
  22 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  23
  24 ---
  25  arch/arm64/kernel/head.S |    3 ++-
  26  1 file changed, 2 insertions(+), 1 deletion(-)
  27
  28 --- a/arch/arm64/kernel/head.S
  29 +++ b/arch/arm64/kernel/head.S
  30 @@ -578,8 +578,9 @@ CPU_LE(     movk    x0, #0x30d0, lsl #16    )       // C
  31         b.lt    4f                              // Skip if no PMU present
  32         mrs     x0, pmcr_el0                    // Disable debug access traps
  33         ubfx    x0, x0, #11, #5                 // to EL2 and allow access to
  34 -       msr     mdcr_el2, x0                    // all PMU counters from EL1
  35  4:
  36 +       csel    x0, xzr, x0, lt                 // all PMU counters from EL1
  37 +       msr     mdcr_el2, x0                    // (if they exist)
  38
  39         /* Stage-2 translation */
  40         msr     vttbr_el2, xzr