releases/4.9.165/powerpc-83xx-also-save-restore-sprg4-7-during-suspend.patch

   1 From 36da5ff0bea2dc67298150ead8d8471575c54c7d Mon Sep 17 00:00:00 2001
   2 From: Christophe Leroy <christophe.leroy@c-s.fr>
   3 Date: Fri, 25 Jan 2019 12:03:55 +0000
   4 Subject: powerpc/83xx: Also save/restore SPRG4-7 during suspend
   5
   6 From: Christophe Leroy <christophe.leroy@c-s.fr>
   7
   8 commit 36da5ff0bea2dc67298150ead8d8471575c54c7d upstream.
   9
  10 The 83xx has 8 SPRG registers and uses at least SPRG4
  11 for DTLB handling LRU.
  12
  13 Fixes: 2319f1239592 ("powerpc/mm: e300c2/c3/c4 TLB errata workaround")
  14 Cc: stable@vger.kernel.org
  15 Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
  16 Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
  17 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  18
  19 ---
  20  arch/powerpc/platforms/83xx/suspend-asm.S |   34 +++++++++++++++++++++++-------
  21  1 file changed, 27 insertions(+), 7 deletions(-)
  22
  23 --- a/arch/powerpc/platforms/83xx/suspend-asm.S
  24 +++ b/arch/powerpc/platforms/83xx/suspend-asm.S
  25 @@ -26,13 +26,13 @@
  26  #define SS_MSR         0x74
  27  #define SS_SDR1                0x78
  28  #define SS_LR          0x7c
  29 -#define SS_SPRG                0x80 /* 4 SPRGs */
  30 -#define SS_DBAT                0x90 /* 8 DBATs */
  31 -#define SS_IBAT                0xd0 /* 8 IBATs */
  32 -#define SS_TB          0x110
  33 -#define SS_CR          0x118
  34 -#define SS_GPREG       0x11c /* r12-r31 */
  35 -#define STATE_SAVE_SIZE 0x16c
  36 +#define SS_SPRG                0x80 /* 8 SPRGs */
  37 +#define SS_DBAT                0xa0 /* 8 DBATs */
  38 +#define SS_IBAT                0xe0 /* 8 IBATs */
  39 +#define SS_TB          0x120
  40 +#define SS_CR          0x128
  41 +#define SS_GPREG       0x12c /* r12-r31 */
  42 +#define STATE_SAVE_SIZE 0x17c
  43
  44         .section .data
  45         .align  5
  46 @@ -103,6 +103,16 @@ _GLOBAL(mpc83xx_enter_deep_sleep)
  47         stw     r7, SS_SPRG+12(r3)
  48         stw     r8, SS_SDR1(r3)
  49
  50 +       mfspr   r4, SPRN_SPRG4
  51 +       mfspr   r5, SPRN_SPRG5
  52 +       mfspr   r6, SPRN_SPRG6
  53 +       mfspr   r7, SPRN_SPRG7
  54 +
  55 +       stw     r4, SS_SPRG+16(r3)
  56 +       stw     r5, SS_SPRG+20(r3)
  57 +       stw     r6, SS_SPRG+24(r3)
  58 +       stw     r7, SS_SPRG+28(r3)
  59 +
  60         mfspr   r4, SPRN_DBAT0U
  61         mfspr   r5, SPRN_DBAT0L
  62         mfspr   r6, SPRN_DBAT1U
  63 @@ -493,6 +503,16 @@ mpc83xx_deep_resume:
  64         mtspr   SPRN_IBAT7U, r6
  65         mtspr   SPRN_IBAT7L, r7
  66
  67 +       lwz     r4, SS_SPRG+16(r3)
  68 +       lwz     r5, SS_SPRG+20(r3)
  69 +       lwz     r6, SS_SPRG+24(r3)
  70 +       lwz     r7, SS_SPRG+28(r3)
  71 +
  72 +       mtspr   SPRN_SPRG4, r4
  73 +       mtspr   SPRN_SPRG5, r5
  74 +       mtspr   SPRN_SPRG6, r6
  75 +       mtspr   SPRN_SPRG7, r7
  76 +
  77         lwz     r4, SS_SPRG+0(r3)
  78         lwz     r5, SS_SPRG+4(r3)
  79         lwz     r6, SS_SPRG+8(r3)