releases/6.6.26/drm-i915-eliminate-is_mtl_graphics_step.patch

   1 From 9e5bb437a63dec8f1ea87ff52a23124c6939230c Mon Sep 17 00:00:00 2001
   2 From: Sasha Levin <sashal@kernel.org>
   3 Date: Mon, 21 Aug 2023 11:06:24 -0700
   4 Subject: drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
   5
   6 From: Matt Roper <matthew.d.roper@intel.com>
   7
   8 [ Upstream commit 5a213086a025349361b5cf75c8fd4591d96a7a99 ]
   9
  10 Several workarounds are guarded by IS_MTL_GRAPHICS_STEP.  However none
  11 of these workarounds are actually tied to MTL as a platform; they only
  12 relate to the Xe_LPG graphics IP, regardless of what platform it appears
  13 in.  At the moment MTL is the only platform that uses Xe_LPG with IP
  14 versions 12.70 and 12.71, but we can't count on this being true in the
  15 future.  Switch these to use a new IS_GFX_GT_IP_STEP() macro instead
  16 that is purely based on IP version.  IS_GFX_GT_IP_STEP() is also
  17 GT-based rather than device-based, which will help prevent mistakes
  18 where we accidentally try to apply Xe_LPG graphics workarounds to the
  19 Xe_LPM+ media GT and vice-versa.
  20
  21 v2:
  22  - Switch to a more generic and shorter IS_GT_IP_STEP macro that can be
  23    used for both graphics and media IP (and any other kind of GTs that
  24    show up in the future).
  25 v3:
  26  - Switch back to long-form IS_GFX_GT_IP_STEP macro.  (Jani)
  27  - Move macro to intel_gt.h.  (Andi)
  28 v4:
  29  - Build IS_GFX_GT_IP_STEP on top of IS_GFX_GT_IP_RANGE and
  30    IS_GRAPHICS_STEP building blocks and name the parameters from/until
  31    rather than begin/fixed.  (Jani)
  32  - Fix usage examples in comment.
  33 v5:
  34  - Tweak comment on macro.  (Gustavo)
  35
  36 Cc: Gustavo Sousa <gustavo.sousa@intel.com>
  37 Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
  38 Cc: Andi Shyti <andi.shyti@linux.intel.com>
  39 Cc: Jani Nikula <jani.nikula@linux.intel.com>
  40 Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
  41 Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
  42 Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
  43 Link: https://patchwork.freedesktop.org/patch/msgid/20230821180619.650007-15-matthew.d.roper@intel.com
  44 Stable-dep-of: 186bce682772 ("drm/i915/mtl: Update workaround 14018575942")
  45 Signed-off-by: Sasha Levin <sashal@kernel.org>
  46 ---
  47  .../drm/i915/display/skl_universal_plane.c    |  5 +-
  48  drivers/gpu/drm/i915/gt/gen8_engine_cs.c      | 11 +++--
  49  drivers/gpu/drm/i915/gt/intel_gt.h            | 20 ++++++++
  50  drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  7 ++-
  51  drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
  52  drivers/gpu/drm/i915/gt/intel_reset.c         |  2 +-
  53  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 48 ++++++++++---------
  54  drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  2 +-
  55  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  2 +-
  56  drivers/gpu/drm/i915/i915_drv.h               |  4 --
  57  10 files changed, 62 insertions(+), 43 deletions(-)
  58
  59 diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
  60 index ffc15d278a39d..d557ecd4e1ebe 100644
  61 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
  62 +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
  63 @@ -20,6 +20,7 @@
  64  #include "skl_scaler.h"
  65  #include "skl_universal_plane.h"
  66  #include "skl_watermark.h"
  67 +#include "gt/intel_gt.h"
  68  #include "pxp/intel_pxp.h"
  69
  70  static const u32 skl_plane_formats[] = {
  71 @@ -2169,8 +2170,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
  72                                  enum pipe pipe, enum plane_id plane_id)
  73  {
  74         /* Wa_14017240301 */
  75 -       if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
  76 -           IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
  77 +       if (IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 70), STEP_A0, STEP_B0) ||
  78 +           IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 71), STEP_A0, STEP_B0))
  79                 return false;
  80
  81         /* Wa_22011186057 */
  82 diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
  83 index 7ad36198aab2a..3ac3e12d9c524 100644
  84 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
  85 +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
  86 @@ -4,9 +4,9 @@
  87   */
  88
  89  #include "gen8_engine_cs.h"
  90 -#include "i915_drv.h"
  91  #include "intel_engine_regs.h"
  92  #include "intel_gpu_commands.h"
  93 +#include "intel_gt.h"
  94  #include "intel_lrc.h"
  95  #include "intel_ring.h"
  96
  97 @@ -226,8 +226,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs)
  98  static int mtl_dummy_pipe_control(struct i915_request *rq)
  99  {
 100         /* Wa_14016712196 */
 101 -       if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
 102 -           IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
 103 +       if (IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
 104 +           IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
 105                 u32 *cs;
 106
 107                 /* dummy PIPE_CONTROL + depth flush */
 108 @@ -808,6 +808,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
 109  u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
 110  {
 111         struct drm_i915_private *i915 = rq->i915;
 112 +       struct intel_gt *gt = rq->engine->gt;
 113         u32 flags = (PIPE_CONTROL_CS_STALL |
 114                      PIPE_CONTROL_TLB_INVALIDATE |
 115                      PIPE_CONTROL_TILE_CACHE_FLUSH |
 116 @@ -818,8 +819,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
 117                      PIPE_CONTROL_FLUSH_ENABLE);
 118
 119         /* Wa_14016712196 */
 120 -       if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
 121 -           IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
 122 +       if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
 123 +           IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
 124                 /* dummy PIPE_CONTROL + depth flush */
 125                 cs = gen12_emit_pipe_control(cs, 0,
 126                                              PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
 127 diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
 128 index 15c25980411db..6e63b46682f76 100644
 129 --- a/drivers/gpu/drm/i915/gt/intel_gt.h
 130 +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
 131 @@ -25,6 +25,26 @@ struct drm_printer;
 132          GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
 133          GRAPHICS_VER_FULL((gt)->i915) <= (until)))
 134
 135 +/*
 136 + * Check that the GT is a graphics GT with a specific IP version and has
 137 + * a stepping in the range [from, until).  The lower stepping bound is
 138 + * inclusive, the upper bound is exclusive.  The most common use-case of this
 139 + * macro is for checking bounds for workarounds, which usually have a stepping
 140 + * ("from") at which the hardware issue is first present and another stepping
 141 + * ("until") at which a hardware fix is present and the software workaround is
 142 + * no longer necessary.  E.g.,
 143 + *
 144 + *    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0)
 145 + *    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B1, STEP_FOREVER)
 146 + *
 147 + * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper
 148 + * stepping bound for the specified IP version.
 149 + */
 150 +#define IS_GFX_GT_IP_STEP(gt, ipver, from, until) ( \
 151 +       BUILD_BUG_ON_ZERO((until) <= (from)) + \
 152 +       (IS_GFX_GT_IP_RANGE((gt), (ipver), (ipver)) && \
 153 +        IS_GRAPHICS_STEP((gt)->i915, (from), (until))))
 154 +
 155  #define GT_TRACE(gt, fmt, ...) do {                                    \
 156         const struct intel_gt *gt__ __maybe_unused = (gt);              \
 157         GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev),             \
 158 diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
 159 index 2c0f1f3e28ff8..c6dec485aefbe 100644
 160 --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
 161 +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
 162 @@ -3,8 +3,7 @@
 163   * Copyright © 2022 Intel Corporation
 164   */
 165
 166 -#include "i915_drv.h"
 167 -
 168 +#include "intel_gt.h"
 169  #include "intel_gt_mcr.h"
 170  #include "intel_gt_print.h"
 171  #include "intel_gt_regs.h"
 172 @@ -166,8 +165,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
 173                 gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
 174         } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
 175                 /* Wa_14016747170 */
 176 -               if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
 177 -                   IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
 178 +               if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
 179 +                   IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
 180                         fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
 181                                              intel_uncore_read(gt->uncore,
 182                                                                MTL_GT_ACTIVITY_FACTOR));
 183 diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
 184 index f297c5808e7c8..b99efa348ad1e 100644
 185 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
 186 +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
 187 @@ -1347,8 +1347,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
 188         cs = gen12_emit_aux_table_inv(ce->engine, cs);
 189
 190         /* Wa_16014892111 */
 191 -       if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
 192 -           IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
 193 +       if (IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
 194 +           IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
 195             IS_DG2(ce->engine->i915))
 196                 cs = dg2_emit_draw_watermark_setting(cs);
 197
 198 diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
 199 index 3a3f71ce3cb77..63d0892d3c45a 100644
 200 --- a/drivers/gpu/drm/i915/gt/intel_reset.c
 201 +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
 202 @@ -1641,7 +1641,7 @@ bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
 203         if (GRAPHICS_VER(gt->i915) < 11)
 204                 return false;
 205
 206 -       if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
 207 +       if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0))
 208                 return true;
 209
 210         if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
 211 diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
 212 index 4c24f3897aee1..b6237e999be93 100644
 213 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
 214 +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
 215 @@ -784,24 +784,24 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
 216  static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
 217                                      struct i915_wa_list *wal)
 218  {
 219 -       struct drm_i915_private *i915 = engine->i915;
 220 +       struct intel_gt *gt = engine->gt;
 221
 222         dg2_ctx_gt_tuning_init(engine, wal);
 223
 224 -       if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
 225 -           IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
 226 +       if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
 227 +           IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
 228                 wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
 229  }
 230
 231  static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
 232                                        struct i915_wa_list *wal)
 233  {
 234 -       struct drm_i915_private *i915 = engine->i915;
 235 +       struct intel_gt *gt = engine->gt;
 236
 237         xelpg_ctx_gt_tuning_init(engine, wal);
 238
 239 -       if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
 240 -           IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
 241 +       if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
 242 +           IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
 243                 /* Wa_14014947963 */
 244                 wa_masked_field_set(wal, VF_PREEMPTION,
 245                                     PREEMPTION_VERTEX_COUNT, 0x4000);
 246 @@ -1644,8 +1644,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 247         /* Wa_22016670082 */
 248         wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
 249
 250 -       if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
 251 -           IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
 252 +       if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
 253 +           IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
 254                 /* Wa_14014830051 */
 255                 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
 256
 257 @@ -2297,23 +2297,24 @@ static void
 258  rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 259  {
 260         struct drm_i915_private *i915 = engine->i915;
 261 +       struct intel_gt *gt = engine->gt;
 262
 263 -       if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
 264 -           IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
 265 +       if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
 266 +           IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
 267                 /* Wa_22014600077 */
 268                 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
 269                                  ENABLE_EU_COUNT_FOR_TDL_FLUSH);
 270         }
 271
 272 -       if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
 273 -           IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
 274 +       if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
 275 +           IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
 276             IS_DG2(i915)) {
 277                 /* Wa_1509727124 */
 278                 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
 279                                  SC_DISABLE_POWER_OPTIMIZATION_EBB);
 280         }
 281
 282 -       if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
 283 +       if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
 284             IS_DG2(i915)) {
 285                 /* Wa_22012856258 */
 286                 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
 287 @@ -2829,8 +2830,9 @@ static void
 288  general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 289  {
 290         struct drm_i915_private *i915 = engine->i915;
 291 +       struct intel_gt *gt = engine->gt;
 292
 293 -       add_render_compute_tuning_settings(engine->gt, wal);
 294 +       add_render_compute_tuning_settings(gt, wal);
 295
 296         if (GRAPHICS_VER(i915) >= 11) {
 297                 /* This is not a Wa (although referred to as
 298 @@ -2851,13 +2853,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 299                                  GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
 300         }
 301
 302 -       if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
 303 -           IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
 304 +       if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
 305 +           IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
 306                 /* Wa_14017856879 */
 307                 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
 308
 309 -       if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
 310 -           IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
 311 +       if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
 312 +           IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
 313                 /*
 314                  * Wa_14017066071
 315                  * Wa_14017654203
 316 @@ -2865,13 +2867,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 317                 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
 318                                  MTL_DISABLE_SAMPLER_SC_OOO);
 319
 320 -       if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
 321 +       if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
 322                 /* Wa_22015279794 */
 323                 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
 324                                  DISABLE_PREFETCH_INTO_IC);
 325
 326 -       if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
 327 -           IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
 328 +       if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
 329 +           IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
 330             IS_DG2(i915)) {
 331                 /* Wa_22013037850 */
 332                 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
 333 @@ -2881,8 +2883,8 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 334                 wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
 335         }
 336
 337 -       if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
 338 -           IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
 339 +       if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
 340 +           IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
 341             IS_PONTEVECCHIO(i915) ||
 342             IS_DG2(i915)) {
 343                 /* Wa_22014226127 */
 344 diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
 345 index da967938fea58..861d0c58388cf 100644
 346 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
 347 +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
 348 @@ -273,7 +273,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
 349                 flags |= GUC_WA_POLLCS;
 350
 351         /* Wa_14014475959 */
 352 -       if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
 353 +       if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
 354             IS_DG2(gt->i915))
 355                 flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
 356
 357 diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
 358 index 7a3e02ea56639..b5de5a9f59671 100644
 359 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
 360 +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
 361 @@ -4297,7 +4297,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
 362
 363         /* Wa_14014475959:dg2 */
 364         if (engine->class == COMPUTE_CLASS)
 365 -               if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
 366 +               if (IS_GFX_GT_IP_STEP(engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
 367                     IS_DG2(engine->i915))
 368                         engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
 369
 370 diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
 371 index 7a8ce7239bc9e..e0e0493d6c1f0 100644
 372 --- a/drivers/gpu/drm/i915/i915_drv.h
 373 +++ b/drivers/gpu/drm/i915/i915_drv.h
 374 @@ -658,10 +658,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 375  #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
 376         (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
 377
 378 -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
 379 -       (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
 380 -        IS_GRAPHICS_STEP(__i915, since, until))
 381 -
 382  #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
 383         (IS_METEORLAKE(__i915) && \
 384          IS_DISPLAY_STEP(__i915, since, until))
 385 --
 386 2.43.0
 387