releases/6.6.26/drm-i915-tidy-workaround-definitions.patch

   1 From 65faed6ed2afa25e38d57dd8c0a25144228feeb7 Mon Sep 17 00:00:00 2001
   2 From: Sasha Levin <sashal@kernel.org>
   3 Date: Wed, 16 Aug 2023 14:42:06 -0700
   4 Subject: drm/i915: Tidy workaround definitions
   5
   6 From: Matt Roper <matthew.d.roper@intel.com>
   7
   8 [ Upstream commit f1c805716516f9e648e13f0108cea8096e0c7023 ]
   9
  10 Removal of the DG2 pre-production workarounds has left duplicate
  11 condition blocks in a couple places, as well as some inconsistent
  12 platform ordering.  Reshuffle and consolidate some of the workarounds to
  13 reduce the number of condition blocks and to more consistently follow
  14 the "newest platform first" convention.  Code movement only; no
  15 functional change.
  16
  17 Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
  18 Acked-by: Jani Nikula <jani.nikula@intel.com>
  19 Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
  20 Link: https://patchwork.freedesktop.org/patch/msgid/20230816214201.534095-11-matthew.d.roper@intel.com
  21 Stable-dep-of: 186bce682772 ("drm/i915/mtl: Update workaround 14018575942")
  22 Signed-off-by: Sasha Levin <sashal@kernel.org>
  23 ---
  24  drivers/gpu/drm/i915/gt/intel_workarounds.c | 100 +++++++++-----------
  25  1 file changed, 46 insertions(+), 54 deletions(-)
  26
  27 diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
  28 index 7b426f3015b34..69973dc518280 100644
  29 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
  30 +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
  31 @@ -2337,6 +2337,19 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
  32                            true);
  33         }
  34
  35 +       if (IS_DG2(i915) || IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
  36 +           IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
  37 +               /*
  38 +                * Wa_1606700617:tgl,dg1,adl-p
  39 +                * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p
  40 +                * Wa_14010826681:tgl,dg1,rkl,adl-p
  41 +                * Wa_18019627453:dg2
  42 +                */
  43 +               wa_masked_en(wal,
  44 +                            GEN9_CS_DEBUG_MODE1,
  45 +                            FF_DOP_CLOCK_GATE_DISABLE);
  46 +       }
  47 +
  48         if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
  49             IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
  50                 /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
  51 @@ -2350,19 +2363,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
  52                  */
  53                 wa_write_or(wal, GEN7_FF_THREAD_MODE,
  54                             GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
  55 -       }
  56
  57 -       if (IS_ALDERLAKE_P(i915) || IS_DG2(i915) || IS_ALDERLAKE_S(i915) ||
  58 -           IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
  59 -               /*
  60 -                * Wa_1606700617:tgl,dg1,adl-p
  61 -                * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p
  62 -                * Wa_14010826681:tgl,dg1,rkl,adl-p
  63 -                * Wa_18019627453:dg2
  64 -                */
  65 -               wa_masked_en(wal,
  66 -                            GEN9_CS_DEBUG_MODE1,
  67 -                            FF_DOP_CLOCK_GATE_DISABLE);
  68 +               /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */
  69 +               wa_mcr_masked_en(wal,
  70 +                                GEN10_SAMPLER_MODE,
  71 +                                ENABLE_SMALLPL);
  72         }
  73
  74         if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
  75 @@ -2389,14 +2394,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
  76                              GEN8_RC_SEMA_IDLE_MSG_DISABLE);
  77         }
  78
  79 -       if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) ||
  80 -           IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) {
  81 -               /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */
  82 -               wa_mcr_masked_en(wal,
  83 -                                GEN10_SAMPLER_MODE,
  84 -                                ENABLE_SMALLPL);
  85 -       }
  86 -
  87         if (GRAPHICS_VER(i915) == 11) {
  88                 /* This is not an Wa. Enable for better image quality */
  89                 wa_masked_en(wal,
  90 @@ -2877,6 +2874,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
  91                 /* Wa_22013037850 */
  92                 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
  93                                 DISABLE_128B_EVICTION_COMMAND_UDW);
  94 +
  95 +               /* Wa_18017747507 */
  96 +               wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
  97         }
  98
  99         if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
 100 @@ -2887,11 +2887,20 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 101                 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
 102         }
 103
 104 -       if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
 105 -           IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
 106 -           IS_DG2(i915)) {
 107 -               /* Wa_18017747507 */
 108 -               wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
 109 +       if (IS_PONTEVECCHIO(i915) || IS_DG2(i915)) {
 110 +               /* Wa_14015227452:dg2,pvc */
 111 +               wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
 112 +
 113 +               /* Wa_16015675438:dg2,pvc */
 114 +               wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
 115 +       }
 116 +
 117 +       if (IS_DG2(i915)) {
 118 +               /*
 119 +                * Wa_16011620976:dg2_g11
 120 +                * Wa_22015475538:dg2
 121 +                */
 122 +               wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
 123         }
 124
 125         if (IS_DG2_G11(i915)) {
 126 @@ -2906,6 +2915,18 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 127                 /* Wa_22013059131:dg2 */
 128                 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
 129                                 FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
 130 +
 131 +               /*
 132 +                * Wa_22012654132
 133 +                *
 134 +                * Note that register 0xE420 is write-only and cannot be read
 135 +                * back for verification on DG2 (due to Wa_14012342262), so
 136 +                * we need to explicitly skip the readback.
 137 +                */
 138 +               wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
 139 +                          _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
 140 +                          0 /* write-only, so skip validation */,
 141 +                          true);
 142         }
 143
 144         if (IS_XEHPSDV(i915)) {
 145 @@ -2923,35 +2944,6 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 146                 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
 147                                  GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
 148         }
 149 -
 150 -       if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) {
 151 -               /* Wa_14015227452:dg2,pvc */
 152 -               wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
 153 -
 154 -               /* Wa_16015675438:dg2,pvc */
 155 -               wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
 156 -       }
 157 -
 158 -       if (IS_DG2(i915)) {
 159 -               /*
 160 -                * Wa_16011620976:dg2_g11
 161 -                * Wa_22015475538:dg2
 162 -                */
 163 -               wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
 164 -       }
 165 -
 166 -       if (IS_DG2_G11(i915))
 167 -               /*
 168 -                * Wa_22012654132
 169 -                *
 170 -                * Note that register 0xE420 is write-only and cannot be read
 171 -                * back for verification on DG2 (due to Wa_14012342262), so
 172 -                * we need to explicitly skip the readback.
 173 -                */
 174 -               wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
 175 -                          _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
 176 -                          0 /* write-only, so skip validation */,
 177 -                          true);
 178  }
 179
 180  static void
 181 --
 182 2.43.0
 183