sim/arm/wrapper.c

   1 /* run front end support for arm
   2    Copyright (C) 1995-2022 Free Software Foundation, Inc.
   3
   4    This file is part of ARM SIM.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 /* This file provides the interface between the simulator and
  20    run.c and gdb (when the simulator is linked with gdb).
  21    All simulator interaction should go through this file.  */
  22
  23 /* This must come before any other includes.  */
  24 #include "defs.h"
  25
  26 #include <stdio.h>
  27 #include <stdarg.h>
  28 #include <stdlib.h>
  29 #include <string.h>
  30 #include <bfd.h>
  31 #include <signal.h>
  32 #include "sim/callback.h"
  33 #include "sim/sim.h"
  34 #include "sim-main.h"
  35 #include "sim-options.h"
  36 #include "armemu.h"
  37 #include "dbg_rdi.h"
  38 #include "ansidecl.h"
  39 #include "gdb/sim-arm.h"
  40 #include "gdb/signals.h"
  41 #include "libiberty.h"
  42 #include "iwmmxt.h"
  43 #include "maverick.h"
  44
  45 /* TODO: This should get pulled from the SIM_DESC.  */
  46 host_callback *sim_callback;
  47
  48 /* TODO: This should get merged into sim_cpu.  */
  49 struct ARMul_State *state;
  50
  51 /* Memory size in bytes.  */
  52 /* TODO: Memory should be converted to the common memory module.  */
  53 static int mem_size = (1 << 21);
  54
  55 int stop_simulator;
  56
  57 #include "dis-asm.h"
  58
  59 /* TODO: Tracing should be converted to common tracing module.  */
  60 int trace = 0;
  61 int disas = 0;
  62 int trace_funcs = 0;
  63
  64 static struct disassemble_info  info;
  65 static char opbuf[1000];
  66
  67 static int ATTRIBUTE_PRINTF (2, 3)
  68 op_printf (char *buf, const char *fmt, ...)
  69 {
  70   int ret;
  71   va_list ap;
  72
  73   va_start (ap, fmt);
  74   ret = vsprintf (opbuf + strlen (opbuf), fmt, ap);
  75   va_end (ap);
  76   return ret;
  77 }
  78
  79 static int ATTRIBUTE_PRINTF (3, 4)
  80 op_styled_printf (char *buf, enum disassembler_style style,
  81                   const char *fmt, ...)
  82 {
  83   int ret;
  84   va_list ap;
  85
  86   va_start (ap, fmt);
  87   ret = vsprintf (opbuf + strlen (opbuf), fmt, ap);
  88   va_end (ap);
  89   return ret;
  90 }
  91
  92 static int
  93 sim_dis_read (bfd_vma                     memaddr ATTRIBUTE_UNUSED,
  94               bfd_byte *                  ptr,
  95               unsigned int                length,
  96               struct disassemble_info *   info)
  97 {
  98   ARMword val = (ARMword) *((ARMword *) info->application_data);
  99
 100   while (length--)
 101     {
 102       * ptr ++ = val & 0xFF;
 103       val >>= 8;
 104     }
 105   return 0;
 106 }
 107
 108 void
 109 print_insn (ARMword instr)
 110 {
 111   int size;
 112   disassembler_ftype disassemble_fn;
 113
 114   opbuf[0] = 0;
 115   info.application_data = & instr;
 116   disassemble_fn = disassembler (bfd_arch_arm, 0, 0, NULL);
 117   size = disassemble_fn (0, & info);
 118   fprintf (stderr, " %*s\n", size, opbuf);
 119 }
 120
 121 static void
 122 init (void)
 123 {
 124   static int done;
 125
 126   if (!done)
 127     {
 128       ARMul_EmulateInit ();
 129       state = ARMul_NewState ();
 130       state->bigendSig = (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? HIGH : LOW);
 131       ARMul_MemoryInit (state, mem_size);
 132       ARMul_OSInit (state);
 133       state->verbose = 0;
 134       done = 1;
 135     }
 136 }
 137
 138 void
 139 ARMul_ConsolePrint (ARMul_State * state,
 140                     const char * format,
 141                     ...)
 142 {
 143   va_list ap;
 144
 145   if (state->verbose)
 146     {
 147       va_start (ap, format);
 148       vprintf (format, ap);
 149       va_end (ap);
 150     }
 151 }
 152
 153 int
 154 sim_write (SIM_DESC sd ATTRIBUTE_UNUSED,
 155            SIM_ADDR addr,
 156            const unsigned char * buffer,
 157            int size)
 158 {
 159   int i;
 160
 161   init ();
 162
 163   for (i = 0; i < size; i++)
 164     ARMul_SafeWriteByte (state, addr + i, buffer[i]);
 165
 166   return size;
 167 }
 168
 169 int
 170 sim_read (SIM_DESC sd ATTRIBUTE_UNUSED,
 171           SIM_ADDR addr,
 172           unsigned char * buffer,
 173           int size)
 174 {
 175   int i;
 176
 177   init ();
 178
 179   for (i = 0; i < size; i++)
 180     buffer[i] = ARMul_SafeReadByte (state, addr + i);
 181
 182   return size;
 183 }
 184
 185 int
 186 sim_stop (SIM_DESC sd ATTRIBUTE_UNUSED)
 187 {
 188   state->Emulate = STOP;
 189   stop_simulator = 1;
 190   return 1;
 191 }
 192
 193 void
 194 sim_resume (SIM_DESC sd ATTRIBUTE_UNUSED,
 195             int step,
 196             int siggnal ATTRIBUTE_UNUSED)
 197 {
 198   state->EndCondition = 0;
 199   stop_simulator = 0;
 200
 201   if (step)
 202     {
 203       state->Reg[15] = ARMul_DoInstr (state);
 204       if (state->EndCondition == 0)
 205         state->EndCondition = RDIError_BreakpointReached;
 206     }
 207   else
 208     {
 209       state->NextInstr = RESUME;        /* treat as PC change */
 210       state->Reg[15] = ARMul_DoProg (state);
 211     }
 212
 213   FLUSHPIPE;
 214 }
 215
 216 SIM_RC
 217 sim_create_inferior (SIM_DESC sd ATTRIBUTE_UNUSED,
 218                      struct bfd * abfd,
 219                      char * const *argv,
 220                      char * const *env)
 221 {
 222   int argvlen = 0;
 223   int mach;
 224   char * const *arg;
 225
 226   init ();
 227
 228   if (abfd != NULL)
 229     {
 230       ARMul_SetPC (state, bfd_get_start_address (abfd));
 231       mach = bfd_get_mach (abfd);
 232     }
 233   else
 234     {
 235       ARMul_SetPC (state, 0);   /* ??? */
 236       mach = 0;
 237     }
 238
 239 #ifdef MODET
 240   if (abfd != NULL && (bfd_get_start_address (abfd) & 1))
 241     SETT;
 242 #endif
 243
 244   switch (mach)
 245     {
 246     default:
 247       (*sim_callback->printf_filtered)
 248         (sim_callback,
 249          "Unknown machine type '%d'; please update sim_create_inferior.\n",
 250          mach);
 251       /* fall through */
 252
 253     case 0:
 254       /* We wouldn't set the machine type with earlier toolchains, so we
 255          explicitly select a processor capable of supporting all ARMs in
 256          32bit mode.  */
 257       ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_v6_Prop);
 258       break;
 259
 260 #if 1
 261     case bfd_mach_arm_6T2:
 262     case bfd_mach_arm_7:
 263     case bfd_mach_arm_7EM:
 264       ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_v6_Prop);
 265       break;
 266 #endif
 267
 268     case bfd_mach_arm_XScale:
 269       ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_v6_Prop);
 270       break;
 271
 272     case bfd_mach_arm_iWMMXt2:
 273     case bfd_mach_arm_iWMMXt:
 274       {
 275         extern int SWI_vector_installed;
 276         ARMword i;
 277
 278         if (! SWI_vector_installed)
 279           {
 280             /* Intialise the hardware vectors to zero.  */
 281             if (! SWI_vector_installed)
 282               for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
 283                 ARMul_WriteWord (state, i, 0);
 284
 285             /* ARM_WriteWord will have detected the write to the SWI vector,
 286                but we want SWI_vector_installed to remain at 0 so that thumb
 287                mode breakpoints will work.  */
 288             SWI_vector_installed = 0;
 289           }
 290       }
 291       ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_iWMMXt_Prop);
 292       break;
 293
 294     case bfd_mach_arm_ep9312:
 295       ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop);
 296       break;
 297
 298     case bfd_mach_arm_5:
 299       if (bfd_family_coff (abfd))
 300         {
 301           /* This is a special case in order to support COFF based ARM toolchains.
 302              The COFF header does not have enough room to store all the different
 303              kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
 304              to v5.  (See coff_set_flags() in bdf/coffcode.h).  So if we see a v5
 305              machine type here, we assume it could be any of the above architectures
 306              and so select the most feature-full.  */
 307           ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
 308           break;
 309         }
 310       /* Otherwise drop through.  */
 311
 312     case bfd_mach_arm_5T:
 313       ARMul_SelectProcessor (state, ARM_v5_Prop);
 314       break;
 315
 316     case bfd_mach_arm_5TE:
 317       ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop);
 318       break;
 319
 320     case bfd_mach_arm_4:
 321     case bfd_mach_arm_4T:
 322       ARMul_SelectProcessor (state, ARM_v4_Prop);
 323       break;
 324
 325     case bfd_mach_arm_3:
 326     case bfd_mach_arm_3M:
 327       ARMul_SelectProcessor (state, ARM_Lock_Prop);
 328       break;
 329
 330     case bfd_mach_arm_2:
 331     case bfd_mach_arm_2a:
 332       ARMul_SelectProcessor (state, ARM_Fix26_Prop);
 333       break;
 334     }
 335
 336   memset (& info, 0, sizeof (info));
 337   INIT_DISASSEMBLE_INFO (info, stdout, op_printf, op_styled_printf);
 338   info.read_memory_func = sim_dis_read;
 339   info.arch = bfd_get_arch (abfd);
 340   info.mach = bfd_get_mach (abfd);
 341   info.endian_code = BFD_ENDIAN_LITTLE;
 342   if (info.mach == 0)
 343     info.arch = bfd_arch_arm;
 344   disassemble_init_for_target (& info);
 345
 346   if (argv != NULL)
 347     {
 348       /* Set up the command line by laboriously stringing together
 349          the environment carefully picked apart by our caller.  */
 350
 351       /* Free any old stuff.  */
 352       if (state->CommandLine != NULL)
 353         {
 354           free (state->CommandLine);
 355           state->CommandLine = NULL;
 356         }
 357
 358       /* See how much we need.  */
 359       for (arg = argv; *arg != NULL; arg++)
 360         argvlen += strlen (*arg) + 1;
 361
 362       /* Allocate it.  */
 363       state->CommandLine = malloc (argvlen + 1);
 364       if (state->CommandLine != NULL)
 365         {
 366           arg = argv;
 367           state->CommandLine[0] = '\0';
 368
 369           for (arg = argv; *arg != NULL; arg++)
 370             {
 371               strcat (state->CommandLine, *arg);
 372               strcat (state->CommandLine, " ");
 373             }
 374         }
 375     }
 376
 377   if (env != NULL)
 378     {
 379       /* Now see if there's a MEMSIZE spec in the environment.  */
 380       while (*env)
 381         {
 382           if (strncmp (*env, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0)
 383             {
 384               char *end_of_num;
 385
 386               /* Set up memory limit.  */
 387               state->MemSize =
 388                 strtoul (*env + sizeof ("MEMSIZE=") - 1, &end_of_num, 0);
 389             }
 390           env++;
 391         }
 392     }
 393
 394   return SIM_RC_OK;
 395 }
 396
 397 static int
 398 frommem (struct ARMul_State *state, unsigned char *memory)
 399 {
 400   if (state->bigendSig == HIGH)
 401     return (memory[0] << 24) | (memory[1] << 16)
 402       | (memory[2] << 8) | (memory[3] << 0);
 403   else
 404     return (memory[3] << 24) | (memory[2] << 16)
 405       | (memory[1] << 8) | (memory[0] << 0);
 406 }
 407
 408 static void
 409 tomem (struct ARMul_State *state,
 410        unsigned char *memory,
 411        int val)
 412 {
 413   if (state->bigendSig == HIGH)
 414     {
 415       memory[0] = val >> 24;
 416       memory[1] = val >> 16;
 417       memory[2] = val >> 8;
 418       memory[3] = val >> 0;
 419     }
 420   else
 421     {
 422       memory[3] = val >> 24;
 423       memory[2] = val >> 16;
 424       memory[1] = val >> 8;
 425       memory[0] = val >> 0;
 426     }
 427 }
 428
 429 static int
 430 arm_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
 431 {
 432   init ();
 433
 434   switch ((enum sim_arm_regs) rn)
 435     {
 436     case SIM_ARM_R0_REGNUM:
 437     case SIM_ARM_R1_REGNUM:
 438     case SIM_ARM_R2_REGNUM:
 439     case SIM_ARM_R3_REGNUM:
 440     case SIM_ARM_R4_REGNUM:
 441     case SIM_ARM_R5_REGNUM:
 442     case SIM_ARM_R6_REGNUM:
 443     case SIM_ARM_R7_REGNUM:
 444     case SIM_ARM_R8_REGNUM:
 445     case SIM_ARM_R9_REGNUM:
 446     case SIM_ARM_R10_REGNUM:
 447     case SIM_ARM_R11_REGNUM:
 448     case SIM_ARM_R12_REGNUM:
 449     case SIM_ARM_R13_REGNUM:
 450     case SIM_ARM_R14_REGNUM:
 451     case SIM_ARM_R15_REGNUM: /* PC */
 452     case SIM_ARM_FP0_REGNUM:
 453     case SIM_ARM_FP1_REGNUM:
 454     case SIM_ARM_FP2_REGNUM:
 455     case SIM_ARM_FP3_REGNUM:
 456     case SIM_ARM_FP4_REGNUM:
 457     case SIM_ARM_FP5_REGNUM:
 458     case SIM_ARM_FP6_REGNUM:
 459     case SIM_ARM_FP7_REGNUM:
 460     case SIM_ARM_FPS_REGNUM:
 461       ARMul_SetReg (state, state->Mode, rn, frommem (state, memory));
 462       break;
 463
 464     case SIM_ARM_PS_REGNUM:
 465       state->Cpsr = frommem (state, memory);
 466       ARMul_CPSRAltered (state);
 467       break;
 468
 469     case SIM_ARM_MAVERIC_COP0R0_REGNUM:
 470     case SIM_ARM_MAVERIC_COP0R1_REGNUM:
 471     case SIM_ARM_MAVERIC_COP0R2_REGNUM:
 472     case SIM_ARM_MAVERIC_COP0R3_REGNUM:
 473     case SIM_ARM_MAVERIC_COP0R4_REGNUM:
 474     case SIM_ARM_MAVERIC_COP0R5_REGNUM:
 475     case SIM_ARM_MAVERIC_COP0R6_REGNUM:
 476     case SIM_ARM_MAVERIC_COP0R7_REGNUM:
 477     case SIM_ARM_MAVERIC_COP0R8_REGNUM:
 478     case SIM_ARM_MAVERIC_COP0R9_REGNUM:
 479     case SIM_ARM_MAVERIC_COP0R10_REGNUM:
 480     case SIM_ARM_MAVERIC_COP0R11_REGNUM:
 481     case SIM_ARM_MAVERIC_COP0R12_REGNUM:
 482     case SIM_ARM_MAVERIC_COP0R13_REGNUM:
 483     case SIM_ARM_MAVERIC_COP0R14_REGNUM:
 484     case SIM_ARM_MAVERIC_COP0R15_REGNUM:
 485       memcpy (& DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
 486               memory, sizeof (struct maverick_regs));
 487       return sizeof (struct maverick_regs);
 488
 489     case SIM_ARM_MAVERIC_DSPSC_REGNUM:
 490       memcpy (&DSPsc, memory, sizeof DSPsc);
 491       return sizeof DSPsc;
 492
 493     case SIM_ARM_IWMMXT_COP0R0_REGNUM:
 494     case SIM_ARM_IWMMXT_COP0R1_REGNUM:
 495     case SIM_ARM_IWMMXT_COP0R2_REGNUM:
 496     case SIM_ARM_IWMMXT_COP0R3_REGNUM:
 497     case SIM_ARM_IWMMXT_COP0R4_REGNUM:
 498     case SIM_ARM_IWMMXT_COP0R5_REGNUM:
 499     case SIM_ARM_IWMMXT_COP0R6_REGNUM:
 500     case SIM_ARM_IWMMXT_COP0R7_REGNUM:
 501     case SIM_ARM_IWMMXT_COP0R8_REGNUM:
 502     case SIM_ARM_IWMMXT_COP0R9_REGNUM:
 503     case SIM_ARM_IWMMXT_COP0R10_REGNUM:
 504     case SIM_ARM_IWMMXT_COP0R11_REGNUM:
 505     case SIM_ARM_IWMMXT_COP0R12_REGNUM:
 506     case SIM_ARM_IWMMXT_COP0R13_REGNUM:
 507     case SIM_ARM_IWMMXT_COP0R14_REGNUM:
 508     case SIM_ARM_IWMMXT_COP0R15_REGNUM:
 509     case SIM_ARM_IWMMXT_COP1R0_REGNUM:
 510     case SIM_ARM_IWMMXT_COP1R1_REGNUM:
 511     case SIM_ARM_IWMMXT_COP1R2_REGNUM:
 512     case SIM_ARM_IWMMXT_COP1R3_REGNUM:
 513     case SIM_ARM_IWMMXT_COP1R4_REGNUM:
 514     case SIM_ARM_IWMMXT_COP1R5_REGNUM:
 515     case SIM_ARM_IWMMXT_COP1R6_REGNUM:
 516     case SIM_ARM_IWMMXT_COP1R7_REGNUM:
 517     case SIM_ARM_IWMMXT_COP1R8_REGNUM:
 518     case SIM_ARM_IWMMXT_COP1R9_REGNUM:
 519     case SIM_ARM_IWMMXT_COP1R10_REGNUM:
 520     case SIM_ARM_IWMMXT_COP1R11_REGNUM:
 521     case SIM_ARM_IWMMXT_COP1R12_REGNUM:
 522     case SIM_ARM_IWMMXT_COP1R13_REGNUM:
 523     case SIM_ARM_IWMMXT_COP1R14_REGNUM:
 524     case SIM_ARM_IWMMXT_COP1R15_REGNUM:
 525       return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
 526
 527     default:
 528       return 0;
 529     }
 530
 531   return length;
 532 }
 533
 534 static int
 535 arm_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
 536 {
 537   ARMword regval;
 538   int len = length;
 539
 540   init ();
 541
 542   switch ((enum sim_arm_regs) rn)
 543     {
 544     case SIM_ARM_R0_REGNUM:
 545     case SIM_ARM_R1_REGNUM:
 546     case SIM_ARM_R2_REGNUM:
 547     case SIM_ARM_R3_REGNUM:
 548     case SIM_ARM_R4_REGNUM:
 549     case SIM_ARM_R5_REGNUM:
 550     case SIM_ARM_R6_REGNUM:
 551     case SIM_ARM_R7_REGNUM:
 552     case SIM_ARM_R8_REGNUM:
 553     case SIM_ARM_R9_REGNUM:
 554     case SIM_ARM_R10_REGNUM:
 555     case SIM_ARM_R11_REGNUM:
 556     case SIM_ARM_R12_REGNUM:
 557     case SIM_ARM_R13_REGNUM:
 558     case SIM_ARM_R14_REGNUM:
 559     case SIM_ARM_R15_REGNUM: /* PC */
 560       regval = ARMul_GetReg (state, state->Mode, rn);
 561       break;
 562
 563     case SIM_ARM_FP0_REGNUM:
 564     case SIM_ARM_FP1_REGNUM:
 565     case SIM_ARM_FP2_REGNUM:
 566     case SIM_ARM_FP3_REGNUM:
 567     case SIM_ARM_FP4_REGNUM:
 568     case SIM_ARM_FP5_REGNUM:
 569     case SIM_ARM_FP6_REGNUM:
 570     case SIM_ARM_FP7_REGNUM:
 571     case SIM_ARM_FPS_REGNUM:
 572       memset (memory, 0, length);
 573       return 0;
 574
 575     case SIM_ARM_PS_REGNUM:
 576       regval = ARMul_GetCPSR (state);
 577       break;
 578
 579     case SIM_ARM_MAVERIC_COP0R0_REGNUM:
 580     case SIM_ARM_MAVERIC_COP0R1_REGNUM:
 581     case SIM_ARM_MAVERIC_COP0R2_REGNUM:
 582     case SIM_ARM_MAVERIC_COP0R3_REGNUM:
 583     case SIM_ARM_MAVERIC_COP0R4_REGNUM:
 584     case SIM_ARM_MAVERIC_COP0R5_REGNUM:
 585     case SIM_ARM_MAVERIC_COP0R6_REGNUM:
 586     case SIM_ARM_MAVERIC_COP0R7_REGNUM:
 587     case SIM_ARM_MAVERIC_COP0R8_REGNUM:
 588     case SIM_ARM_MAVERIC_COP0R9_REGNUM:
 589     case SIM_ARM_MAVERIC_COP0R10_REGNUM:
 590     case SIM_ARM_MAVERIC_COP0R11_REGNUM:
 591     case SIM_ARM_MAVERIC_COP0R12_REGNUM:
 592     case SIM_ARM_MAVERIC_COP0R13_REGNUM:
 593     case SIM_ARM_MAVERIC_COP0R14_REGNUM:
 594     case SIM_ARM_MAVERIC_COP0R15_REGNUM:
 595       memcpy (memory, & DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
 596               sizeof (struct maverick_regs));
 597       return sizeof (struct maverick_regs);
 598
 599     case SIM_ARM_MAVERIC_DSPSC_REGNUM:
 600       memcpy (memory, & DSPsc, sizeof DSPsc);
 601       return sizeof DSPsc;
 602
 603     case SIM_ARM_IWMMXT_COP0R0_REGNUM:
 604     case SIM_ARM_IWMMXT_COP0R1_REGNUM:
 605     case SIM_ARM_IWMMXT_COP0R2_REGNUM:
 606     case SIM_ARM_IWMMXT_COP0R3_REGNUM:
 607     case SIM_ARM_IWMMXT_COP0R4_REGNUM:
 608     case SIM_ARM_IWMMXT_COP0R5_REGNUM:
 609     case SIM_ARM_IWMMXT_COP0R6_REGNUM:
 610     case SIM_ARM_IWMMXT_COP0R7_REGNUM:
 611     case SIM_ARM_IWMMXT_COP0R8_REGNUM:
 612     case SIM_ARM_IWMMXT_COP0R9_REGNUM:
 613     case SIM_ARM_IWMMXT_COP0R10_REGNUM:
 614     case SIM_ARM_IWMMXT_COP0R11_REGNUM:
 615     case SIM_ARM_IWMMXT_COP0R12_REGNUM:
 616     case SIM_ARM_IWMMXT_COP0R13_REGNUM:
 617     case SIM_ARM_IWMMXT_COP0R14_REGNUM:
 618     case SIM_ARM_IWMMXT_COP0R15_REGNUM:
 619     case SIM_ARM_IWMMXT_COP1R0_REGNUM:
 620     case SIM_ARM_IWMMXT_COP1R1_REGNUM:
 621     case SIM_ARM_IWMMXT_COP1R2_REGNUM:
 622     case SIM_ARM_IWMMXT_COP1R3_REGNUM:
 623     case SIM_ARM_IWMMXT_COP1R4_REGNUM:
 624     case SIM_ARM_IWMMXT_COP1R5_REGNUM:
 625     case SIM_ARM_IWMMXT_COP1R6_REGNUM:
 626     case SIM_ARM_IWMMXT_COP1R7_REGNUM:
 627     case SIM_ARM_IWMMXT_COP1R8_REGNUM:
 628     case SIM_ARM_IWMMXT_COP1R9_REGNUM:
 629     case SIM_ARM_IWMMXT_COP1R10_REGNUM:
 630     case SIM_ARM_IWMMXT_COP1R11_REGNUM:
 631     case SIM_ARM_IWMMXT_COP1R12_REGNUM:
 632     case SIM_ARM_IWMMXT_COP1R13_REGNUM:
 633     case SIM_ARM_IWMMXT_COP1R14_REGNUM:
 634     case SIM_ARM_IWMMXT_COP1R15_REGNUM:
 635       return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
 636
 637     default:
 638       return 0;
 639     }
 640
 641   while (len)
 642     {
 643       tomem (state, memory, regval);
 644
 645       len -= 4;
 646       memory += 4;
 647       regval = 0;
 648     }
 649
 650   return length;
 651 }
 652
 653 typedef struct
 654 {
 655   char *        swi_option;
 656   unsigned int  swi_mask;
 657 } swi_options;
 658
 659 #define SWI_SWITCH      "--swi-support"
 660
 661 static swi_options options[] =
 662   {
 663     { "none",    0 },
 664     { "demon",   SWI_MASK_DEMON },
 665     { "angel",   SWI_MASK_ANGEL },
 666     { "redboot", SWI_MASK_REDBOOT },
 667     { "all",     -1 },
 668     { "NONE",    0 },
 669     { "DEMON",   SWI_MASK_DEMON },
 670     { "ANGEL",   SWI_MASK_ANGEL },
 671     { "REDBOOT", SWI_MASK_REDBOOT },
 672     { "ALL",     -1 }
 673   };
 674
 675
 676 static int
 677 sim_target_parse_command_line (int argc, char ** argv)
 678 {
 679   int i;
 680
 681   for (i = 1; i < argc; i++)
 682     {
 683       char * ptr = argv[i];
 684       int arg;
 685
 686       if ((ptr == NULL) || (* ptr != '-'))
 687         break;
 688
 689       if (strcmp (ptr, "-t") == 0)
 690         {
 691           trace = 1;
 692           continue;
 693         }
 694
 695       if (strcmp (ptr, "-z") == 0)
 696         {
 697           /* Remove this option from the argv array.  */
 698           for (arg = i; arg < argc; arg ++)
 699             {
 700               free (argv[arg]);
 701               argv[arg] = argv[arg + 1];
 702             }
 703           argc --;
 704           i --;
 705           trace_funcs = 1;
 706           continue;
 707         }
 708
 709       if (strcmp (ptr, "-d") == 0)
 710         {
 711           /* Remove this option from the argv array.  */
 712           for (arg = i; arg < argc; arg ++)
 713             {
 714               free (argv[arg]);
 715               argv[arg] = argv[arg + 1];
 716             }
 717           argc --;
 718           i --;
 719           disas = 1;
 720           continue;
 721         }
 722
 723       if (strncmp (ptr, SWI_SWITCH, sizeof SWI_SWITCH - 1) != 0)
 724         continue;
 725
 726       if (ptr[sizeof SWI_SWITCH - 1] == 0)
 727         {
 728           /* Remove this option from the argv array.  */
 729           for (arg = i; arg < argc; arg ++)
 730             {
 731               free (argv[arg]);
 732               argv[arg] = argv[arg + 1];
 733             }
 734           argc --;
 735
 736           ptr = argv[i];
 737         }
 738       else
 739         ptr += sizeof SWI_SWITCH;
 740
 741       swi_mask = 0;
 742
 743       while (* ptr)
 744         {
 745           int i;
 746
 747           for (i = ARRAY_SIZE (options); i--;)
 748             if (strncmp (ptr, options[i].swi_option,
 749                          strlen (options[i].swi_option)) == 0)
 750               {
 751                 swi_mask |= options[i].swi_mask;
 752                 ptr += strlen (options[i].swi_option);
 753
 754                 if (* ptr == ',')
 755                   ++ ptr;
 756
 757                 break;
 758               }
 759
 760           if (i < 0)
 761             break;
 762         }
 763
 764       if (* ptr != 0)
 765         fprintf (stderr, "Ignoring swi options: %s\n", ptr);
 766
 767       /* Remove this option from the argv array.  */
 768       for (arg = i; arg < argc; arg ++)
 769         {
 770           free (argv[arg]);
 771           argv[arg] = argv[arg + 1];
 772         }
 773       argc --;
 774       i --;
 775     }
 776   return argc;
 777 }
 778
 779 static void
 780 sim_target_parse_arg_array (char ** argv)
 781 {
 782   sim_target_parse_command_line (countargv (argv), argv);
 783 }
 784
 785 static sim_cia
 786 arm_pc_get (sim_cpu *cpu)
 787 {
 788   return PC;
 789 }
 790
 791 static void
 792 arm_pc_set (sim_cpu *cpu, sim_cia pc)
 793 {
 794   ARMul_SetPC (state, pc);
 795 }
 796
 797 static void
 798 free_state (SIM_DESC sd)
 799 {
 800   if (STATE_MODULES (sd) != NULL)
 801     sim_module_uninstall (sd);
 802   sim_cpu_free_all (sd);
 803   sim_state_free (sd);
 804 }
 805
 806 SIM_DESC
 807 sim_open (SIM_OPEN_KIND kind,
 808           host_callback *cb,
 809           struct bfd *abfd,
 810           char * const *argv)
 811 {
 812   int i;
 813   char **argv_copy;
 814   SIM_DESC sd = sim_state_alloc (kind, cb);
 815   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
 816
 817   /* Set default options before parsing user options.  */
 818   current_alignment = STRICT_ALIGNMENT;
 819
 820   /* The cpu data is kept in a separately allocated chunk of memory.  */
 821   if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
 822     {
 823       free_state (sd);
 824       return 0;
 825     }
 826
 827   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
 828     {
 829       free_state (sd);
 830       return 0;
 831     }
 832
 833   /* The parser will print an error message for us, so we silently return.  */
 834   if (sim_parse_args (sd, argv) != SIM_RC_OK)
 835     {
 836       free_state (sd);
 837       return 0;
 838     }
 839
 840   /* Check for/establish the a reference program image.  */
 841   if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK)
 842     {
 843       free_state (sd);
 844       return 0;
 845     }
 846
 847   /* Configure/verify the target byte order and other runtime
 848      configuration options.  */
 849   if (sim_config (sd) != SIM_RC_OK)
 850     {
 851       sim_module_uninstall (sd);
 852       return 0;
 853     }
 854
 855   if (sim_post_argv_init (sd) != SIM_RC_OK)
 856     {
 857       /* Uninstall the modules to avoid memory leaks,
 858          file descriptor leaks, etc.  */
 859       sim_module_uninstall (sd);
 860       return 0;
 861     }
 862
 863   /* CPU specific initialization.  */
 864   for (i = 0; i < MAX_NR_PROCESSORS; ++i)
 865     {
 866       SIM_CPU *cpu = STATE_CPU (sd, i);
 867
 868       CPU_REG_FETCH (cpu) = arm_reg_fetch;
 869       CPU_REG_STORE (cpu) = arm_reg_store;
 870       CPU_PC_FETCH (cpu) = arm_pc_get;
 871       CPU_PC_STORE (cpu) = arm_pc_set;
 872     }
 873
 874   sim_callback = cb;
 875
 876   /* Copy over the argv contents so we can modify them.  */
 877   argv_copy = dupargv (argv);
 878
 879   sim_target_parse_arg_array (argv_copy);
 880
 881   if (argv_copy[1] != NULL)
 882     {
 883       int i;
 884
 885       /* Scan for memory-size switches.  */
 886       for (i = 0; (argv_copy[i] != NULL) && (argv_copy[i][0] != 0); i++)
 887         if (argv_copy[i][0] == '-' && argv_copy[i][1] == 'm')
 888           {
 889             if (argv_copy[i][2] != '\0')
 890               mem_size = atoi (&argv_copy[i][2]);
 891             else if (argv_copy[i + 1] != NULL)
 892               {
 893                 mem_size = atoi (argv_copy[i + 1]);
 894                 i++;
 895               }
 896             else
 897               {
 898                 sim_callback->printf_filtered (sim_callback,
 899                                                "Missing argument to -m option\n");
 900                 return NULL;
 901               }
 902           }
 903     }
 904
 905   freeargv (argv_copy);
 906
 907   return sd;
 908 }
 909
 910 void
 911 sim_stop_reason (SIM_DESC sd ATTRIBUTE_UNUSED,
 912                  enum sim_stop *reason,
 913                  int *sigrc)
 914 {
 915   if (stop_simulator)
 916     {
 917       *reason = sim_stopped;
 918       *sigrc = GDB_SIGNAL_INT;
 919     }
 920   else if (state->EndCondition == 0)
 921     {
 922       *reason = sim_exited;
 923       *sigrc = state->Reg[0] & 255;
 924     }
 925   else
 926     {
 927       *reason = sim_stopped;
 928       if (state->EndCondition == RDIError_BreakpointReached)
 929         *sigrc = GDB_SIGNAL_TRAP;
 930       else if (   state->EndCondition == RDIError_DataAbort
 931                || state->EndCondition == RDIError_AddressException)
 932         *sigrc = GDB_SIGNAL_BUS;
 933       else
 934         *sigrc = 0;
 935     }
 936 }