]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/d10v/interp.c
5 #include "remote-sim.h"
9 #define IMEM_SIZE 18 /* D10V instruction memory size is 18 bits */
10 #define DMEM_SIZE 16 /* Data memory is 64K (but only 32K internal RAM) */
11 #define UMEM_SIZE 17 /* Each unified memory segment is 17 bits */
12 #define UMEM_SEGMENTS 128 /* Number of segments in unified memory region */
14 enum _leftright
{ LEFT_FIRST
, RIGHT_FIRST
};
17 static SIM_OPEN_KIND sim_kind
;
19 host_callback
*d10v_callback
;
20 unsigned long ins_type_counters
[ (int)INS_MAX
];
24 static int init_text_p
= 0;
25 /* non-zero if we opened prog_bfd */
26 static int prog_bfd_was_opened_p
;
32 static long hash
PARAMS ((long insn
, int format
));
33 static struct hash_entry
*lookup_hash
PARAMS ((uint32 ins
, int size
));
34 static void get_operands
PARAMS ((struct simops
*s
, uint32 ins
));
35 static void do_long
PARAMS ((uint32 ins
));
36 static void do_2_short
PARAMS ((uint16 ins1
, uint16 ins2
, enum _leftright leftright
));
37 static void do_parallel
PARAMS ((uint16 ins1
, uint16 ins2
));
38 static char *add_commas
PARAMS ((char *buf
, int sizeof_buf
, unsigned long value
));
39 extern void sim_set_profile
PARAMS ((int n
));
40 extern void sim_set_profile_size
PARAMS ((int n
));
43 #if defined(__GNUC__) && defined(__OPTIMIZE__)
44 #define INLINE __inline__
53 struct hash_entry
*next
;
60 struct hash_entry hash_table
[MAX_HASH
+1];
67 if (format
& LONG_OPCODE
)
68 return ((insn
& 0x3F000000) >> 24);
70 return((insn
& 0x7E00) >> 9);
73 INLINE
static struct hash_entry
*
74 lookup_hash (ins
, size
)
81 h
= &hash_table
[(ins
& 0x3F000000) >> 24];
83 h
= &hash_table
[(ins
& 0x7E00) >> 9];
85 while ((ins
& h
->mask
) != h
->opcode
|| h
->size
!= size
)
89 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR looking up hash for %x at PC %x\n",ins
, PC
);
98 get_operands (struct simops
*s
, uint32 ins
)
100 int i
, shift
, bits
, flags
;
102 for (i
=0; i
< s
->numops
; i
++)
104 shift
= s
->operands
[3*i
];
105 bits
= s
->operands
[3*i
+1];
106 flags
= s
->operands
[3*i
+2];
107 mask
= 0x7FFFFFFF >> (31 - bits
);
108 OP
[i
] = (ins
>> shift
) & mask
;
116 if (!init_text_p
&& prog_bfd
!= NULL
)
119 for (s
= prog_bfd
->sections
; s
; s
= s
->next
)
120 if (strcmp (bfd_get_section_name (prog_bfd
, s
), ".text") == 0)
123 text_start
= bfd_get_section_vma (prog_bfd
, s
);
124 text_end
= text_start
+ bfd_section_size (prog_bfd
, s
);
129 return (PC
<< 2) + text_start
;
136 struct hash_entry
*h
;
138 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
139 (*d10v_callback
->printf_filtered
) (d10v_callback
, "do_long 0x%x\n", ins
);
141 h
= lookup_hash (ins
, 1);
142 get_operands (h
->ops
, ins
);
143 State
.ins_type
= INS_LONG
;
144 ins_type_counters
[ (int)State
.ins_type
]++;
149 do_2_short (ins1
, ins2
, leftright
)
151 enum _leftright leftright
;
153 struct hash_entry
*h
;
155 enum _ins_type first
, second
;
158 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
159 (*d10v_callback
->printf_filtered
) (d10v_callback
, "do_2_short 0x%x (%s) -> 0x%x\n",
160 ins1
, (leftright
) ? "left" : "right", ins2
);
163 if (leftright
== LEFT_FIRST
)
167 ins_type_counters
[ (int)INS_LEFTRIGHT
]++;
173 ins_type_counters
[ (int)INS_RIGHTLEFT
]++;
176 h
= lookup_hash (ins1
, 0);
177 get_operands (h
->ops
, ins1
);
178 State
.ins_type
= first
;
179 ins_type_counters
[ (int)State
.ins_type
]++;
182 /* If the PC has changed (ie, a jump), don't do the second instruction */
183 if (orig_pc
== PC
&& !State
.exception
)
185 h
= lookup_hash (ins2
, 0);
186 get_operands (h
->ops
, ins2
);
187 State
.ins_type
= second
;
188 ins_type_counters
[ (int)State
.ins_type
]++;
189 ins_type_counters
[ (int)INS_CYCLES
]++;
192 else if (orig_pc
!= PC
&& !State
.exception
)
193 ins_type_counters
[ (int)INS_COND_JUMP
]++;
197 do_parallel (ins1
, ins2
)
200 struct hash_entry
*h1
, *h2
;
202 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
203 (*d10v_callback
->printf_filtered
) (d10v_callback
, "do_parallel 0x%x || 0x%x\n", ins1
, ins2
);
205 ins_type_counters
[ (int)INS_PARALLEL
]++;
206 h1
= lookup_hash (ins1
, 0);
207 h2
= lookup_hash (ins2
, 0);
209 if (h1
->ops
->exec_type
== PARONLY
)
211 get_operands (h1
->ops
, ins1
);
212 State
.ins_type
= INS_LEFT_COND_TEST
;
213 ins_type_counters
[ (int)State
.ins_type
]++;
217 ins_type_counters
[ (int)INS_COND_TRUE
]++;
218 get_operands (h2
->ops
, ins2
);
219 State
.ins_type
= INS_RIGHT_COND_EXE
;
220 ins_type_counters
[ (int)State
.ins_type
]++;
224 ins_type_counters
[ (int)INS_COND_FALSE
]++;
226 else if (h2
->ops
->exec_type
== PARONLY
)
228 get_operands (h2
->ops
, ins2
);
229 State
.ins_type
= INS_RIGHT_COND_TEST
;
230 ins_type_counters
[ (int)State
.ins_type
]++;
234 ins_type_counters
[ (int)INS_COND_TRUE
]++;
235 get_operands (h1
->ops
, ins1
);
236 State
.ins_type
= INS_LEFT_COND_EXE
;
237 ins_type_counters
[ (int)State
.ins_type
]++;
241 ins_type_counters
[ (int)INS_COND_FALSE
]++;
245 get_operands (h1
->ops
, ins1
);
246 State
.ins_type
= INS_LEFT_PARALLEL
;
247 ins_type_counters
[ (int)State
.ins_type
]++;
249 if (!State
.exception
)
251 get_operands (h2
->ops
, ins2
);
252 State
.ins_type
= INS_RIGHT_PARALLEL
;
253 ins_type_counters
[ (int)State
.ins_type
]++;
260 add_commas(buf
, sizeof_buf
, value
)
266 char *endbuf
= buf
+ sizeof_buf
- 1;
276 *--endbuf
= (value
% 10) + '0';
277 } while ((value
/= 10) != 0);
291 for (i
=0;i
<UMEM_SEGMENTS
;i
++)
295 free (State
.umem
[i
]);
296 State
.umem
[i
] = NULL
;
303 State
.imem
= (uint8
*)calloc(1,1<<IMEM_SIZE
);
304 State
.dmem
= (uint8
*)calloc(1,1<<DMEM_SIZE
);
305 for (i
=1;i
<(UMEM_SEGMENTS
-1);i
++)
306 State
.umem
[i
] = NULL
;
307 State
.umem
[0] = (uint8
*)calloc(1,1<<UMEM_SIZE
);
308 State
.umem
[1] = (uint8
*)calloc(1,1<<UMEM_SIZE
);
309 State
.umem
[2] = (uint8
*)calloc(1,1<<UMEM_SIZE
);
310 State
.umem
[UMEM_SEGMENTS
-1] = (uint8
*)calloc(1,1<<UMEM_SIZE
);
311 if (!State
.imem
|| !State
.dmem
|| !State
.umem
[0] || !State
.umem
[1] || !State
.umem
[2] || !State
.umem
[UMEM_SEGMENTS
-1] )
313 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Memory allocation failed.\n");
318 if ((d10v_debug
& DEBUG_MEMSIZE
) != 0)
321 (*d10v_callback
->printf_filtered
) (d10v_callback
,
322 "Allocated %s bytes instruction memory and\n",
323 add_commas (buffer
, sizeof (buffer
), (1UL<<IMEM_SIZE
)));
325 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %s bytes data memory.\n",
326 add_commas (buffer
, sizeof (buffer
), (1UL<<IMEM_SIZE
)));
331 /* Transfer data to/from simulated memory. Since a bug in either the
332 simulated program or in gdb or the simulator itself may cause a
333 bogus address to be passed in, we need to do some sanity checking
334 on addresses to make sure they are within bounds. When an address
335 fails the bounds check, treat it as a zero length read/write rather
336 than aborting the entire run. */
339 xfer_mem (SIM_ADDR addr
,
340 unsigned char *buffer
,
344 unsigned char *memory
;
345 int segment
= ((addr
>> 24) & 0xff);
346 addr
= (addr
& 0x00ffffff);
349 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
353 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_write %d bytes to 0x%02x:%06x\n", size
, segment
, addr
);
357 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_read %d bytes from 0x%2x:%6x\n", size
, segment
, addr
);
362 /* to access data, we use the following mapping
363 0x00xxxxxx: Logical data address segment (DMAP translated memory)
364 0x01xxxxxx: Logical instruction address segment (IMAP translated memory)
365 0x10xxxxxx: Physical data memory segment (On-chip data memory)
366 0x11xxxxxx: Physical instruction memory segment (On-chip insn memory)
367 0x12xxxxxx: Phisical unified memory segment (Unified memory)
372 case 0x00: /* DMAP translated memory */
375 for (byte
= 0; byte
< size
; byte
++)
377 uint8
*mem
= dmem_addr (addr
+ byte
);
388 case 0x01: /* IMAP translated memory */
391 for (byte
= 0; byte
< size
; byte
++)
393 uint8
*mem
= imem_addr (addr
+ byte
);
404 case 0x10: /* On-chip data memory */
406 addr
&= ((1 << DMEM_SIZE
) - 1);
407 if ((addr
+ size
) > (1 << DMEM_SIZE
))
409 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: data address 0x%x is outside range 0-0x%x.\n",
410 addr
+ size
- 1, (1 << DMEM_SIZE
) - 1);
413 memory
= State
.dmem
+ addr
;
417 case 0x11: /* On-chip insn memory */
419 addr
&= ((1 << IMEM_SIZE
) - 1);
420 if ((addr
+ size
) > (1 << IMEM_SIZE
))
422 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: instruction address 0x%x is outside range 0-0x%x.\n",
423 addr
+ size
- 1, (1 << IMEM_SIZE
) - 1);
426 memory
= State
.imem
+ addr
;
429 case 0x12: /* Unified memory */
431 int startsegment
, startoffset
; /* Segment and offset within segment where xfer starts */
432 int endsegment
, endoffset
; /* Segment and offset within segment where xfer ends */
434 startsegment
= addr
>> UMEM_SIZE
;
435 startoffset
= addr
& ((1 << UMEM_SIZE
) - 1);
436 endsegment
= (addr
+ size
) >> UMEM_SIZE
;
437 endoffset
= (addr
+ size
) & ((1 << UMEM_SIZE
) - 1);
439 /* FIXME: We do not currently implement xfers across segments,
440 so detect this case and fail gracefully. */
442 if ((startsegment
!= endsegment
) && !((endsegment
== (startsegment
+ 1)) && endoffset
== 0))
444 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: Unimplemented support for transfers across unified memory segment boundaries\n");
447 if (!State
.umem
[startsegment
])
450 if ((d10v_debug
& DEBUG_MEMSIZE
) != 0)
452 (*d10v_callback
->printf_filtered
) (d10v_callback
,"Allocating %s bytes unified memory to region %d\n",
453 add_commas (buffer
, sizeof (buffer
), (1UL<<IMEM_SIZE
)), startsegment
);
456 State
.umem
[startsegment
] = (uint8
*)calloc(1,1<<UMEM_SIZE
);
458 if (!State
.umem
[startsegment
])
460 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: Memory allocation of 0x%x bytes failed.\n", 1<<UMEM_SIZE
);
463 memory
= State
.umem
[startsegment
] + startoffset
;
469 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: address 0x%lx is not in valid range\n", (long) addr
);
470 (*d10v_callback
->printf_filtered
) (d10v_callback
, "0x00xxxxxx: Logical data address segment (DMAP translated memory)\n");
471 (*d10v_callback
->printf_filtered
) (d10v_callback
, "0x01xxxxxx: Logical instruction address segment (IMAP translated memory)\n");
472 (*d10v_callback
->printf_filtered
) (d10v_callback
, "0x10xxxxxx: Physical data memory segment (On-chip data memory)\n");
473 (*d10v_callback
->printf_filtered
) (d10v_callback
, "0x11xxxxxx: Physical instruction memory segment (On-chip insn memory)\n");
474 (*d10v_callback
->printf_filtered
) (d10v_callback
, "0x12xxxxxx: Phisical unified memory segment (Unified memory)\n");
481 memcpy (memory
, buffer
, size
);
485 memcpy (buffer
, memory
, size
);
493 sim_write (sd
, addr
, buffer
, size
)
496 unsigned char *buffer
;
499 /* FIXME: this should be performing a virtual transfer */
500 return xfer_mem( addr
, buffer
, size
, 1);
504 sim_read (sd
, addr
, buffer
, size
)
507 unsigned char *buffer
;
510 /* FIXME: this should be performing a virtual transfer */
511 return xfer_mem( addr
, buffer
, size
, 0);
516 sim_open (kind
, callback
, abfd
, argv
)
518 host_callback
*callback
;
523 struct hash_entry
*h
;
524 static int init_p
= 0;
528 d10v_callback
= callback
;
531 for (p
= argv
+ 1; *p
; ++p
)
534 if (strcmp (*p
, "-t") == 0)
538 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: unsupported option(s): %s\n",*p
);
541 /* put all the opcodes in the hash table */
544 for (s
= Simops
; s
->func
; s
++)
546 h
= &hash_table
[hash(s
->opcode
,s
->format
)];
548 /* go to the last entry in the chain */
554 h
->next
= (struct hash_entry
*) calloc(1,sizeof(struct hash_entry
));
556 perror ("malloc failure");
562 h
->opcode
= s
->opcode
;
563 h
->size
= s
->is_long
;
567 /* reset the processor state */
570 sim_create_inferior ((SIM_DESC
) 1, NULL
, NULL
, NULL
);
572 /* Fudge our descriptor. */
578 sim_close (sd
, quitting
)
582 if (prog_bfd
!= NULL
&& prog_bfd_was_opened_p
)
584 bfd_close (prog_bfd
);
586 prog_bfd_was_opened_p
= 0;
594 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_set_profile %d\n",n
);
598 sim_set_profile_size (n
)
601 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_set_profile_size %d\n",n
);
615 if ( (addr
& 0xfff0) != 0xff00)
617 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Data address 0x%lx is in I/O space, pc = 0x%lx.\n",
618 (long)addr
, (long)decode_pc ());
619 State
.exception
= SIGBUS
;
622 return State
.dmem
+ addr
;
629 /* instruction memory */
630 return (DMAP
& 0xf) * 0x4000 + State
.imem
;
633 /* this is ugly because we allocate unified memory in 128K segments and */
634 /* dmap addresses 16k segments */
635 seg
= (DMAP
& 0x3ff) >> 3;
636 if (State
.umem
[seg
] == NULL
)
638 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: unified memory region %d unmapped, pc = 0x%lx\n",
639 seg
, (long)decode_pc ());
640 State
.exception
= SIGBUS
;
642 return State
.umem
[seg
] + (DMAP
& 7) * 0x4000;
645 return State
.dmem
+ addr
;
650 imem_addr (uint32 pc
)
660 return State
.imem
+ pc
;
662 if (State
.umem
[imap
& 0xff] == NULL
)
665 /* Discard upper bit(s) of PC in case IMAP1 selects unified memory. */
666 pc
&= (1 << UMEM_SIZE
) - 1;
668 return State
.umem
[imap
& 0xff] + pc
;
672 static int stop_simulator
= 0;
683 /* Run (or resume) the program. */
685 sim_resume (sd
, step
, siggnal
)
693 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
700 iaddr
= imem_addr ((uint32
)PC
<< 2);
703 State
.exception
= SIGBUS
;
707 inst
= get_longword( iaddr
);
709 State
.pc_changed
= 0;
710 ins_type_counters
[ (int)INS_CYCLES
]++;
712 /* check to see if IBA should be triggered after
714 if (State
.DB
&& (PC
== IBA
))
719 switch (inst
& 0xC0000000)
722 /* long instruction */
723 do_long (inst
& 0x3FFFFFFF);
727 do_2_short ( inst
& 0x7FFF, (inst
& 0x3FFF8000) >> 15, RIGHT_FIRST
);
731 do_2_short ((inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF, LEFT_FIRST
);
734 do_parallel ((inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF);
738 /* calculate the next PC */
739 if (!State
.pc_changed
)
741 if (State
.RP
&& PC
== RPT_E
)
743 /* Note: The behavour of a branch instruction at RPT_E
744 is implementation dependant, this simulator takes the
745 branch. Branching to RPT_E is valid, the instruction
746 must be executed before the loop is taken. */
763 move_to_cr (BPSW_CR
, PSW
);
764 move_to_cr (PSW_CR
, PSW
& PSW_SM_BIT
);
765 PC
= SDBT_VECTOR_START
;
768 while ( !State
.exception
&& !stop_simulator
);
770 if (step
&& !State
.exception
)
771 State
.exception
= SIGTRAP
;
781 sim_resume (sd
, 0, 0);
786 sim_info (sd
, verbose
)
795 unsigned long left
= ins_type_counters
[ (int)INS_LEFT
] + ins_type_counters
[ (int)INS_LEFT_COND_EXE
];
796 unsigned long left_nops
= ins_type_counters
[ (int)INS_LEFT_NOPS
];
797 unsigned long left_parallel
= ins_type_counters
[ (int)INS_LEFT_PARALLEL
];
798 unsigned long left_cond
= ins_type_counters
[ (int)INS_LEFT_COND_TEST
];
799 unsigned long left_total
= left
+ left_parallel
+ left_cond
+ left_nops
;
801 unsigned long right
= ins_type_counters
[ (int)INS_RIGHT
] + ins_type_counters
[ (int)INS_RIGHT_COND_EXE
];
802 unsigned long right_nops
= ins_type_counters
[ (int)INS_RIGHT_NOPS
];
803 unsigned long right_parallel
= ins_type_counters
[ (int)INS_RIGHT_PARALLEL
];
804 unsigned long right_cond
= ins_type_counters
[ (int)INS_RIGHT_COND_TEST
];
805 unsigned long right_total
= right
+ right_parallel
+ right_cond
+ right_nops
;
807 unsigned long unknown
= ins_type_counters
[ (int)INS_UNKNOWN
];
808 unsigned long ins_long
= ins_type_counters
[ (int)INS_LONG
];
809 unsigned long parallel
= ins_type_counters
[ (int)INS_PARALLEL
];
810 unsigned long leftright
= ins_type_counters
[ (int)INS_LEFTRIGHT
];
811 unsigned long rightleft
= ins_type_counters
[ (int)INS_RIGHTLEFT
];
812 unsigned long cond_true
= ins_type_counters
[ (int)INS_COND_TRUE
];
813 unsigned long cond_false
= ins_type_counters
[ (int)INS_COND_FALSE
];
814 unsigned long cond_jump
= ins_type_counters
[ (int)INS_COND_JUMP
];
815 unsigned long cycles
= ins_type_counters
[ (int)INS_CYCLES
];
816 unsigned long total
= (unknown
+ left_total
+ right_total
+ ins_long
);
818 int size
= strlen (add_commas (buf1
, sizeof (buf1
), total
));
819 int parallel_size
= strlen (add_commas (buf1
, sizeof (buf1
),
820 (left_parallel
> right_parallel
) ? left_parallel
: right_parallel
));
821 int cond_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_cond
> right_cond
) ? left_cond
: right_cond
));
822 int nop_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_nops
> right_nops
) ? left_nops
: right_nops
));
823 int normal_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left
> right
) ? left
: right
));
825 (*d10v_callback
->printf_filtered
) (d10v_callback
,
826 "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
827 size
, add_commas (buf1
, sizeof (buf1
), left_total
),
828 normal_size
, add_commas (buf2
, sizeof (buf2
), left
),
829 parallel_size
, add_commas (buf3
, sizeof (buf3
), left_parallel
),
830 cond_size
, add_commas (buf4
, sizeof (buf4
), left_cond
),
831 nop_size
, add_commas (buf5
, sizeof (buf5
), left_nops
));
833 (*d10v_callback
->printf_filtered
) (d10v_callback
,
834 "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
835 size
, add_commas (buf1
, sizeof (buf1
), right_total
),
836 normal_size
, add_commas (buf2
, sizeof (buf2
), right
),
837 parallel_size
, add_commas (buf3
, sizeof (buf3
), right_parallel
),
838 cond_size
, add_commas (buf4
, sizeof (buf4
), right_cond
),
839 nop_size
, add_commas (buf5
, sizeof (buf5
), right_nops
));
842 (*d10v_callback
->printf_filtered
) (d10v_callback
,
843 "executed %*s long instruction(s)\n",
844 size
, add_commas (buf1
, sizeof (buf1
), ins_long
));
847 (*d10v_callback
->printf_filtered
) (d10v_callback
,
848 "executed %*s parallel instruction(s)\n",
849 size
, add_commas (buf1
, sizeof (buf1
), parallel
));
852 (*d10v_callback
->printf_filtered
) (d10v_callback
,
853 "executed %*s instruction(s) encoded L->R\n",
854 size
, add_commas (buf1
, sizeof (buf1
), leftright
));
857 (*d10v_callback
->printf_filtered
) (d10v_callback
,
858 "executed %*s instruction(s) encoded R->L\n",
859 size
, add_commas (buf1
, sizeof (buf1
), rightleft
));
862 (*d10v_callback
->printf_filtered
) (d10v_callback
,
863 "executed %*s unknown instruction(s)\n",
864 size
, add_commas (buf1
, sizeof (buf1
), unknown
));
867 (*d10v_callback
->printf_filtered
) (d10v_callback
,
868 "executed %*s instruction(s) due to EXExxx condition being true\n",
869 size
, add_commas (buf1
, sizeof (buf1
), cond_true
));
872 (*d10v_callback
->printf_filtered
) (d10v_callback
,
873 "skipped %*s instruction(s) due to EXExxx condition being false\n",
874 size
, add_commas (buf1
, sizeof (buf1
), cond_false
));
877 (*d10v_callback
->printf_filtered
) (d10v_callback
,
878 "skipped %*s instruction(s) due to conditional branch succeeding\n",
879 size
, add_commas (buf1
, sizeof (buf1
), cond_jump
));
881 (*d10v_callback
->printf_filtered
) (d10v_callback
,
882 "executed %*s cycle(s)\n",
883 size
, add_commas (buf1
, sizeof (buf1
), cycles
));
885 (*d10v_callback
->printf_filtered
) (d10v_callback
,
886 "executed %*s total instructions\n",
887 size
, add_commas (buf1
, sizeof (buf1
), total
));
891 sim_create_inferior (sd
, abfd
, argv
, env
)
897 bfd_vma start_address
;
899 /* reset all state information */
900 memset (&State
.regs
, 0, (int)&State
.imem
- (int)&State
.regs
[0]);
904 /* a hack to set r0/r1 with argc/argv */
905 /* some high memory that won't be overwritten by the stack soon */
906 addr
= State
.regs
[0] = 0x7C00;
911 SW (addr
+ 2*i
, addr
+ p
);
912 size
= strlen (argv
[i
]) + 1;
913 sim_write (sd
, addr
+ 0, argv
[i
], size
);
922 start_address
= bfd_get_start_address (abfd
);
924 start_address
= 0xffc0 << 2;
927 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_create_inferior: PC=0x%lx\n", (long) start_address
);
929 PC
= start_address
>> 2;
931 /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board */
932 /* resets imap0 and imap1 to 0x1000. */
951 sim_set_callbacks (p
)
958 sim_stop_reason (sd
, reason
, sigrc
)
960 enum sim_stop
*reason
;
963 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */
965 switch (State
.exception
)
967 case SIG_D10V_STOP
: /* stop instruction */
968 *reason
= sim_exited
;
972 case SIG_D10V_EXIT
: /* exit trap */
973 *reason
= sim_exited
;
974 *sigrc
= State
.regs
[0];
977 default: /* some signal */
978 *reason
= sim_stopped
;
979 if (stop_simulator
&& !State
.exception
)
982 *sigrc
= State
.exception
;
990 sim_fetch_register (sd
, rn
, memory
)
993 unsigned char *memory
;
996 WRITE_64 (memory
, State
.a
[rn
-35]);
998 WRITE_16 (memory
, IMAP0
);
1000 WRITE_16 (memory
, IMAP1
);
1002 WRITE_16 (memory
, DMAP
);
1004 WRITE_16 (memory
, move_from_cr (rn
- 16));
1006 WRITE_16 (memory
, State
.regs
[rn
]);
1010 sim_store_register (sd
, rn
, memory
)
1013 unsigned char *memory
;
1016 State
.a
[rn
-35] = READ_64 (memory
) & MASK40
;
1018 SET_DMAP( READ_16(memory
) );
1020 SET_IMAP1( READ_16(memory
) );
1022 SET_IMAP0( READ_16(memory
) );
1024 move_to_cr (rn
- 16, READ_16 (memory
));
1026 State
.regs
[rn
]= READ_16 (memory
);
1031 sim_do_command (sd
, cmd
)
1035 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_do_command: %s\n",cmd
);
1039 sim_load (sd
, prog
, abfd
, from_tty
)
1045 extern bfd
*sim_load_file (); /* ??? Don't know where this should live. */
1047 if (prog_bfd
!= NULL
&& prog_bfd_was_opened_p
)
1049 bfd_close (prog_bfd
);
1050 prog_bfd_was_opened_p
= 0;
1052 prog_bfd
= sim_load_file (sd
, myname
, d10v_callback
, prog
, abfd
,
1053 sim_kind
== SIM_OPEN_DEBUG
,
1054 1/*LMA*/, sim_write
);
1055 if (prog_bfd
== NULL
)
1057 prog_bfd_was_opened_p
= abfd
== NULL
;