]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/d10v/interp.c
fde96aa70e385669cd504005d7784878f9e55d84
1 /* This must come before any other includes. */
7 #include "sim/callback.h"
11 #include "sim-options.h"
12 #include "sim-signal.h"
14 #include "gdb/sim-d10v.h"
15 #include "gdb/signals.h"
21 #include "target-newlib-syscall.h"
23 enum _leftright
{ LEFT_FIRST
, RIGHT_FIRST
};
29 /* Set this to true to get the previous segment layout. */
31 int old_segment_mapping
;
33 unsigned long ins_type_counters
[ (int)INS_MAX
];
37 static long hash (long insn
, int format
);
38 static struct hash_entry
*lookup_hash (SIM_DESC
, SIM_CPU
*, uint32_t ins
, int size
);
39 static void get_operands (struct simops
*s
, uint32_t ins
);
40 static void do_long (SIM_DESC
, SIM_CPU
*, uint32_t ins
);
41 static void do_2_short (SIM_DESC
, SIM_CPU
*, uint16_t ins1
, uint16_t ins2
, enum _leftright leftright
);
42 static void do_parallel (SIM_DESC
, SIM_CPU
*, uint16_t ins1
, uint16_t ins2
);
43 static char *add_commas (char *buf
, int sizeof_buf
, unsigned long value
);
44 static INLINE
uint8_t *map_memory (SIM_DESC
, SIM_CPU
*, unsigned phys_addr
);
49 struct hash_entry
*next
;
56 struct hash_entry hash_table
[MAX_HASH
+1];
59 hash (long insn
, int format
)
61 if (format
& LONG_OPCODE
)
62 return ((insn
& 0x3F000000) >> 24);
64 return((insn
& 0x7E00) >> 9);
67 INLINE
static struct hash_entry
*
68 lookup_hash (SIM_DESC sd
, SIM_CPU
*cpu
, uint32_t ins
, int size
)
73 h
= &hash_table
[(ins
& 0x3F000000) >> 24];
75 h
= &hash_table
[(ins
& 0x7E00) >> 9];
77 while ((ins
& h
->mask
) != h
->opcode
|| h
->size
!= size
)
80 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGILL
);
87 get_operands (struct simops
*s
, uint32_t ins
)
89 int i
, shift
, bits
, flags
;
91 for (i
=0; i
< s
->numops
; i
++)
93 shift
= s
->operands
[3*i
];
94 bits
= s
->operands
[3*i
+1];
95 flags
= s
->operands
[3*i
+2];
96 mask
= 0x7FFFFFFF >> (31 - bits
);
97 OP
[i
] = (ins
>> shift
) & mask
;
99 /* FIXME: for tracing, update values that need to be updated each
100 instruction decode cycle */
101 State
.trace
.psw
= PSW
;
105 do_long (SIM_DESC sd
, SIM_CPU
*cpu
, uint32_t ins
)
107 struct hash_entry
*h
;
109 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
110 sim_io_printf (sd
, "do_long 0x%x\n", ins
);
112 h
= lookup_hash (sd
, cpu
, ins
, 1);
115 get_operands (h
->ops
, ins
);
116 State
.ins_type
= INS_LONG
;
117 ins_type_counters
[ (int)State
.ins_type
]++;
118 (h
->ops
->func
) (sd
, cpu
);
122 do_2_short (SIM_DESC sd
, SIM_CPU
*cpu
, uint16_t ins1
, uint16_t ins2
, enum _leftright leftright
)
124 struct hash_entry
*h
;
125 enum _ins_type first
, second
;
128 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
129 sim_io_printf (sd
, "do_2_short 0x%x (%s) -> 0x%x\n", ins1
,
130 leftright
? "left" : "right", ins2
);
133 if (leftright
== LEFT_FIRST
)
137 ins_type_counters
[ (int)INS_LEFTRIGHT
]++;
143 ins_type_counters
[ (int)INS_RIGHTLEFT
]++;
146 /* Issue the first instruction */
147 h
= lookup_hash (sd
, cpu
, ins1
, 0);
150 get_operands (h
->ops
, ins1
);
151 State
.ins_type
= first
;
152 ins_type_counters
[ (int)State
.ins_type
]++;
153 (h
->ops
->func
) (sd
, cpu
);
155 /* Issue the second instruction (if the PC hasn't changed) */
156 if (!State
.pc_changed
)
158 /* finish any existing instructions */
160 h
= lookup_hash (sd
, cpu
, ins2
, 0);
163 get_operands (h
->ops
, ins2
);
164 State
.ins_type
= second
;
165 ins_type_counters
[ (int)State
.ins_type
]++;
166 ins_type_counters
[ (int)INS_CYCLES
]++;
167 (h
->ops
->func
) (sd
, cpu
);
170 ins_type_counters
[ (int)INS_COND_JUMP
]++;
174 do_parallel (SIM_DESC sd
, SIM_CPU
*cpu
, uint16_t ins1
, uint16_t ins2
)
176 struct hash_entry
*h1
, *h2
;
178 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
179 sim_io_printf (sd
, "do_parallel 0x%x || 0x%x\n", ins1
, ins2
);
181 ins_type_counters
[ (int)INS_PARALLEL
]++;
182 h1
= lookup_hash (sd
, cpu
, ins1
, 0);
185 h2
= lookup_hash (sd
, cpu
, ins2
, 0);
189 if (h1
->ops
->exec_type
== PARONLY
)
191 get_operands (h1
->ops
, ins1
);
192 State
.ins_type
= INS_LEFT_COND_TEST
;
193 ins_type_counters
[ (int)State
.ins_type
]++;
194 (h1
->ops
->func
) (sd
, cpu
);
197 ins_type_counters
[ (int)INS_COND_TRUE
]++;
198 get_operands (h2
->ops
, ins2
);
199 State
.ins_type
= INS_RIGHT_COND_EXE
;
200 ins_type_counters
[ (int)State
.ins_type
]++;
201 (h2
->ops
->func
) (sd
, cpu
);
204 ins_type_counters
[ (int)INS_COND_FALSE
]++;
206 else if (h2
->ops
->exec_type
== PARONLY
)
208 get_operands (h2
->ops
, ins2
);
209 State
.ins_type
= INS_RIGHT_COND_TEST
;
210 ins_type_counters
[ (int)State
.ins_type
]++;
211 (h2
->ops
->func
) (sd
, cpu
);
214 ins_type_counters
[ (int)INS_COND_TRUE
]++;
215 get_operands (h1
->ops
, ins1
);
216 State
.ins_type
= INS_LEFT_COND_EXE
;
217 ins_type_counters
[ (int)State
.ins_type
]++;
218 (h1
->ops
->func
) (sd
, cpu
);
221 ins_type_counters
[ (int)INS_COND_FALSE
]++;
225 get_operands (h1
->ops
, ins1
);
226 State
.ins_type
= INS_LEFT_PARALLEL
;
227 ins_type_counters
[ (int)State
.ins_type
]++;
228 (h1
->ops
->func
) (sd
, cpu
);
229 get_operands (h2
->ops
, ins2
);
230 State
.ins_type
= INS_RIGHT_PARALLEL
;
231 ins_type_counters
[ (int)State
.ins_type
]++;
232 (h2
->ops
->func
) (sd
, cpu
);
237 add_commas (char *buf
, int sizeof_buf
, unsigned long value
)
240 char *endbuf
= buf
+ sizeof_buf
- 1;
250 *--endbuf
= (value
% 10) + '0';
251 } while ((value
/= 10) != 0);
260 for (i
= 0; i
< IMEM_SEGMENTS
; i
++)
262 if (State
.mem
.insn
[i
])
263 free (State
.mem
.insn
[i
]);
265 for (i
= 0; i
< DMEM_SEGMENTS
; i
++)
267 if (State
.mem
.data
[i
])
268 free (State
.mem
.data
[i
]);
270 for (i
= 0; i
< UMEM_SEGMENTS
; i
++)
272 if (State
.mem
.unif
[i
])
273 free (State
.mem
.unif
[i
]);
275 /* Always allocate dmem segment 0. This contains the IMAP and DMAP
277 State
.mem
.data
[0] = calloc (1, SEGMENT_SIZE
);
280 /* For tracing - leave info on last access around. */
281 static char *last_segname
= "invalid";
282 static char *last_from
= "invalid";
283 static char *last_to
= "invalid";
287 IMAP0_OFFSET
= 0xff00,
288 DMAP0_OFFSET
= 0xff08,
289 DMAP2_SHADDOW
= 0xff04,
290 DMAP2_OFFSET
= 0xff0c
294 set_dmap_register (SIM_DESC sd
, int reg_nr
, unsigned long value
)
296 uint8_t *raw
= map_memory (sd
, NULL
, SIM_D10V_MEMORY_DATA
297 + DMAP0_OFFSET
+ 2 * reg_nr
);
298 WRITE_16 (raw
, value
);
300 if ((d10v_debug
& DEBUG_MEMORY
))
302 sim_io_printf (sd
, "mem: dmap%d=0x%04lx\n", reg_nr
, value
);
308 dmap_register (SIM_DESC sd
, SIM_CPU
*cpu
, void *regcache
, int reg_nr
)
310 uint8_t *raw
= map_memory (sd
, cpu
, SIM_D10V_MEMORY_DATA
311 + DMAP0_OFFSET
+ 2 * reg_nr
);
312 return READ_16 (raw
);
316 set_imap_register (SIM_DESC sd
, int reg_nr
, unsigned long value
)
318 uint8_t *raw
= map_memory (sd
, NULL
, SIM_D10V_MEMORY_DATA
319 + IMAP0_OFFSET
+ 2 * reg_nr
);
320 WRITE_16 (raw
, value
);
322 if ((d10v_debug
& DEBUG_MEMORY
))
324 sim_io_printf (sd
, "mem: imap%d=0x%04lx\n", reg_nr
, value
);
330 imap_register (SIM_DESC sd
, SIM_CPU
*cpu
, void *regcache
, int reg_nr
)
332 uint8_t *raw
= map_memory (sd
, cpu
, SIM_D10V_MEMORY_DATA
333 + IMAP0_OFFSET
+ 2 * reg_nr
);
334 return READ_16 (raw
);
349 return HELD_SP (HELD_SPU_IDX
);
358 return HELD_SP (HELD_SPI_IDX
);
362 set_spi_register (unsigned long value
)
365 SET_GPR (SP_IDX
, value
);
366 SET_HELD_SP (HELD_SPI_IDX
, value
);
370 set_spu_register (unsigned long value
)
373 SET_GPR (SP_IDX
, value
);
374 SET_HELD_SP (HELD_SPU_IDX
, value
);
377 /* Given a virtual address in the DMAP address space, translate it
378 into a physical address. */
381 sim_d10v_translate_dmap_addr (SIM_DESC sd
,
383 unsigned long offset
,
387 unsigned long (*dmap_register
) (SIM_DESC
,
394 last_from
= "logical-data";
395 if (offset
>= DMAP_BLOCK_SIZE
* SIM_D10V_NR_DMAP_REGS
)
397 /* Logical address out side of data segments, not supported */
400 regno
= (offset
/ DMAP_BLOCK_SIZE
);
401 offset
= (offset
% DMAP_BLOCK_SIZE
);
402 if ((offset
% DMAP_BLOCK_SIZE
) + nr_bytes
> DMAP_BLOCK_SIZE
)
404 /* Don't cross a BLOCK boundary */
405 nr_bytes
= DMAP_BLOCK_SIZE
- (offset
% DMAP_BLOCK_SIZE
);
407 map
= dmap_register (sd
, cpu
, regcache
, regno
);
410 /* Always maps to data memory */
411 int iospi
= (offset
/ 0x1000) % 4;
412 int iosp
= (map
>> (4 * (3 - iospi
))) % 0x10;
413 last_to
= "io-space";
414 *phys
= (SIM_D10V_MEMORY_DATA
+ (iosp
* 0x10000) + 0xc000 + offset
);
418 int sp
= ((map
& 0x3000) >> 12);
419 int segno
= (map
& 0x3ff);
422 case 0: /* 00: Unified memory */
423 *phys
= SIM_D10V_MEMORY_UNIFIED
+ (segno
* DMAP_BLOCK_SIZE
) + offset
;
426 case 1: /* 01: Instruction Memory */
427 *phys
= SIM_D10V_MEMORY_INSN
+ (segno
* DMAP_BLOCK_SIZE
) + offset
;
428 last_to
= "chip-insn";
430 case 2: /* 10: Internal data memory */
431 *phys
= SIM_D10V_MEMORY_DATA
+ (segno
<< 16) + (regno
* DMAP_BLOCK_SIZE
) + offset
;
432 last_to
= "chip-data";
434 case 3: /* 11: Reserved */
441 /* Given a virtual address in the IMAP address space, translate it
442 into a physical address. */
445 sim_d10v_translate_imap_addr (SIM_DESC sd
,
447 unsigned long offset
,
451 unsigned long (*imap_register
) (SIM_DESC
,
460 last_from
= "logical-insn";
461 if (offset
>= (IMAP_BLOCK_SIZE
* SIM_D10V_NR_IMAP_REGS
))
463 /* Logical address outside of IMAP segments, not supported */
466 regno
= (offset
/ IMAP_BLOCK_SIZE
);
467 offset
= (offset
% IMAP_BLOCK_SIZE
);
468 if (offset
+ nr_bytes
> IMAP_BLOCK_SIZE
)
470 /* Don't cross a BLOCK boundary */
471 nr_bytes
= IMAP_BLOCK_SIZE
- offset
;
473 map
= imap_register (sd
, cpu
, regcache
, regno
);
474 sp
= (map
& 0x3000) >> 12;
475 segno
= (map
& 0x007f);
478 case 0: /* 00: unified memory */
479 *phys
= SIM_D10V_MEMORY_UNIFIED
+ (segno
<< 17) + offset
;
482 case 1: /* 01: instruction memory */
483 *phys
= SIM_D10V_MEMORY_INSN
+ (IMAP_BLOCK_SIZE
* regno
) + offset
;
484 last_to
= "chip-insn";
489 case 3: /* 11: for testing - instruction memory */
490 offset
= (offset
% 0x800);
491 *phys
= SIM_D10V_MEMORY_INSN
+ offset
;
492 if (offset
+ nr_bytes
> 0x800)
493 /* don't cross VM boundary */
494 nr_bytes
= 0x800 - offset
;
495 last_to
= "test-insn";
502 sim_d10v_translate_addr (SIM_DESC sd
,
504 unsigned long memaddr
,
506 unsigned long *targ_addr
,
508 unsigned long (*dmap_register
) (SIM_DESC
,
512 unsigned long (*imap_register
) (SIM_DESC
,
521 last_from
= "unknown";
524 seg
= (memaddr
>> 24);
525 off
= (memaddr
& 0xffffffL
);
527 /* However, if we've asked to use the previous generation of segment
528 mapping, rearrange the segments as follows. */
530 if (old_segment_mapping
)
534 case 0x00: /* DMAP translated memory */
537 case 0x01: /* IMAP translated memory */
540 case 0x10: /* On-chip data memory */
543 case 0x11: /* On-chip insn memory */
546 case 0x12: /* Unified memory */
554 case 0x00: /* Physical unified memory */
555 last_from
= "phys-unified";
557 phys
= SIM_D10V_MEMORY_UNIFIED
+ off
;
558 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
559 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
562 case 0x01: /* Physical instruction memory */
563 last_from
= "phys-insn";
564 last_to
= "chip-insn";
565 phys
= SIM_D10V_MEMORY_INSN
+ off
;
566 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
567 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
570 case 0x02: /* Physical data memory segment */
571 last_from
= "phys-data";
572 last_to
= "chip-data";
573 phys
= SIM_D10V_MEMORY_DATA
+ off
;
574 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
575 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
578 case 0x10: /* in logical data address segment */
579 nr_bytes
= sim_d10v_translate_dmap_addr (sd
, cpu
, off
, nr_bytes
, &phys
,
580 regcache
, dmap_register
);
583 case 0x11: /* in logical instruction address segment */
584 nr_bytes
= sim_d10v_translate_imap_addr (sd
, cpu
, off
, nr_bytes
, &phys
,
585 regcache
, imap_register
);
596 /* Return a pointer into the raw buffer designated by phys_addr. It
597 is assumed that the client has already ensured that the access
598 isn't going to cross a segment boundary. */
601 map_memory (SIM_DESC sd
, SIM_CPU
*cpu
, unsigned phys_addr
)
606 int segment
= ((phys_addr
>> 24) & 0xff);
611 case 0x00: /* Unified memory */
613 memory
= &State
.mem
.unif
[(phys_addr
/ SEGMENT_SIZE
) % UMEM_SEGMENTS
];
614 last_segname
= "umem";
618 case 0x01: /* On-chip insn memory */
620 memory
= &State
.mem
.insn
[(phys_addr
/ SEGMENT_SIZE
) % IMEM_SEGMENTS
];
621 last_segname
= "imem";
625 case 0x02: /* On-chip data memory */
627 if ((phys_addr
& 0xff00) == 0xff00)
629 phys_addr
= (phys_addr
& 0xffff);
630 if (phys_addr
== DMAP2_SHADDOW
)
632 phys_addr
= DMAP2_OFFSET
;
633 last_segname
= "dmap";
636 last_segname
= "reg";
639 last_segname
= "dmem";
640 memory
= &State
.mem
.data
[(phys_addr
/ SEGMENT_SIZE
) % DMEM_SEGMENTS
];
646 last_segname
= "scrap";
647 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGBUS
);
651 *memory
= xcalloc (1, SEGMENT_SIZE
);
653 offset
= (phys_addr
% SEGMENT_SIZE
);
654 raw
= *memory
+ offset
;
658 /* Transfer data to/from simulated memory. Since a bug in either the
659 simulated program or in gdb or the simulator itself may cause a
660 bogus address to be passed in, we need to do some sanity checking
661 on addresses to make sure they are within bounds. When an address
662 fails the bounds check, treat it as a zero length read/write rather
663 than aborting the entire run. */
666 xfer_mem (SIM_DESC sd
,
668 unsigned char *buffer
,
675 phys_size
= sim_d10v_translate_addr (sd
, NULL
, virt
, size
, &phys
, NULL
,
676 dmap_register
, imap_register
);
680 memory
= map_memory (sd
, NULL
, phys
);
683 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
687 "sim_%s %d bytes: 0x%08" PRIxTA
" (%s) -> 0x%08lx (%s) -> %p (%s)\n",
688 write_p
? "write" : "read",
689 phys_size
, virt
, last_from
,
691 memory
, last_segname
);
697 memcpy (memory
, buffer
, phys_size
);
701 memcpy (buffer
, memory
, phys_size
);
709 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
711 /* FIXME: this should be performing a virtual transfer */
712 /* FIXME: We cast the const away, but it's safe because xfer_mem only reads
713 when write_p==1. This is still ugly. */
714 return xfer_mem (sd
, addr
, (void *) buffer
, size
, 1);
718 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
720 /* FIXME: this should be performing a virtual transfer */
721 return xfer_mem (sd
, addr
, buffer
, size
, 0);
725 d10v_pc_get (sim_cpu
*cpu
)
731 d10v_pc_set (sim_cpu
*cpu
, sim_cia pc
)
733 SIM_DESC sd
= CPU_STATE (cpu
);
738 free_state (SIM_DESC sd
)
740 if (STATE_MODULES (sd
) != NULL
)
741 sim_module_uninstall (sd
);
742 sim_cpu_free_all (sd
);
746 static int d10v_reg_fetch (SIM_CPU
*, int, unsigned char *, int);
747 static int d10v_reg_store (SIM_CPU
*, int, unsigned char *, int);
750 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
,
751 struct bfd
*abfd
, char * const *argv
)
754 struct hash_entry
*h
;
755 static int init_p
= 0;
758 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
759 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
761 /* Set default options before parsing user options. */
762 current_alignment
= STRICT_ALIGNMENT
;
763 cb
->syscall_map
= cb_d10v_syscall_map
;
765 /* The cpu data is kept in a separately allocated chunk of memory. */
766 if (sim_cpu_alloc_all (sd
, 1) != SIM_RC_OK
)
772 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
778 /* The parser will print an error message for us, so we silently return. */
779 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
785 /* Check for/establish the a reference program image. */
786 if (sim_analyze_program (sd
, STATE_PROG_FILE (sd
), abfd
) != SIM_RC_OK
)
792 /* Configure/verify the target byte order and other runtime
793 configuration options. */
794 if (sim_config (sd
) != SIM_RC_OK
)
796 sim_module_uninstall (sd
);
800 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
802 /* Uninstall the modules to avoid memory leaks,
803 file descriptor leaks, etc. */
804 sim_module_uninstall (sd
);
808 /* CPU specific initialization. */
809 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
811 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
813 CPU_REG_FETCH (cpu
) = d10v_reg_fetch
;
814 CPU_REG_STORE (cpu
) = d10v_reg_store
;
815 CPU_PC_FETCH (cpu
) = d10v_pc_get
;
816 CPU_PC_STORE (cpu
) = d10v_pc_set
;
819 old_segment_mapping
= 0;
821 /* NOTE: This argument parsing is only effective when this function
822 is called by GDB. Standalone argument parsing is handled by
824 for (p
= argv
+ 1; *p
; ++p
)
826 if (strcmp (*p
, "-oldseg") == 0)
827 old_segment_mapping
= 1;
829 else if (strcmp (*p
, "-t") == 0)
831 else if (strncmp (*p
, "-t", 2) == 0)
832 d10v_debug
= atoi (*p
+ 2);
836 /* put all the opcodes in the hash table */
839 for (s
= Simops
; s
->func
; s
++)
841 h
= &hash_table
[hash(s
->opcode
,s
->format
)];
843 /* go to the last entry in the chain */
849 h
->next
= (struct hash_entry
*) calloc(1,sizeof(struct hash_entry
));
851 perror ("malloc failure");
857 h
->opcode
= s
->opcode
;
858 h
->size
= s
->is_long
;
862 /* reset the processor state */
863 if (!State
.mem
.data
[0])
870 dmem_addr (SIM_DESC sd
, SIM_CPU
*cpu
, uint16_t offset
)
876 /* Note: DMEM address range is 0..0x10000. Calling code can compute
877 things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
878 is uint16_t this is modulo'ed onto 0x0e5d. */
880 phys_size
= sim_d10v_translate_dmap_addr (sd
, cpu
, offset
, 1, &phys
, NULL
,
883 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGBUS
);
884 mem
= map_memory (sd
, cpu
, phys
);
886 if ((d10v_debug
& DEBUG_MEMORY
))
890 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> %p (%s)\n",
892 phys
, phys_size
, last_to
,
900 imem_addr (SIM_DESC sd
, SIM_CPU
*cpu
, uint32_t offset
)
904 int phys_size
= sim_d10v_translate_imap_addr (sd
, cpu
, offset
, 1, &phys
, NULL
,
907 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGBUS
);
908 mem
= map_memory (sd
, cpu
, phys
);
910 if ((d10v_debug
& DEBUG_MEMORY
))
914 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> %p (%s)\n",
916 phys
, phys_size
, last_to
,
924 step_once (SIM_DESC sd
, SIM_CPU
*cpu
)
929 /* TODO: Unindent this block. */
931 iaddr
= imem_addr (sd
, cpu
, (uint32_t)PC
<< 2);
933 inst
= get_longword( iaddr
);
935 State
.pc_changed
= 0;
936 ins_type_counters
[ (int)INS_CYCLES
]++;
938 switch (inst
& 0xC0000000)
941 /* long instruction */
942 do_long (sd
, cpu
, inst
& 0x3FFFFFFF);
946 do_2_short (sd
, cpu
, inst
& 0x7FFF, (inst
& 0x3FFF8000) >> 15, RIGHT_FIRST
);
950 do_2_short (sd
, cpu
, (inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF, LEFT_FIRST
);
953 do_parallel (sd
, cpu
, (inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF);
957 /* If the PC of the current instruction matches RPT_E then
958 schedule a branch to the loop start. If one of those
959 instructions happens to be a branch, than that instruction
961 if (!State
.pc_changed
)
963 if (PSW_RP
&& PC
== RPT_E
)
965 /* Note: The behavour of a branch instruction at RPT_E
966 is implementation dependant, this simulator takes the
967 branch. Branching to RPT_E is valid, the instruction
968 must be executed before the loop is taken. */
977 SET_RPT_C (RPT_C
- 1);
985 /* Check for a breakpoint trap on this instruction. This
986 overrides any pending branches or loops */
987 if (PSW_DB
&& PC
== IBA
)
991 SET_PSW (PSW
& PSW_SM_BIT
);
992 SET_PC (SDBT_VECTOR_START
);
995 /* Writeback all the DATA / PC changes */
1001 sim_engine_run (SIM_DESC sd
,
1002 int next_cpu_nr
, /* ignore */
1003 int nr_cpus
, /* ignore */
1008 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
1010 cpu
= STATE_CPU (sd
, 0);
1016 case GDB_SIGNAL_BUS
:
1019 SET_HW_PSW ((PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
1020 JMP (AE_VECTOR_START
);
1023 case GDB_SIGNAL_ILL
:
1026 SET_HW_PSW ((PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
1027 JMP (RIE_VECTOR_START
);
1031 /* just ignore it */
1037 step_once (sd
, cpu
);
1038 if (sim_events_tick (sd
))
1039 sim_events_process (sd
);
1044 sim_info (SIM_DESC sd
, int verbose
)
1051 unsigned long left
= ins_type_counters
[ (int)INS_LEFT
] + ins_type_counters
[ (int)INS_LEFT_COND_EXE
];
1052 unsigned long left_nops
= ins_type_counters
[ (int)INS_LEFT_NOPS
];
1053 unsigned long left_parallel
= ins_type_counters
[ (int)INS_LEFT_PARALLEL
];
1054 unsigned long left_cond
= ins_type_counters
[ (int)INS_LEFT_COND_TEST
];
1055 unsigned long left_total
= left
+ left_parallel
+ left_cond
+ left_nops
;
1057 unsigned long right
= ins_type_counters
[ (int)INS_RIGHT
] + ins_type_counters
[ (int)INS_RIGHT_COND_EXE
];
1058 unsigned long right_nops
= ins_type_counters
[ (int)INS_RIGHT_NOPS
];
1059 unsigned long right_parallel
= ins_type_counters
[ (int)INS_RIGHT_PARALLEL
];
1060 unsigned long right_cond
= ins_type_counters
[ (int)INS_RIGHT_COND_TEST
];
1061 unsigned long right_total
= right
+ right_parallel
+ right_cond
+ right_nops
;
1063 unsigned long unknown
= ins_type_counters
[ (int)INS_UNKNOWN
];
1064 unsigned long ins_long
= ins_type_counters
[ (int)INS_LONG
];
1065 unsigned long parallel
= ins_type_counters
[ (int)INS_PARALLEL
];
1066 unsigned long leftright
= ins_type_counters
[ (int)INS_LEFTRIGHT
];
1067 unsigned long rightleft
= ins_type_counters
[ (int)INS_RIGHTLEFT
];
1068 unsigned long cond_true
= ins_type_counters
[ (int)INS_COND_TRUE
];
1069 unsigned long cond_false
= ins_type_counters
[ (int)INS_COND_FALSE
];
1070 unsigned long cond_jump
= ins_type_counters
[ (int)INS_COND_JUMP
];
1071 unsigned long cycles
= ins_type_counters
[ (int)INS_CYCLES
];
1072 unsigned long total
= (unknown
+ left_total
+ right_total
+ ins_long
);
1074 int size
= strlen (add_commas (buf1
, sizeof (buf1
), total
));
1075 int parallel_size
= strlen (add_commas (buf1
, sizeof (buf1
),
1076 (left_parallel
> right_parallel
) ? left_parallel
: right_parallel
));
1077 int cond_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_cond
> right_cond
) ? left_cond
: right_cond
));
1078 int nop_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_nops
> right_nops
) ? left_nops
: right_nops
));
1079 int normal_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left
> right
) ? left
: right
));
1082 "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1083 size
, add_commas (buf1
, sizeof (buf1
), left_total
),
1084 normal_size
, add_commas (buf2
, sizeof (buf2
), left
),
1085 parallel_size
, add_commas (buf3
, sizeof (buf3
), left_parallel
),
1086 cond_size
, add_commas (buf4
, sizeof (buf4
), left_cond
),
1087 nop_size
, add_commas (buf5
, sizeof (buf5
), left_nops
));
1090 "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1091 size
, add_commas (buf1
, sizeof (buf1
), right_total
),
1092 normal_size
, add_commas (buf2
, sizeof (buf2
), right
),
1093 parallel_size
, add_commas (buf3
, sizeof (buf3
), right_parallel
),
1094 cond_size
, add_commas (buf4
, sizeof (buf4
), right_cond
),
1095 nop_size
, add_commas (buf5
, sizeof (buf5
), right_nops
));
1099 "executed %*s long instruction(s)\n",
1100 size
, add_commas (buf1
, sizeof (buf1
), ins_long
));
1104 "executed %*s parallel instruction(s)\n",
1105 size
, add_commas (buf1
, sizeof (buf1
), parallel
));
1109 "executed %*s instruction(s) encoded L->R\n",
1110 size
, add_commas (buf1
, sizeof (buf1
), leftright
));
1114 "executed %*s instruction(s) encoded R->L\n",
1115 size
, add_commas (buf1
, sizeof (buf1
), rightleft
));
1119 "executed %*s unknown instruction(s)\n",
1120 size
, add_commas (buf1
, sizeof (buf1
), unknown
));
1124 "executed %*s instruction(s) due to EXExxx condition being true\n",
1125 size
, add_commas (buf1
, sizeof (buf1
), cond_true
));
1129 "skipped %*s instruction(s) due to EXExxx condition being false\n",
1130 size
, add_commas (buf1
, sizeof (buf1
), cond_false
));
1134 "skipped %*s instruction(s) due to conditional branch succeeding\n",
1135 size
, add_commas (buf1
, sizeof (buf1
), cond_jump
));
1138 "executed %*s cycle(s)\n",
1139 size
, add_commas (buf1
, sizeof (buf1
), cycles
));
1142 "executed %*s total instructions\n",
1143 size
, add_commas (buf1
, sizeof (buf1
), total
));
1147 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
1148 char * const *argv
, char * const *env
)
1150 bfd_vma start_address
;
1152 /* Make sure we have the right structure for the following memset. */
1153 static_assert (offsetof (struct _state
, regs
) == 0,
1154 "State.regs is not at offset 0");
1156 /* Reset state from the regs field until the mem field. */
1157 memset (&State
, 0, (uintptr_t) &State
.mem
- (uintptr_t) &State
.regs
);
1159 /* There was a hack here to copy the values of argc and argv into r0
1160 and r1. The values were also saved into some high memory that
1161 won't be overwritten by the stack (0x7C00). The reason for doing
1162 this was to allow the 'run' program to accept arguments. Without
1163 the hack, this is not possible anymore. If the simulator is run
1164 from the debugger, arguments cannot be passed in, so this makes
1169 start_address
= bfd_get_start_address (abfd
);
1171 start_address
= 0xffc0 << 2;
1174 sim_io_printf (sd
, "sim_create_inferior: PC=0x%" PRIx64
"\n",
1175 (uint64_t) start_address
);
1178 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1179 SET_CREG (PC_CR
, start_address
>> 2);
1182 /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board
1183 initializes imap0 and imap1 to 0x1000 as part of its ROM
1185 if (old_segment_mapping
)
1187 /* External memory startup. This is the HARD reset state. */
1188 set_imap_register (sd
, 0, 0x0000);
1189 set_imap_register (sd
, 1, 0x007f);
1190 set_dmap_register (sd
, 0, 0x2000);
1191 set_dmap_register (sd
, 1, 0x2000);
1192 set_dmap_register (sd
, 2, 0x0000); /* Old DMAP */
1193 set_dmap_register (sd
, 3, 0x0000);
1197 /* Internal memory startup. This is the ROM intialized state. */
1198 set_imap_register (sd
, 0, 0x1000);
1199 set_imap_register (sd
, 1, 0x1000);
1200 set_dmap_register (sd
, 0, 0x2000);
1201 set_dmap_register (sd
, 1, 0x2000);
1202 set_dmap_register (sd
, 2, 0x2000); /* DMAP2 initial internal value is
1203 0x2000 on the new board. */
1204 set_dmap_register (sd
, 3, 0x0000);
1212 d10v_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1214 SIM_DESC sd
= CPU_STATE (cpu
);
1216 switch ((enum sim_d10v_regs
) rn
)
1218 case SIM_D10V_R0_REGNUM
:
1219 case SIM_D10V_R1_REGNUM
:
1220 case SIM_D10V_R2_REGNUM
:
1221 case SIM_D10V_R3_REGNUM
:
1222 case SIM_D10V_R4_REGNUM
:
1223 case SIM_D10V_R5_REGNUM
:
1224 case SIM_D10V_R6_REGNUM
:
1225 case SIM_D10V_R7_REGNUM
:
1226 case SIM_D10V_R8_REGNUM
:
1227 case SIM_D10V_R9_REGNUM
:
1228 case SIM_D10V_R10_REGNUM
:
1229 case SIM_D10V_R11_REGNUM
:
1230 case SIM_D10V_R12_REGNUM
:
1231 case SIM_D10V_R13_REGNUM
:
1232 case SIM_D10V_R14_REGNUM
:
1233 case SIM_D10V_R15_REGNUM
:
1234 WRITE_16 (memory
, GPR (rn
- SIM_D10V_R0_REGNUM
));
1237 case SIM_D10V_CR0_REGNUM
:
1238 case SIM_D10V_CR1_REGNUM
:
1239 case SIM_D10V_CR2_REGNUM
:
1240 case SIM_D10V_CR3_REGNUM
:
1241 case SIM_D10V_CR4_REGNUM
:
1242 case SIM_D10V_CR5_REGNUM
:
1243 case SIM_D10V_CR6_REGNUM
:
1244 case SIM_D10V_CR7_REGNUM
:
1245 case SIM_D10V_CR8_REGNUM
:
1246 case SIM_D10V_CR9_REGNUM
:
1247 case SIM_D10V_CR10_REGNUM
:
1248 case SIM_D10V_CR11_REGNUM
:
1249 case SIM_D10V_CR12_REGNUM
:
1250 case SIM_D10V_CR13_REGNUM
:
1251 case SIM_D10V_CR14_REGNUM
:
1252 case SIM_D10V_CR15_REGNUM
:
1253 WRITE_16 (memory
, CREG (rn
- SIM_D10V_CR0_REGNUM
));
1256 case SIM_D10V_A0_REGNUM
:
1257 case SIM_D10V_A1_REGNUM
:
1258 WRITE_64 (memory
, ACC (rn
- SIM_D10V_A0_REGNUM
));
1261 case SIM_D10V_SPI_REGNUM
:
1262 /* PSW_SM indicates that the current SP is the USER
1264 WRITE_16 (memory
, spi_register ());
1267 case SIM_D10V_SPU_REGNUM
:
1268 /* PSW_SM indicates that the current SP is the USER
1270 WRITE_16 (memory
, spu_register ());
1273 case SIM_D10V_IMAP0_REGNUM
:
1274 case SIM_D10V_IMAP1_REGNUM
:
1275 WRITE_16 (memory
, imap_register (sd
, cpu
, NULL
, rn
- SIM_D10V_IMAP0_REGNUM
));
1278 case SIM_D10V_DMAP0_REGNUM
:
1279 case SIM_D10V_DMAP1_REGNUM
:
1280 case SIM_D10V_DMAP2_REGNUM
:
1281 case SIM_D10V_DMAP3_REGNUM
:
1282 WRITE_16 (memory
, dmap_register (sd
, cpu
, NULL
, rn
- SIM_D10V_DMAP0_REGNUM
));
1285 case SIM_D10V_TS2_DMAP_REGNUM
:
1296 d10v_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1298 SIM_DESC sd
= CPU_STATE (cpu
);
1300 switch ((enum sim_d10v_regs
) rn
)
1302 case SIM_D10V_R0_REGNUM
:
1303 case SIM_D10V_R1_REGNUM
:
1304 case SIM_D10V_R2_REGNUM
:
1305 case SIM_D10V_R3_REGNUM
:
1306 case SIM_D10V_R4_REGNUM
:
1307 case SIM_D10V_R5_REGNUM
:
1308 case SIM_D10V_R6_REGNUM
:
1309 case SIM_D10V_R7_REGNUM
:
1310 case SIM_D10V_R8_REGNUM
:
1311 case SIM_D10V_R9_REGNUM
:
1312 case SIM_D10V_R10_REGNUM
:
1313 case SIM_D10V_R11_REGNUM
:
1314 case SIM_D10V_R12_REGNUM
:
1315 case SIM_D10V_R13_REGNUM
:
1316 case SIM_D10V_R14_REGNUM
:
1317 case SIM_D10V_R15_REGNUM
:
1318 SET_GPR (rn
- SIM_D10V_R0_REGNUM
, READ_16 (memory
));
1321 case SIM_D10V_CR0_REGNUM
:
1322 case SIM_D10V_CR1_REGNUM
:
1323 case SIM_D10V_CR2_REGNUM
:
1324 case SIM_D10V_CR3_REGNUM
:
1325 case SIM_D10V_CR4_REGNUM
:
1326 case SIM_D10V_CR5_REGNUM
:
1327 case SIM_D10V_CR6_REGNUM
:
1328 case SIM_D10V_CR7_REGNUM
:
1329 case SIM_D10V_CR8_REGNUM
:
1330 case SIM_D10V_CR9_REGNUM
:
1331 case SIM_D10V_CR10_REGNUM
:
1332 case SIM_D10V_CR11_REGNUM
:
1333 case SIM_D10V_CR12_REGNUM
:
1334 case SIM_D10V_CR13_REGNUM
:
1335 case SIM_D10V_CR14_REGNUM
:
1336 case SIM_D10V_CR15_REGNUM
:
1337 SET_CREG (rn
- SIM_D10V_CR0_REGNUM
, READ_16 (memory
));
1340 case SIM_D10V_A0_REGNUM
:
1341 case SIM_D10V_A1_REGNUM
:
1342 SET_ACC (rn
- SIM_D10V_A0_REGNUM
, READ_64 (memory
) & MASK40
);
1345 case SIM_D10V_SPI_REGNUM
:
1346 /* PSW_SM indicates that the current SP is the USER
1348 set_spi_register (READ_16 (memory
));
1351 case SIM_D10V_SPU_REGNUM
:
1352 set_spu_register (READ_16 (memory
));
1355 case SIM_D10V_IMAP0_REGNUM
:
1356 case SIM_D10V_IMAP1_REGNUM
:
1357 set_imap_register (sd
, rn
- SIM_D10V_IMAP0_REGNUM
, READ_16(memory
));
1360 case SIM_D10V_DMAP0_REGNUM
:
1361 case SIM_D10V_DMAP1_REGNUM
:
1362 case SIM_D10V_DMAP2_REGNUM
:
1363 case SIM_D10V_DMAP3_REGNUM
:
1364 set_dmap_register (sd
, rn
- SIM_D10V_DMAP0_REGNUM
, READ_16(memory
));
1367 case SIM_D10V_TS2_DMAP_REGNUM
: