]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/d10v/simops.c
9 #include "sys/syscall.h"
11 extern char *strrchr ();
43 static void trace_input_func
PARAMS ((char *name
,
48 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
50 static void trace_output_func
PARAMS ((enum op_types result
));
52 #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
54 #ifndef SIZE_INSTRUCTION
55 #define SIZE_INSTRUCTION 8
59 #define SIZE_OPERANDS 18
63 #define SIZE_VALUES 13
67 #define SIZE_LOCATION 20
74 #ifndef SIZE_LINE_NUMBER
75 #define SIZE_LINE_NUMBER 4
79 trace_input_func (name
, in1
, in2
, in3
)
93 const char *functionname
;
94 unsigned int linenumber
;
97 if ((d10v_debug
& DEBUG_TRACE
) == 0)
100 switch (State
.ins_type
)
103 case INS_UNKNOWN
: type
= " ?"; break;
104 case INS_LEFT
: type
= " L"; break;
105 case INS_RIGHT
: type
= " R"; break;
106 case INS_LEFT_PARALLEL
: type
= "*L"; break;
107 case INS_RIGHT_PARALLEL
: type
= "*R"; break;
108 case INS_LEFT_COND_TEST
: type
= "?L"; break;
109 case INS_RIGHT_COND_TEST
: type
= "?R"; break;
110 case INS_LEFT_COND_EXE
: type
= "&L"; break;
111 case INS_RIGHT_COND_EXE
: type
= "&R"; break;
112 case INS_LONG
: type
= " B"; break;
115 if ((d10v_debug
& DEBUG_LINE_NUMBER
) == 0)
116 (*d10v_callback
->printf_filtered
) (d10v_callback
,
118 SIZE_PC
, (unsigned)PC
,
120 SIZE_INSTRUCTION
, name
);
125 byte_pc
= decode_pc ();
126 if (text
&& byte_pc
>= text_start
&& byte_pc
< text_end
)
128 filename
= (const char *)0;
129 functionname
= (const char *)0;
131 if (bfd_find_nearest_line (exec_bfd
, text
, (struct symbol_cache_entry
**)0, byte_pc
- text_start
,
132 &filename
, &functionname
, &linenumber
))
137 sprintf (p
, "#%-*d ", SIZE_LINE_NUMBER
, linenumber
);
142 sprintf (p
, "%-*s ", SIZE_LINE_NUMBER
+1, "---");
143 p
+= SIZE_LINE_NUMBER
+2;
148 sprintf (p
, "%s ", functionname
);
153 char *q
= strrchr (filename
, '/');
154 sprintf (p
, "%s ", (q
) ? q
+1 : filename
);
163 (*d10v_callback
->printf_filtered
) (d10v_callback
,
164 "0x%.*x %s: %-*.*s %-*s ",
165 SIZE_PC
, (unsigned)PC
,
167 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
168 SIZE_INSTRUCTION
, name
);
176 for (i
= 0; i
< 3; i
++)
191 sprintf (p
, "%sr%d", comma
, OP
[i
]);
199 sprintf (p
, "%scr%d", comma
, OP
[i
]);
205 case OP_ACCUM_OUTPUT
:
206 case OP_ACCUM_REVERSE
:
207 sprintf (p
, "%sa%d", comma
, OP
[i
]);
213 sprintf (p
, "%s%d", comma
, OP
[i
]);
219 sprintf (p
, "%s%d", comma
, SEXT8(OP
[i
]));
225 sprintf (p
, "%s%d", comma
, SEXT4(OP
[i
]));
231 sprintf (p
, "%s%d", comma
, SEXT3(OP
[i
]));
237 sprintf (p
, "%s@r%d", comma
, OP
[i
]);
243 sprintf (p
, "%s@(%d,r%d)", comma
, (int16
)OP
[i
], OP
[i
+1]);
249 sprintf (p
, "%s@r%d+", comma
, OP
[i
]);
255 sprintf (p
, "%s@r%d-", comma
, OP
[i
]);
261 sprintf (p
, "%s@-r%d", comma
, OP
[i
]);
269 sprintf (p
, "%sf0", comma
);
272 sprintf (p
, "%sf1", comma
);
275 sprintf (p
, "%sc", comma
);
283 if ((d10v_debug
& DEBUG_VALUES
) == 0)
287 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%s", buf
);
292 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%-*s", SIZE_OPERANDS
, buf
);
295 for (i
= 0; i
< 3; i
++)
301 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "");
307 case OP_ACCUM_OUTPUT
:
309 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "---");
317 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
318 (uint16
)State
.regs
[OP
[i
]]);
322 tmp
= (long)((((uint32
) State
.regs
[OP
[i
]]) << 16) | ((uint32
) State
.regs
[OP
[i
]+1]));
323 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.8lx", SIZE_VALUES
-10, "", tmp
);
328 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
329 (uint16
)State
.cregs
[OP
[i
]]);
333 case OP_ACCUM_REVERSE
:
334 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.2x%.8lx", SIZE_VALUES
-12, "",
335 ((int)(State
.a
[OP
[i
]] >> 32) & 0xff),
336 ((unsigned long)State
.a
[OP
[i
]]) & 0xffffffff);
340 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
345 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
346 (uint16
)SEXT4(OP
[i
]));
350 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
351 (uint16
)SEXT8(OP
[i
]));
355 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
356 (uint16
)SEXT3(OP
[i
]));
361 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF0 = %d", SIZE_VALUES
-6, "",
365 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF1 = %d", SIZE_VALUES
-6, "",
369 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sC = %d", SIZE_VALUES
-5, "",
375 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
377 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
378 (uint16
)State
.regs
[OP
[++i
]]);
382 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
383 (uint16
)State
.regs
[2]);
387 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
388 (uint16
)State
.regs
[3]);
392 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
393 (uint16
)State
.regs
[4]);
397 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
398 (uint16
)State
.regs
[2]);
399 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
400 (uint16
)State
.regs
[3]);
409 trace_output_func (result
)
410 enum op_types result
;
412 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
424 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
425 (uint16
)State
.regs
[OP
[0]],
426 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
431 tmp
= (long)((((uint32
) State
.regs
[OP
[0]]) << 16) | ((uint32
) State
.regs
[OP
[0]+1]));
432 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-10, "", tmp
,
433 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
438 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
439 (uint16
)State
.cregs
[OP
[0]],
440 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
444 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
445 (uint16
)State
.cregs
[OP
[1]],
446 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
450 case OP_ACCUM_OUTPUT
:
451 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-12, "",
452 ((int)(State
.a
[OP
[0]] >> 32) & 0xff),
453 ((unsigned long)State
.a
[OP
[0]]) & 0xffffffff,
454 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
457 case OP_ACCUM_REVERSE
:
458 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-12, "",
459 ((int)(State
.a
[OP
[1]] >> 32) & 0xff),
460 ((unsigned long)State
.a
[OP
[1]]) & 0xffffffff,
461 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
466 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES
, "",
467 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
471 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
472 (uint16
)State
.regs
[2],
473 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
477 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-10, "",
478 (uint16
)State
.regs
[2], (uint16
)State
.regs
[3],
479 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
486 #define trace_input(NAME, IN1, IN2, IN3)
487 #define trace_output(RESULT)
494 trace_input ("abs", OP_REG
, OP_VOID
, OP_VOID
);
496 if ((int16
)(State
.regs
[OP
[0]]) < 0)
498 State
.regs
[OP
[0]] = -(int16
)(State
.regs
[OP
[0]]);
503 trace_output (OP_REG
);
512 trace_input ("abs", OP_ACCUM
, OP_VOID
, OP_VOID
);
514 State
.a
[OP
[0]] = SEXT40(State
.a
[OP
[0]]);
516 if (State
.a
[OP
[0]] < 0 )
518 tmp
= -State
.a
[OP
[0]];
522 State
.a
[OP
[0]] = MAX32
;
523 else if (tmp
< MIN32
)
524 State
.a
[OP
[0]] = MIN32
;
526 State
.a
[OP
[0]] = tmp
& MASK40
;
529 State
.a
[OP
[0]] = tmp
& MASK40
;
534 trace_output (OP_ACCUM
);
541 uint16 tmp
= State
.regs
[OP
[0]];
542 trace_input ("add", OP_REG
, OP_REG
, OP_VOID
);
543 State
.regs
[OP
[0]] += State
.regs
[OP
[1]];
544 if ( tmp
> State
.regs
[OP
[0]])
548 trace_output (OP_REG
);
556 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
558 trace_input ("add", OP_ACCUM
, OP_REG
, OP_VOID
);
562 State
.a
[OP
[0]] = MAX32
;
563 else if ( tmp
< MIN32
)
564 State
.a
[OP
[0]] = MIN32
;
566 State
.a
[OP
[0]] = tmp
& MASK40
;
569 State
.a
[OP
[0]] = tmp
& MASK40
;
570 trace_output (OP_ACCUM
);
578 tmp
= SEXT40(State
.a
[OP
[0]]) + SEXT40(State
.a
[OP
[1]]);
580 trace_input ("add", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
584 State
.a
[OP
[0]] = MAX32
;
585 else if ( tmp
< MIN32
)
586 State
.a
[OP
[0]] = MIN32
;
588 State
.a
[OP
[0]] = tmp
& MASK40
;
591 State
.a
[OP
[0]] = tmp
& MASK40
;
592 trace_output (OP_ACCUM
);
600 uint32 tmp1
= (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1];
601 uint32 tmp2
= (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
603 trace_input ("add2w", OP_DREG
, OP_DREG
, OP_VOID
);
605 if ( (tmp
< tmp1
) || (tmp
< tmp2
) )
609 State
.regs
[OP
[0]] = tmp
>> 16;
610 State
.regs
[OP
[0]+1] = tmp
& 0xFFFF;
611 trace_output (OP_DREG
);
618 uint16 tmp
= State
.regs
[OP
[0]];
619 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] + OP
[2];
621 trace_input ("add3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
622 if ( tmp
> State
.regs
[OP
[0]])
626 trace_output (OP_REG
);
634 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
636 trace_input ("addac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
637 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
638 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
639 trace_output (OP_DREG
);
647 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
649 trace_input ("addac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
650 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
651 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
652 trace_output (OP_DREG
);
662 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
663 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
666 State
.regs
[OP
[0]] = 0x7fff;
667 State
.regs
[OP
[0]+1] = 0xffff;
670 else if (tmp
< MIN32
)
672 State
.regs
[OP
[0]] = 0x8000;
673 State
.regs
[OP
[0]+1] = 0;
678 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
679 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
682 trace_output (OP_DREG
);
692 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
693 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
696 State
.regs
[OP
[0]] = 0x7fff;
697 State
.regs
[OP
[0]+1] = 0xffff;
700 else if (tmp
< MIN32
)
702 State
.regs
[OP
[0]] = 0x8000;
703 State
.regs
[OP
[0]+1] = 0;
708 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
709 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
712 trace_output (OP_DREG
);
719 uint tmp
= State
.regs
[OP
[0]];
722 trace_input ("addi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
723 State
.regs
[OP
[0]] += OP
[1];
724 if (tmp
> State
.regs
[OP
[0]])
728 trace_output (OP_REG
);
735 trace_input ("and", OP_REG
, OP_REG
, OP_VOID
);
736 State
.regs
[OP
[0]] &= State
.regs
[OP
[1]];
737 trace_output (OP_REG
);
744 trace_input ("and3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
745 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & OP
[2];
746 trace_output (OP_REG
);
753 trace_input ("bclri", OP_REG
, OP_CONSTANT16
, OP_VOID
);
754 State
.regs
[OP
[0]] &= ~(0x8000 >> OP
[1]);
755 trace_output (OP_REG
);
762 trace_input ("bl.s", OP_CONSTANT8
, OP_R2
, OP_R3
);
763 State
.regs
[13] = PC
+1;
765 trace_output (OP_VOID
);
772 trace_input ("bl.l", OP_CONSTANT16
, OP_R2
, OP_R3
);
773 State
.regs
[13] = PC
+1;
775 trace_output (OP_VOID
);
782 trace_input ("bnoti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
783 State
.regs
[OP
[0]] ^= 0x8000 >> OP
[1];
784 trace_output (OP_REG
);
791 trace_input ("bra.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
793 trace_output (OP_VOID
);
800 trace_input ("bra.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
802 trace_output (OP_VOID
);
809 trace_input ("brf0f.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
812 trace_output (OP_FLAG
);
819 trace_input ("brf0f.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
822 trace_output (OP_FLAG
);
829 trace_input ("brf0t.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
832 trace_output (OP_FLAG
);
839 trace_input ("brf0t.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
842 trace_output (OP_FLAG
);
849 trace_input ("bseti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
850 State
.regs
[OP
[0]] |= 0x8000 >> OP
[1];
851 trace_output (OP_REG
);
858 trace_input ("btsti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
860 State
.F0
= (State
.regs
[OP
[0]] & (0x8000 >> OP
[1])) ? 1 : 0;
861 trace_output (OP_FLAG
);
868 trace_input ("clrac", OP_ACCUM_OUTPUT
, OP_VOID
, OP_VOID
);
870 trace_output (OP_ACCUM
);
877 trace_input ("cmp", OP_REG
, OP_REG
, OP_VOID
);
879 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(State
.regs
[OP
[1]])) ? 1 : 0;
880 trace_output (OP_FLAG
);
887 trace_input ("cmp", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
889 State
.F0
= (SEXT40(State
.a
[OP
[0]]) < SEXT40(State
.a
[OP
[1]])) ? 1 : 0;
890 trace_output (OP_FLAG
);
897 trace_input ("cmpeq", OP_REG
, OP_REG
, OP_VOID
);
899 State
.F0
= (State
.regs
[OP
[0]] == State
.regs
[OP
[1]]) ? 1 : 0;
900 trace_output (OP_FLAG
);
907 trace_input ("cmpeq", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
909 State
.F0
= (State
.a
[OP
[0]] == State
.a
[OP
[1]]) ? 1 : 0;
910 trace_output (OP_FLAG
);
917 trace_input ("cmpeqi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
919 State
.F0
= (State
.regs
[OP
[0]] == (reg_t
)SEXT4(OP
[1])) ? 1 : 0;
920 trace_output (OP_FLAG
);
927 trace_input ("cmpeqi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
929 State
.F0
= (State
.regs
[OP
[0]] == (reg_t
)OP
[1]) ? 1 : 0;
930 trace_output (OP_FLAG
);
937 trace_input ("cmpi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
939 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)SEXT4(OP
[1])) ? 1 : 0;
940 trace_output (OP_FLAG
);
947 trace_input ("cmpi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
949 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(OP
[1])) ? 1 : 0;
950 trace_output (OP_FLAG
);
957 trace_input ("cmpu", OP_REG
, OP_REG
, OP_VOID
);
959 State
.F0
= (State
.regs
[OP
[0]] < State
.regs
[OP
[1]]) ? 1 : 0;
960 trace_output (OP_FLAG
);
967 trace_input ("cmpui", OP_REG
, OP_CONSTANT16
, OP_VOID
);
969 State
.F0
= (State
.regs
[OP
[0]] < (reg_t
)OP
[1]) ? 1 : 0;
970 trace_output (OP_FLAG
);
979 trace_input ("cpfg", OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
993 trace_output (OP_FLAG
);
1000 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1001 State
.exception
= SIGTRAP
;
1008 uint16 foo
, tmp
, tmpf
;
1010 trace_input ("divs", OP_DREG
, OP_REG
, OP_VOID
);
1011 foo
= (State
.regs
[OP
[0]] << 1) | (State
.regs
[OP
[0]+1] >> 15);
1012 tmp
= (int16
)foo
- (int16
)(State
.regs
[OP
[1]]);
1013 tmpf
= (foo
>= State
.regs
[OP
[1]]) ? 1 : 0;
1014 State
.regs
[OP
[0]] = (tmpf
== 1) ? tmp
: foo
;
1015 State
.regs
[OP
[0]+1] = (State
.regs
[OP
[0]+1] << 1) | tmpf
;
1016 trace_output (OP_DREG
);
1023 trace_input ("exef0f", OP_VOID
, OP_VOID
, OP_VOID
);
1024 State
.exe
= (State
.F0
== 0);
1025 trace_output (OP_FLAG
);
1032 trace_input ("exef0t", OP_VOID
, OP_VOID
, OP_VOID
);
1033 State
.exe
= (State
.F0
!= 0);
1034 trace_output (OP_FLAG
);
1041 trace_input ("exef1f", OP_VOID
, OP_VOID
, OP_VOID
);
1042 State
.exe
= (State
.F1
== 0);
1043 trace_output (OP_FLAG
);
1050 trace_input ("exef1t", OP_VOID
, OP_VOID
, OP_VOID
);
1051 State
.exe
= (State
.F1
!= 0);
1052 trace_output (OP_FLAG
);
1059 trace_input ("exefaf", OP_VOID
, OP_VOID
, OP_VOID
);
1060 State
.exe
= (State
.F0
== 0) & (State
.F1
== 0);
1061 trace_output (OP_FLAG
);
1068 trace_input ("exefat", OP_VOID
, OP_VOID
, OP_VOID
);
1069 State
.exe
= (State
.F0
== 0) & (State
.F1
!= 0);
1070 trace_output (OP_FLAG
);
1077 trace_input ("exetaf", OP_VOID
, OP_VOID
, OP_VOID
);
1078 State
.exe
= (State
.F0
!= 0) & (State
.F1
== 0);
1079 trace_output (OP_FLAG
);
1086 trace_input ("exetat", OP_VOID
, OP_VOID
, OP_VOID
);
1087 State
.exe
= (State
.F0
!= 0) & (State
.F1
!= 0);
1088 trace_output (OP_FLAG
);
1098 trace_input ("exp", OP_REG_OUTPUT
, OP_DREG
, OP_VOID
);
1099 if (((int16
)State
.regs
[OP
[1]]) >= 0)
1100 tmp
= (State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1];
1102 tmp
= ~((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
1109 State
.regs
[OP
[0]] = i
-1;
1110 trace_output (OP_REG
);
1115 State
.regs
[OP
[0]] = 16;
1116 trace_output (OP_REG
);
1126 trace_input ("exp", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1127 if (SEXT40(State
.a
[OP
[1]]) >= 0)
1128 tmp
= State
.a
[OP
[1]];
1130 tmp
= ~(State
.a
[OP
[1]]);
1132 foo
= 0x4000000000LL
;
1137 State
.regs
[OP
[0]] = i
-9;
1138 trace_output (OP_REG
);
1143 State
.regs
[OP
[0]] = 16;
1144 trace_output (OP_REG
);
1151 trace_input ("jl", OP_REG
, OP_R2
, OP_R3
);
1152 State
.regs
[13] = PC
+1;
1153 PC
= State
.regs
[OP
[0]];
1154 trace_output (OP_VOID
);
1161 trace_input ("jmp", OP_REG
,
1162 (OP
[0] == 13) ? OP_R2
: OP_VOID
,
1163 (OP
[0] == 13) ? OP_R3
: OP_VOID
);
1165 PC
= State
.regs
[OP
[0]];
1166 trace_output (OP_VOID
);
1173 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1174 State
.regs
[OP
[0]] = RW (OP
[1] + State
.regs
[OP
[2]]);
1175 trace_output (OP_REG
);
1182 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1183 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1184 INC_ADDR(State
.regs
[OP
[1]],-2);
1185 trace_output (OP_REG
);
1192 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1193 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1194 INC_ADDR(State
.regs
[OP
[1]],2);
1195 trace_output (OP_REG
);
1202 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1203 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1204 trace_output (OP_REG
);
1211 uint16 addr
= State
.regs
[OP
[2]];
1212 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1213 State
.regs
[OP
[0]] = RW (OP
[1] + addr
);
1214 State
.regs
[OP
[0]+1] = RW (OP
[1] + addr
+ 2);
1215 trace_output (OP_DREG
);
1222 uint16 addr
= State
.regs
[OP
[1]];
1223 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1224 State
.regs
[OP
[0]] = RW (addr
);
1225 State
.regs
[OP
[0]+1] = RW (addr
+2);
1226 INC_ADDR(State
.regs
[OP
[1]],-4);
1227 trace_output (OP_DREG
);
1234 uint16 addr
= State
.regs
[OP
[1]];
1235 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1236 State
.regs
[OP
[0]] = RW (addr
);
1237 State
.regs
[OP
[0]+1] = RW (addr
+2);
1238 INC_ADDR(State
.regs
[OP
[1]],4);
1239 trace_output (OP_DREG
);
1246 uint16 addr
= State
.regs
[OP
[1]];
1247 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1248 State
.regs
[OP
[0]] = RW (addr
);
1249 State
.regs
[OP
[0]+1] = RW (addr
+2);
1250 trace_output (OP_DREG
);
1257 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1258 State
.regs
[OP
[0]] = SEXT8 (RB (OP
[1] + State
.regs
[OP
[2]]));
1259 trace_output (OP_REG
);
1266 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1267 State
.regs
[OP
[0]] = SEXT8 (RB (State
.regs
[OP
[1]]));
1268 trace_output (OP_REG
);
1275 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT4
, OP_VOID
);
1276 State
.regs
[OP
[0]] = SEXT4(OP
[1]);
1277 trace_output (OP_REG
);
1284 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT16
, OP_VOID
);
1285 State
.regs
[OP
[0]] = OP
[1];
1286 trace_output (OP_REG
);
1293 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1294 State
.regs
[OP
[0]] = RB (OP
[1] + State
.regs
[OP
[2]]);
1295 trace_output (OP_REG
);
1302 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1303 State
.regs
[OP
[0]] = RB (State
.regs
[OP
[1]]);
1304 trace_output (OP_REG
);
1313 trace_input ("mac", OP_ACCUM
, OP_REG
, OP_REG
);
1314 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1317 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1319 if (State
.ST
&& tmp
> MAX32
)
1322 tmp
+= SEXT40(State
.a
[OP
[0]]);
1326 State
.a
[OP
[0]] = MAX32
;
1327 else if (tmp
< MIN32
)
1328 State
.a
[OP
[0]] = MIN32
;
1330 State
.a
[OP
[0]] = tmp
& MASK40
;
1333 State
.a
[OP
[0]] = tmp
& MASK40
;
1334 trace_output (OP_ACCUM
);
1343 trace_input ("macsu", OP_ACCUM
, OP_REG
, OP_REG
);
1344 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1346 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1348 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
1349 trace_output (OP_ACCUM
);
1358 trace_input ("macu", OP_ACCUM
, OP_REG
, OP_REG
);
1359 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1361 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1362 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
1363 trace_output (OP_ACCUM
);
1370 trace_input ("max", OP_REG
, OP_REG
, OP_VOID
);
1371 State
.F1
= State
.F0
;
1372 if ((int16
)State
.regs
[OP
[1]] > (int16
)State
.regs
[OP
[0]])
1374 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1379 trace_output (OP_REG
);
1388 trace_input ("max", OP_ACCUM
, OP_DREG
, OP_VOID
);
1389 State
.F1
= State
.F0
;
1390 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1391 if (tmp
> SEXT40(State
.a
[OP
[0]]))
1393 State
.a
[OP
[0]] = tmp
& MASK40
;
1398 trace_output (OP_ACCUM
);
1405 trace_input ("max", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1406 State
.F1
= State
.F0
;
1407 if (SEXT40(State
.a
[OP
[1]]) > SEXT40(State
.a
[OP
[0]]))
1409 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1414 trace_output (OP_ACCUM
);
1422 trace_input ("min", OP_REG
, OP_REG
, OP_VOID
);
1423 State
.F1
= State
.F0
;
1424 if ((int16
)State
.regs
[OP
[1]] < (int16
)State
.regs
[OP
[0]])
1426 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1431 trace_output (OP_REG
);
1440 trace_input ("min", OP_ACCUM
, OP_DREG
, OP_VOID
);
1441 State
.F1
= State
.F0
;
1442 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1443 if (tmp
< SEXT40(State
.a
[OP
[0]]))
1445 State
.a
[OP
[0]] = tmp
& MASK40
;
1450 trace_output (OP_ACCUM
);
1457 trace_input ("min", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1458 State
.F1
= State
.F0
;
1459 if (SEXT40(State
.a
[OP
[1]]) < SEXT40(State
.a
[OP
[0]]))
1461 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1466 trace_output (OP_ACCUM
);
1475 trace_input ("msb", OP_ACCUM
, OP_REG
, OP_REG
);
1476 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1479 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1481 if (State
.ST
&& tmp
> MAX32
)
1484 tmp
= SEXT40(State
.a
[OP
[0]]) - tmp
;
1488 State
.a
[OP
[0]] = MAX32
;
1489 else if (tmp
< MIN32
)
1490 State
.a
[OP
[0]] = MIN32
;
1492 State
.a
[OP
[0]] = tmp
& MASK40
;
1495 State
.a
[OP
[0]] = tmp
& MASK40
;
1496 trace_output (OP_ACCUM
);
1505 trace_input ("msbsu", OP_ACCUM
, OP_REG
, OP_REG
);
1506 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1508 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1510 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1511 trace_output (OP_ACCUM
);
1520 trace_input ("msbu", OP_ACCUM
, OP_REG
, OP_REG
);
1521 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1523 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1525 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1526 trace_output (OP_ACCUM
);
1533 trace_input ("mul", OP_REG
, OP_REG
, OP_VOID
);
1534 State
.regs
[OP
[0]] *= State
.regs
[OP
[1]];
1535 trace_output (OP_REG
);
1544 trace_input ("mulx", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1545 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1548 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1550 if (State
.ST
&& tmp
> MAX32
)
1551 State
.a
[OP
[0]] = MAX32
;
1553 State
.a
[OP
[0]] = tmp
& MASK40
;
1554 trace_output (OP_ACCUM
);
1563 trace_input ("mulxsu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1564 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * State
.regs
[OP
[2]]);
1569 State
.a
[OP
[0]] = tmp
& MASK40
;
1570 trace_output (OP_ACCUM
);
1579 trace_input ("mulxu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1580 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1585 State
.a
[OP
[0]] = tmp
& MASK40
;
1586 trace_output (OP_ACCUM
);
1593 trace_input ("mv", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1594 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1595 trace_output (OP_REG
);
1602 trace_input ("mv2w", OP_DREG_OUTPUT
, OP_DREG
, OP_VOID
);
1603 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1604 State
.regs
[OP
[0]+1] = State
.regs
[OP
[1]+1];
1605 trace_output (OP_DREG
);
1612 trace_input ("mv2wfac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1613 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1614 State
.regs
[OP
[0]+1] = State
.a
[OP
[1]] & 0xffff;
1615 trace_output (OP_DREG
);
1622 trace_input ("mv2wtac", OP_ACCUM_OUTPUT
, OP_DREG
, OP_VOID
);
1623 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1]) & MASK40
;
1624 trace_output (OP_ACCUM
);
1631 trace_input ("mvac", OP_ACCUM_OUTPUT
, OP_ACCUM
, OP_VOID
);
1632 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1633 trace_output (OP_ACCUM
);
1640 trace_input ("mvb", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1641 State
.regs
[OP
[0]] = SEXT8 (State
.regs
[OP
[1]] & 0xff);
1642 trace_output (OP_REG
);
1649 trace_input ("mf0f", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1651 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1652 trace_output (OP_REG
);
1659 trace_input ("mf0t", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1661 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1662 trace_output (OP_REG
);
1669 trace_input ("mvfacg", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1670 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 32) & 0xff;
1671 trace_output (OP_ACCUM
);
1678 trace_input ("mvfachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1679 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1680 trace_output (OP_REG
);
1687 trace_input ("mvfaclo", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1688 State
.regs
[OP
[0]] = State
.a
[OP
[1]] & 0xffff;
1689 trace_output (OP_REG
);
1696 trace_input ("mvfc", OP_REG_OUTPUT
, OP_CR
, OP_VOID
);
1699 /* PSW is treated specially */
1701 if (State
.SM
) PSW
|= 0x8000;
1702 if (State
.EA
) PSW
|= 0x2000;
1703 if (State
.DB
) PSW
|= 0x1000;
1704 if (State
.IE
) PSW
|= 0x400;
1705 if (State
.RP
) PSW
|= 0x200;
1706 if (State
.MD
) PSW
|= 0x100;
1707 if (State
.FX
) PSW
|= 0x80;
1708 if (State
.ST
) PSW
|= 0x40;
1709 if (State
.F0
) PSW
|= 8;
1710 if (State
.F1
) PSW
|= 4;
1711 if (State
.C
) PSW
|= 1;
1713 State
.regs
[OP
[0]] = State
.cregs
[OP
[1]];
1714 trace_output (OP_REG
);
1721 trace_input ("mvtacg", OP_REG
, OP_ACCUM
, OP_VOID
);
1722 State
.a
[OP
[1]] &= MASK32
;
1723 State
.a
[OP
[1]] |= (int64
)(State
.regs
[OP
[0]] & 0xff) << 32;
1724 trace_output (OP_ACCUM_REVERSE
);
1733 trace_input ("mvtachi", OP_REG
, OP_ACCUM
, OP_VOID
);
1734 tmp
= State
.a
[OP
[1]] & 0xffff;
1735 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | tmp
) & MASK40
;
1736 trace_output (OP_ACCUM_REVERSE
);
1743 trace_input ("mvtaclo", OP_REG
, OP_ACCUM
, OP_VOID
);
1744 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]])) & MASK40
;
1745 trace_output (OP_ACCUM_REVERSE
);
1752 trace_input ("mvtc", OP_REG
, OP_CR_OUTPUT
, OP_VOID
);
1753 State
.cregs
[OP
[1]] = State
.regs
[OP
[0]];
1756 /* PSW is treated specially */
1757 State
.SM
= (PSW
& 0x8000) ? 1 : 0;
1758 State
.EA
= (PSW
& 0x2000) ? 1 : 0;
1759 State
.DB
= (PSW
& 0x1000) ? 1 : 0;
1760 State
.IE
= (PSW
& 0x400) ? 1 : 0;
1761 State
.RP
= (PSW
& 0x200) ? 1 : 0;
1762 State
.MD
= (PSW
& 0x100) ? 1 : 0;
1763 State
.FX
= (PSW
& 0x80) ? 1 : 0;
1764 State
.ST
= (PSW
& 0x40) ? 1 : 0;
1765 State
.F0
= (PSW
& 8) ? 1 : 0;
1766 State
.F1
= (PSW
& 4) ? 1 : 0;
1768 if (State
.ST
&& !State
.FX
)
1770 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1771 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1773 State
.exception
= SIGILL
;
1776 trace_output (OP_CR_REVERSE
);
1783 trace_input ("mvub", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1784 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & 0xff;
1785 trace_output (OP_REG
);
1792 trace_input ("neg", OP_REG
, OP_VOID
, OP_VOID
);
1793 State
.regs
[OP
[0]] = 0 - State
.regs
[OP
[0]];
1794 trace_output (OP_REG
);
1803 trace_input ("neg", OP_ACCUM
, OP_VOID
, OP_VOID
);
1804 tmp
= -SEXT40(State
.a
[OP
[0]]);
1808 State
.a
[OP
[0]] = MAX32
;
1809 else if (tmp
< MIN32
)
1810 State
.a
[OP
[0]] = MIN32
;
1812 State
.a
[OP
[0]] = tmp
& MASK40
;
1815 State
.a
[OP
[0]] = tmp
& MASK40
;
1816 trace_output (OP_ACCUM
);
1824 trace_input ("nop", OP_VOID
, OP_VOID
, OP_VOID
);
1826 ins_type_counters
[ (int)State
.ins_type
]--; /* don't count nops as normal instructions */
1827 switch (State
.ins_type
)
1830 ins_type_counters
[ (int)INS_UNKNOWN
]++;
1833 case INS_LEFT_PARALLEL
:
1834 /* Don't count a parallel op that includes a NOP as a true parallel op */
1835 ins_type_counters
[ (int)INS_RIGHT_PARALLEL
]--;
1836 ins_type_counters
[ (int)INS_RIGHT
]++;
1837 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
1841 case INS_LEFT_COND_EXE
:
1842 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
1845 case INS_RIGHT_PARALLEL
:
1846 /* Don't count a parallel op that includes a NOP as a true parallel op */
1847 ins_type_counters
[ (int)INS_LEFT_PARALLEL
]--;
1848 ins_type_counters
[ (int)INS_LEFT
]++;
1849 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
1853 case INS_RIGHT_COND_EXE
:
1854 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
1858 trace_output (OP_VOID
);
1865 trace_input ("not", OP_REG
, OP_VOID
, OP_VOID
);
1866 State
.regs
[OP
[0]] = ~(State
.regs
[OP
[0]]);
1867 trace_output (OP_REG
);
1874 trace_input ("or", OP_REG
, OP_REG
, OP_VOID
);
1875 State
.regs
[OP
[0]] |= State
.regs
[OP
[1]];
1876 trace_output (OP_REG
);
1883 trace_input ("or3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
1884 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] | OP
[2];
1885 trace_output (OP_REG
);
1893 int shift
= SEXT3 (OP
[2]);
1895 trace_input ("rac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1898 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1899 "ERROR at PC 0x%x: instruction only valid for A0\n",
1901 State
.exception
= SIGILL
;
1904 State
.F1
= State
.F0
;
1906 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) << shift
;
1908 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) >> -shift
;
1909 tmp
= ( SEXT60(tmp
) + 0x8000 ) >> 16;
1912 State
.regs
[OP
[0]] = 0x7fff;
1913 State
.regs
[OP
[0]+1] = 0xffff;
1916 else if (tmp
< MIN32
)
1918 State
.regs
[OP
[0]] = 0x8000;
1919 State
.regs
[OP
[0]+1] = 0;
1924 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1925 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
1928 trace_output (OP_DREG
);
1936 int shift
= SEXT3 (OP
[2]);
1938 trace_input ("rachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1939 State
.F1
= State
.F0
;
1941 tmp
= SEXT44 (State
.a
[1]) << shift
;
1943 tmp
= SEXT44 (State
.a
[1]) >> -shift
;
1948 State
.regs
[OP
[0]] = 0x7fff;
1951 else if (tmp
< 0xfff80000000LL
)
1953 State
.regs
[OP
[0]] = 0x8000;
1958 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1961 trace_output (OP_REG
);
1968 trace_input ("rep", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1971 RPT_C
= State
.regs
[OP
[0]];
1975 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep with count=0 is illegal.\n");
1976 State
.exception
= SIGILL
;
1980 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep must include at least 4 instructions.\n");
1981 State
.exception
= SIGILL
;
1983 trace_output (OP_VOID
);
1990 trace_input ("repi", OP_CONSTANT16
, OP_CONSTANT16
, OP_VOID
);
1997 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi with count=0 is illegal.\n");
1998 State
.exception
= SIGILL
;
2002 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi must include at least 4 instructions.\n");
2003 State
.exception
= SIGILL
;
2005 trace_output (OP_VOID
);
2012 d10v_callback
->printf_filtered(d10v_callback
, "ERROR: rtd - NOT IMPLEMENTED\n");
2013 State
.exception
= SIGILL
;
2020 trace_input ("rte", OP_VOID
, OP_VOID
, OP_VOID
);
2023 trace_output (OP_VOID
);
2032 trace_input ("sadd", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2033 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT40(State
.a
[OP
[1]]) >> 16);
2037 State
.a
[OP
[0]] = MAX32
;
2038 else if (tmp
< MIN32
)
2039 State
.a
[OP
[0]] = MIN32
;
2041 State
.a
[OP
[0]] = tmp
& MASK40
;
2044 State
.a
[OP
[0]] = tmp
& MASK40
;
2045 trace_output (OP_ACCUM
);
2052 trace_input ("setf0f", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2053 State
.regs
[OP
[0]] = (State
.F0
== 0) ? 1 : 0;
2054 trace_output (OP_REG
);
2061 trace_input ("setf0t", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2062 State
.regs
[OP
[0]] = (State
.F0
== 1) ? 1 : 0;
2063 trace_output (OP_REG
);
2070 trace_input ("sleep", OP_VOID
, OP_VOID
, OP_VOID
);
2072 trace_output (OP_VOID
);
2079 trace_input ("sll", OP_REG
, OP_REG
, OP_VOID
);
2080 State
.regs
[OP
[0]] <<= (State
.regs
[OP
[1]] & 0xf);
2081 trace_output (OP_REG
);
2089 trace_input ("sll", OP_ACCUM
, OP_REG
, OP_VOID
);
2090 if ((State
.regs
[OP
[1]] & 31) <= 16)
2091 tmp
= SEXT40 (State
.a
[OP
[0]]) << (State
.regs
[OP
[1]] & 31);
2094 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2095 State
.exception
= SIGILL
;
2102 State
.a
[OP
[0]] = MAX32
;
2103 else if (tmp
< 0xffffff80000000LL
)
2104 State
.a
[OP
[0]] = MIN32
;
2106 State
.a
[OP
[0]] = tmp
& MASK40
;
2109 State
.a
[OP
[0]] = tmp
& MASK40
;
2110 trace_output (OP_ACCUM
);
2117 trace_input ("slli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2118 State
.regs
[OP
[0]] <<= OP
[1];
2119 trace_output (OP_REG
);
2131 trace_input ("slli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2132 tmp
= SEXT40(State
.a
[OP
[0]]) << OP
[1];
2137 State
.a
[OP
[0]] = MAX32
;
2138 else if (tmp
< 0xffffff80000000LL
)
2139 State
.a
[OP
[0]] = MIN32
;
2141 State
.a
[OP
[0]] = tmp
& MASK40
;
2144 State
.a
[OP
[0]] = tmp
& MASK40
;
2145 trace_output (OP_ACCUM
);
2152 trace_input ("slx", OP_REG
, OP_FLAG
, OP_VOID
);
2153 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] << 1) | State
.F0
;
2154 trace_output (OP_REG
);
2161 trace_input ("sra", OP_REG
, OP_REG
, OP_VOID
);
2162 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> (State
.regs
[OP
[1]] & 0xf);
2163 trace_output (OP_REG
);
2170 trace_input ("sra", OP_ACCUM
, OP_REG
, OP_VOID
);
2171 if ((State
.regs
[OP
[1]] & 31) <= 16)
2172 State
.a
[OP
[0]] >>= (State
.regs
[OP
[1]] & 31);
2175 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2176 State
.exception
= SIGILL
;
2180 trace_output (OP_ACCUM
);
2187 trace_input ("srai", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2188 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> OP
[1];
2189 trace_output (OP_REG
);
2199 trace_input ("srai", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2200 State
.a
[OP
[0]] >>= OP
[1];
2201 trace_output (OP_ACCUM
);
2208 trace_input ("srl", OP_REG
, OP_REG
, OP_VOID
);
2209 State
.regs
[OP
[0]] >>= (State
.regs
[OP
[1]] & 0xf);
2210 trace_output (OP_REG
);
2217 trace_input ("srl", OP_ACCUM
, OP_REG
, OP_VOID
);
2218 if ((State
.regs
[OP
[1]] & 31) <= 16)
2219 State
.a
[OP
[0]] >>= (State
.regs
[OP
[1]] & 31);
2222 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2223 State
.exception
= SIGILL
;
2227 trace_output (OP_ACCUM
);
2234 trace_input ("srli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2235 State
.regs
[OP
[0]] >>= OP
[1];
2236 trace_output (OP_REG
);
2246 trace_input ("srli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2247 State
.a
[OP
[0]] >>= OP
[1];
2248 trace_output (OP_ACCUM
);
2257 trace_input ("srx", OP_REG
, OP_FLAG
, OP_VOID
);
2258 tmp
= State
.F0
<< 15;
2259 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] >> 1) | tmp
;
2260 trace_output (OP_REG
);
2267 trace_input ("st", OP_REG
, OP_MEMREF2
, OP_VOID
);
2268 SW (OP
[1] + State
.regs
[OP
[2]], State
.regs
[OP
[0]]);
2269 trace_output (OP_VOID
);
2276 trace_input ("st", OP_REG
, OP_MEMREF
, OP_VOID
);
2277 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2278 trace_output (OP_VOID
);
2285 trace_input ("st", OP_REG
, OP_PREDEC
, OP_VOID
);
2288 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2289 State
.exception
= SIGILL
;
2292 State
.regs
[OP
[1]] -= 2;
2293 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2294 trace_output (OP_VOID
);
2301 trace_input ("st", OP_REG
, OP_POSTINC
, OP_VOID
);
2302 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2303 INC_ADDR (State
.regs
[OP
[1]],2);
2304 trace_output (OP_VOID
);
2311 trace_input ("st", OP_REG
, OP_POSTDEC
, OP_VOID
);
2312 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2313 INC_ADDR (State
.regs
[OP
[1]],-2);
2314 trace_output (OP_VOID
);
2321 trace_input ("st2w", OP_DREG
, OP_MEMREF2
, OP_VOID
);
2322 SW (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2323 SW (State
.regs
[OP
[2]]+OP
[1]+2, State
.regs
[OP
[0]+1]);
2324 trace_output (OP_VOID
);
2331 trace_input ("st2w", OP_DREG
, OP_MEMREF
, OP_VOID
);
2332 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2333 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2334 trace_output (OP_VOID
);
2341 trace_input ("st2w", OP_DREG
, OP_PREDEC
, OP_VOID
);
2344 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2345 State
.exception
= SIGILL
;
2348 State
.regs
[OP
[1]] -= 4;
2349 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2350 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2351 trace_output (OP_VOID
);
2358 trace_input ("st2w", OP_DREG
, OP_POSTDEC
, OP_VOID
);
2359 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2360 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2361 INC_ADDR (State
.regs
[OP
[1]],4);
2362 trace_output (OP_VOID
);
2369 trace_input ("st2w", OP_DREG
, OP_POSTINC
, OP_VOID
);
2370 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2371 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2372 INC_ADDR (State
.regs
[OP
[1]],-4);
2373 trace_output (OP_VOID
);
2380 trace_input ("stb", OP_REG
, OP_MEMREF2
, OP_VOID
);
2381 SB (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2382 trace_output (OP_VOID
);
2389 trace_input ("stb", OP_REG
, OP_MEMREF
, OP_VOID
);
2390 SB (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2391 trace_output (OP_VOID
);
2398 trace_input ("stop", OP_VOID
, OP_VOID
, OP_VOID
);
2399 State
.exception
= SIG_D10V_STOP
;
2400 trace_output (OP_VOID
);
2409 trace_input ("sub", OP_REG
, OP_REG
, OP_VOID
);
2410 tmp
= (int16
)State
.regs
[OP
[0]]- (int16
)State
.regs
[OP
[1]];
2411 State
.C
= (tmp
& 0xffff0000) ? 1 : 0;
2412 State
.regs
[OP
[0]] = tmp
& 0xffff;
2413 trace_output (OP_REG
);
2422 trace_input ("sub", OP_ACCUM
, OP_DREG
, OP_VOID
);
2423 tmp
= SEXT40(State
.a
[OP
[0]]) - (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
2427 State
.a
[OP
[0]] = MAX32
;
2428 else if ( tmp
< MIN32
)
2429 State
.a
[OP
[0]] = MIN32
;
2431 State
.a
[OP
[0]] = tmp
& MASK40
;
2434 State
.a
[OP
[0]] = tmp
& MASK40
;
2436 trace_output (OP_ACCUM
);
2446 trace_input ("sub", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2447 tmp
= SEXT40(State
.a
[OP
[0]]) - SEXT40(State
.a
[OP
[1]]);
2451 State
.a
[OP
[0]] = MAX32
;
2452 else if ( tmp
< MIN32
)
2453 State
.a
[OP
[0]] = MIN32
;
2455 State
.a
[OP
[0]] = tmp
& MASK40
;
2458 State
.a
[OP
[0]] = tmp
& MASK40
;
2460 trace_output (OP_ACCUM
);
2470 trace_input ("sub2w", OP_DREG
, OP_DREG
, OP_VOID
);
2471 a
= (int32
)((State
.regs
[OP
[0]] << 16) | State
.regs
[OP
[0]+1]);
2472 b
= (int32
)((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
2474 State
.C
= (tmp
& 0xffffffff00000000LL
) ? 1 : 0;
2475 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2476 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2477 trace_output (OP_DREG
);
2486 trace_input ("subac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2487 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40 (State
.a
[OP
[2]]);
2488 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2489 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2490 trace_output (OP_DREG
);
2499 trace_input ("subac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2500 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2501 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2502 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2503 trace_output (OP_DREG
);
2512 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2513 State
.F1
= State
.F0
;
2514 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40(State
.a
[OP
[2]]);
2517 State
.regs
[OP
[0]] = 0x7fff;
2518 State
.regs
[OP
[0]+1] = 0xffff;
2521 else if (tmp
< MIN32
)
2523 State
.regs
[OP
[0]] = 0x8000;
2524 State
.regs
[OP
[0]+1] = 0;
2529 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2530 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2533 trace_output (OP_DREG
);
2542 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2543 State
.F1
= State
.F0
;
2544 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2547 State
.regs
[OP
[0]] = 0x7fff;
2548 State
.regs
[OP
[0]+1] = 0xffff;
2551 else if (tmp
< MIN32
)
2553 State
.regs
[OP
[0]] = 0x8000;
2554 State
.regs
[OP
[0]+1] = 0;
2559 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2560 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2563 trace_output (OP_DREG
);
2574 trace_input ("subi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2575 tmp
= (int16
)State
.regs
[OP
[0]] - OP
[1];
2576 State
.C
= (tmp
& 0xffff0000) ? 1 : 0;
2577 State
.regs
[OP
[0]] = tmp
& 0xffff;
2578 trace_output (OP_REG
);
2585 trace_input ("trap", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
2586 trace_output (OP_VOID
);
2592 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Unknown trap code %d\n", OP
[0]);
2593 State
.exception
= SIGILL
;
2595 /* Use any other traps for batch debugging. */
2598 static int first_time
= 1;
2603 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap # PC ");
2604 for (i
= 0; i
< 16; i
++)
2605 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %sr%d", (i
> 9) ? "" : " ", i
);
2606 (*d10v_callback
->printf_filtered
) (d10v_callback
, " a0 a1 f0 f1 c\n");
2609 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap %2d 0x%.4x:", (int)OP
[0], (int)PC
);
2611 for (i
= 0; i
< 16; i
++)
2612 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.4x", (int) State
.regs
[i
]);
2614 for (i
= 0; i
< 2; i
++)
2615 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.2x%.8lx",
2616 ((int)(State
.a
[i
] >> 32) & 0xff),
2617 ((unsigned long)State
.a
[i
]) & 0xffffffff);
2619 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %d %d %d\n",
2620 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
2625 /* Trap 0 is used for simulating low-level I/O */
2629 /* Registers passed to trap 0 */
2631 #define FUNC State.regs[6] /* function number */
2632 #define PARM1 State.regs[2] /* optional parm 1 */
2633 #define PARM2 State.regs[3] /* optional parm 2 */
2634 #define PARM3 State.regs[4] /* optional parm 3 */
2635 #define PARM4 State.regs[5] /* optional parm 3 */
2637 /* Registers set by trap 0 */
2639 #define RETVAL State.regs[2] /* return value */
2640 #define RETVAL_HIGH State.regs[2] /* return value */
2641 #define RETVAL_LOW State.regs[3] /* return value */
2642 #define RETERR State.regs[4] /* return error code */
2644 /* Turn a pointer in a register into a pointer into real memory. */
2646 #define MEMPTR(x) ((char *)(dmem_addr(x)))
2650 #if !defined(__GO32__) && !defined(_WIN32)
2653 trace_input ("<fork>", OP_VOID
, OP_VOID
, OP_VOID
);
2654 trace_output (OP_R2
);
2658 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
2660 trace_output (OP_R2
);
2664 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
2665 if (PARM1
== getpid ())
2667 trace_output (OP_VOID
);
2668 State
.exception
= PARM2
;
2676 case 1: os_sig
= SIGHUP
; break;
2679 case 2: os_sig
= SIGINT
; break;
2682 case 3: os_sig
= SIGQUIT
; break;
2685 case 4: os_sig
= SIGILL
; break;
2688 case 5: os_sig
= SIGTRAP
; break;
2691 case 6: os_sig
= SIGABRT
; break;
2692 #elif defined(SIGIOT)
2693 case 6: os_sig
= SIGIOT
; break;
2696 case 7: os_sig
= SIGEMT
; break;
2699 case 8: os_sig
= SIGFPE
; break;
2702 case 9: os_sig
= SIGKILL
; break;
2705 case 10: os_sig
= SIGBUS
; break;
2708 case 11: os_sig
= SIGSEGV
; break;
2711 case 12: os_sig
= SIGSYS
; break;
2714 case 13: os_sig
= SIGPIPE
; break;
2717 case 14: os_sig
= SIGALRM
; break;
2720 case 15: os_sig
= SIGTERM
; break;
2723 case 16: os_sig
= SIGURG
; break;
2726 case 17: os_sig
= SIGSTOP
; break;
2729 case 18: os_sig
= SIGTSTP
; break;
2732 case 19: os_sig
= SIGCONT
; break;
2735 case 20: os_sig
= SIGCHLD
; break;
2736 #elif defined(SIGCLD)
2737 case 20: os_sig
= SIGCLD
; break;
2740 case 21: os_sig
= SIGTTIN
; break;
2743 case 22: os_sig
= SIGTTOU
; break;
2746 case 23: os_sig
= SIGIO
; break;
2747 #elif defined (SIGPOLL)
2748 case 23: os_sig
= SIGPOLL
; break;
2751 case 24: os_sig
= SIGXCPU
; break;
2754 case 25: os_sig
= SIGXFSZ
; break;
2757 case 26: os_sig
= SIGVTALRM
; break;
2760 case 27: os_sig
= SIGPROF
; break;
2763 case 28: os_sig
= SIGWINCH
; break;
2766 case 29: os_sig
= SIGLOST
; break;
2769 case 30: os_sig
= SIGUSR1
; break;
2772 case 31: os_sig
= SIGUSR2
; break;
2778 trace_output (OP_VOID
);
2779 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Unknown signal %d\n", PARM2
);
2780 State
.exception
= SIGILL
;
2784 RETVAL
= kill (PARM1
, PARM2
);
2785 trace_output (OP_R2
);
2791 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
2792 (char **)MEMPTR (PARM3
));
2793 trace_input ("<execve>", OP_R2
, OP_R3
, OP_R4
);
2794 trace_output (OP_R2
);
2798 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2799 trace_input ("<execv>", OP_R2
, OP_R3
, OP_VOID
);
2800 trace_output (OP_R2
);
2809 RETVAL
= pipe (host_fd
);
2810 SW (buf
, host_fd
[0]);
2811 buf
+= sizeof(uint16
);
2812 SW (buf
, host_fd
[1]);
2813 trace_input ("<pipe>", OP_R2
, OP_VOID
, OP_VOID
);
2814 trace_output (OP_R2
);
2822 RETVAL
= wait (&status
);
2825 trace_input ("<wait>", OP_R2
, OP_VOID
, OP_VOID
);
2826 trace_output (OP_R2
);
2831 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
2833 trace_output (OP_R2
);
2837 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
2838 trace_output (OP_VOID
);
2839 State
.exception
= PARM2
;
2844 RETVAL
= d10v_callback
->read (d10v_callback
, PARM1
, MEMPTR (PARM2
),
2846 trace_input ("<read>", OP_R2
, OP_R3
, OP_R4
);
2847 trace_output (OP_R2
);
2852 RETVAL
= (int)d10v_callback
->write_stdout (d10v_callback
,
2853 MEMPTR (PARM2
), PARM3
);
2855 RETVAL
= (int)d10v_callback
->write (d10v_callback
, PARM1
,
2856 MEMPTR (PARM2
), PARM3
);
2857 trace_input ("<write>", OP_R2
, OP_R3
, OP_R4
);
2858 trace_output (OP_R2
);
2863 unsigned long ret
= d10v_callback
->lseek (d10v_callback
, PARM1
,
2864 (((unsigned long)PARM2
) << 16) || (unsigned long)PARM3
,
2866 RETVAL_HIGH
= ret
>> 16;
2867 RETVAL_LOW
= ret
& 0xffff;
2869 trace_input ("<lseek>", OP_R2
, OP_R3
, OP_R4
);
2870 trace_output (OP_R2R3
);
2874 RETVAL
= d10v_callback
->close (d10v_callback
, PARM1
);
2875 trace_input ("<close>", OP_R2
, OP_VOID
, OP_VOID
);
2876 trace_output (OP_R2
);
2880 RETVAL
= d10v_callback
->open (d10v_callback
, MEMPTR (PARM1
), PARM2
);
2881 trace_input ("<open>", OP_R2
, OP_R3
, OP_R4
);
2882 trace_output (OP_R2
);
2883 trace_input ("<open>", OP_R2
, OP_R3
, OP_R4
);
2884 trace_output (OP_R2
);
2888 State
.exception
= SIG_D10V_EXIT
;
2889 trace_input ("<exit>", OP_R2
, OP_VOID
, OP_VOID
);
2890 trace_output (OP_VOID
);
2894 /* stat system call */
2896 struct stat host_stat
;
2899 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2903 /* The hard-coded offsets and sizes were determined by using
2904 * the D10V compiler on a test program that used struct stat.
2906 SW (buf
, host_stat
.st_dev
);
2907 SW (buf
+2, host_stat
.st_ino
);
2908 SW (buf
+4, host_stat
.st_mode
);
2909 SW (buf
+6, host_stat
.st_nlink
);
2910 SW (buf
+8, host_stat
.st_uid
);
2911 SW (buf
+10, host_stat
.st_gid
);
2912 SW (buf
+12, host_stat
.st_rdev
);
2913 SLW (buf
+16, host_stat
.st_size
);
2914 SLW (buf
+20, host_stat
.st_atime
);
2915 SLW (buf
+28, host_stat
.st_mtime
);
2916 SLW (buf
+36, host_stat
.st_ctime
);
2918 trace_input ("<stat>", OP_R2
, OP_R3
, OP_VOID
);
2919 trace_output (OP_R2
);
2923 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2924 trace_input ("<chown>", OP_R2
, OP_R3
, OP_R4
);
2925 trace_output (OP_R2
);
2929 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
2930 trace_input ("<chmod>", OP_R2
, OP_R3
, OP_R4
);
2931 trace_output (OP_R2
);
2935 /* Cast the second argument to void *, to avoid type mismatch
2936 if a prototype is present. */
2937 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));
2938 trace_input ("<utime>", OP_R2
, OP_R3
, OP_R4
);
2939 trace_output (OP_R2
);
2944 unsigned long ret
= time (PARM1
? MEMPTR (PARM1
) : NULL
);
2945 RETVAL_HIGH
= ret
>> 16;
2946 RETVAL_LOW
= ret
& 0xffff;
2948 trace_input ("<time>", OP_R2
, OP_R3
, OP_R4
);
2949 trace_output (OP_R2R3
);
2955 RETERR
= d10v_callback
->get_errno(d10v_callback
);
2960 /* Trap 1 prints a string */
2962 char *fstr
= dmem_addr(State
.regs
[2]);
2963 fputs (fstr
, stdout
);
2968 /* Trap 2 calls printf */
2970 char *fstr
= dmem_addr(State
.regs
[2]);
2971 (*d10v_callback
->printf_filtered
) (d10v_callback
, fstr
,
2972 (int16
)State
.regs
[3],
2973 (int16
)State
.regs
[4],
2974 (int16
)State
.regs
[5]);
2979 /* Trap 3 writes a character */
2980 putchar (State
.regs
[2]);
2990 trace_input ("tst0i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2991 State
.F1
= State
.F0
;
2992 State
.F0
= (State
.regs
[OP
[0]] & OP
[1]) ? 1 : 0;
2993 trace_output (OP_FLAG
);
3000 trace_input ("tst1i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3001 State
.F1
= State
.F0
;
3002 State
.F0
= (~(State
.regs
[OP
[0]]) & OP
[1]) ? 1 : 0;
3003 trace_output (OP_FLAG
);
3010 trace_input ("wait", OP_VOID
, OP_VOID
, OP_VOID
);
3012 trace_output (OP_VOID
);
3019 trace_input ("xor", OP_REG
, OP_REG
, OP_VOID
);
3020 State
.regs
[OP
[0]] ^= State
.regs
[OP
[1]];
3021 trace_output (OP_REG
);
3028 trace_input ("xor3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
3029 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] ^ OP
[2];
3030 trace_output (OP_REG
);