1 /* frv simulator support code
2 Copyright (C) 1998-2021 Free Software Foundation, Inc.
3 Contributed by Red Hat.
5 This file is part of the GNU simulators.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* Main header for the frv. */
22 /* This is a global setting. Different cpu families can't mix-n-match -scache
23 and -pbb. However some cpu families may use -simple while others use
24 one of -scache/-pbb. ???? */
25 #define WITH_SCACHE_PBB 0
28 #include "sim-basics.h"
29 #include "cgen-types.h"
34 #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) \
35 frv_sim_engine_halt_hook ((SD), (LAST_CPU), (CIA))
37 #define SIM_ENGINE_RESTART_HOOK(SD, LAST_CPU, CIA) 0
43 #include "registers.h"
46 void frv_sim_engine_halt_hook (SIM_DESC
, SIM_CPU
*, sim_cia
);
48 extern void frv_sim_close (SIM_DESC sd
, int quitting
);
49 #define SIM_CLOSE_HOOK(...) frv_sim_close (__VA_ARGS__)
51 /* The _sim_cpu struct. */
54 /* sim/common cpu base. */
57 /* Static parts of cgen. */
60 /* CPU specific parts go here.
61 Note that in files that don't need to access these pieces WANT_CPU_FOO
62 won't be defined and thus these parts won't appear. This is ok in the
63 sense that things work. It is a source of bugs though.
64 One has to of course be careful to not take the size of this
65 struct and no structure members accessed in non-cpu specific files can
66 go after here. Oh for a better language. */
67 #if defined (WANT_CPU_FRVBF)
68 FRVBF_CPU_DATA cpu_data
;
70 /* Control information for registers */
71 FRV_REGISTER_CONTROL register_control
;
72 #define CPU_REGISTER_CONTROL(cpu) (& (cpu)->register_control)
75 #define CPU_VLIW(cpu) (& (cpu)->vliw)
78 #define CPU_INSN_CACHE(cpu) (& (cpu)->insn_cache)
81 #define CPU_DATA_CACHE(cpu) (& (cpu)->data_cache)
83 FRV_PROFILE_STATE profile_state
;
84 #define CPU_PROFILE_STATE(cpu) (& (cpu)->profile_state)
87 #define CPU_DEBUG_STATE(cpu) ((cpu)->debug_state)
90 #define CPU_LOAD_ADDRESS(cpu) ((cpu)->load_address)
93 #define CPU_LOAD_LENGTH(cpu) ((cpu)->load_length)
96 #define CPU_LOAD_SIGNED(cpu) ((cpu)->load_flag)
97 #define CPU_LOAD_LOCK(cpu) ((cpu)->load_flag)
100 #define CPU_RSTR_INVALIDATE(cpu) ((cpu)->store_flag)
102 unsigned long elf_flags
;
103 #define CPU_ELF_FLAGS(cpu) ((cpu)->elf_flags)
104 #endif /* defined (WANT_CPU_FRVBF) */
107 /* The sim_state struct. */
110 sim_cpu
*cpu
[MAX_NR_PROCESSORS
];
112 CGEN_STATE cgen_state
;
119 /* Catch address exceptions. */
120 extern SIM_CORE_SIGNAL_FN frv_core_signal
;
121 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
122 frv_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
125 /* Default memory size. */
126 #define FRV_DEFAULT_MEM_SIZE 0x800000 /* 8M */