2 Copyright (C) 1999-2021 Free Software Foundation, Inc.
3 Contributed by Red Hat.
5 This file is part of the GNU simulators.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* This must come before any other includes. */
23 #define WANT_CPU frvbf
24 #define WANT_CPU_FRVBF
27 #include "targ-vals.h"
28 #include "cgen-engine.h"
31 #include "sim-signal.h"
32 #include "sim/callback.h"
35 #include "libiberty.h"
39 CGEN_ATTR_VALUE_ENUM_TYPE frv_current_fm_slot
;
41 /* The semantic code invokes this for invalid (unrecognized) instructions. */
44 sim_engine_invalid_insn (SIM_CPU
*current_cpu
, IADDR cia
, SEM_PC vpc
)
46 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
50 /* Process an address exception. */
53 frv_core_signal (SIM_DESC sd
, SIM_CPU
*current_cpu
, sim_cia cia
,
54 unsigned int map
, int nr_bytes
, address_word addr
,
55 transfer_type transfer
, sim_core_signals sig
)
57 if (sig
== sim_core_unaligned_signal
)
59 if (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr400
60 || STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr450
)
61 frv_queue_data_access_error_interrupt (current_cpu
, addr
);
63 frv_queue_mem_address_not_aligned_interrupt (current_cpu
, addr
);
67 sim_core_signal (sd
, current_cpu
, cia
, map
, nr_bytes
, addr
, transfer
, sig
);
71 frv_sim_engine_halt_hook (SIM_DESC sd
, SIM_CPU
*current_cpu
, sim_cia cia
)
74 if (current_cpu
!= NULL
)
75 CPU_PC_SET (current_cpu
, cia
);
77 /* Invalidate the insn and data caches of all cpus. */
78 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
80 current_cpu
= STATE_CPU (sd
, i
);
81 frv_cache_invalidate_all (CPU_INSN_CACHE (current_cpu
), 0);
82 frv_cache_invalidate_all (CPU_DATA_CACHE (current_cpu
), 1);
87 /* Read/write functions for system call interface. */
90 syscall_read_mem (host_callback
*cb
, struct cb_syscall
*sc
,
91 unsigned long taddr
, char *buf
, int bytes
)
93 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
94 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
96 frv_cache_invalidate_all (CPU_DATA_CACHE (cpu
), 1);
97 return sim_core_read_buffer (sd
, cpu
, read_map
, buf
, taddr
, bytes
);
101 syscall_write_mem (host_callback
*cb
, struct cb_syscall
*sc
,
102 unsigned long taddr
, const char *buf
, int bytes
)
104 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
105 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
107 frv_cache_invalidate_all (CPU_INSN_CACHE (cpu
), 0);
108 frv_cache_invalidate_all (CPU_DATA_CACHE (cpu
), 1);
109 return sim_core_write_buffer (sd
, cpu
, write_map
, buf
, taddr
, bytes
);
112 /* Handle TRA and TIRA insns. */
114 frv_itrap (SIM_CPU
*current_cpu
, PCADDR pc
, USI base
, SI offset
)
116 SIM_DESC sd
= CPU_STATE (current_cpu
);
117 host_callback
*cb
= STATE_CALLBACK (sd
);
118 USI num
= ((base
+ offset
) & 0x7f) + 0x80;
120 if (STATE_ENVIRONMENT (sd
) == OPERATING_ENVIRONMENT
)
122 frv_queue_software_interrupt (current_cpu
, num
);
131 CB_SYSCALL_INIT (&s
);
132 s
.func
= GET_H_GR (7);
133 s
.arg1
= GET_H_GR (8);
134 s
.arg2
= GET_H_GR (9);
135 s
.arg3
= GET_H_GR (10);
137 if (s
.func
== TARGET_SYS_exit
)
139 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_exited
, s
.arg1
);
143 s
.p2
= (PTR
) current_cpu
;
144 s
.read_mem
= syscall_read_mem
;
145 s
.write_mem
= syscall_write_mem
;
147 SET_H_GR (8, s
.result
);
148 SET_H_GR (9, s
.result2
);
149 SET_H_GR (10, s
.errcode
);
153 case TRAP_BREAKPOINT
:
154 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
157 /* Add support for dumping registers, either at fixed traps, or all
158 unknown traps if configured with --enable-sim-trapdump. */
161 frv_queue_software_interrupt (current_cpu
, num
);
173 #if TRAPDUMP || (defined (TRAP_REGDUMP1)) || (defined (TRAP_REGDUMP2))
179 if (STATE_TEXT_SECTION (sd
)
180 && pc
>= STATE_TEXT_START (sd
)
181 && pc
< STATE_TEXT_END (sd
))
183 const char *pc_filename
= (const char *)0;
184 const char *pc_function
= (const char *)0;
185 unsigned int pc_linenum
= 0;
187 if (bfd_find_nearest_line (STATE_PROG_BFD (sd
),
188 STATE_TEXT_SECTION (sd
),
189 (struct bfd_symbol
**) 0,
190 pc
- STATE_TEXT_START (sd
),
191 &pc_filename
, &pc_function
, &pc_linenum
)
192 && (pc_function
|| pc_filename
))
199 strcpy (p
, pc_function
);
204 char *q
= (char *) strrchr (pc_filename
, '/');
205 strcpy (p
, (q
) ? q
+1 : pc_filename
);
211 sprintf (p
, " line %d", pc_linenum
);
217 if ((p
+1) - buf
> sizeof (buf
))
223 "\nRegister dump, pc = 0x%.8x%s, base = %u, offset = %d\n",
224 (unsigned)pc
, buf
, (unsigned)base
, (int)offset
);
226 for (i
= 0; i
< 64; i
+= 8)
228 long g0
= (long)GET_H_GR (i
);
229 long g1
= (long)GET_H_GR (i
+1);
230 long g2
= (long)GET_H_GR (i
+2);
231 long g3
= (long)GET_H_GR (i
+3);
232 long g4
= (long)GET_H_GR (i
+4);
233 long g5
= (long)GET_H_GR (i
+5);
234 long g6
= (long)GET_H_GR (i
+6);
235 long g7
= (long)GET_H_GR (i
+7);
237 if ((g0
| g1
| g2
| g3
| g4
| g5
| g6
| g7
) != 0)
239 "\tgr%02d - gr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
240 i
, i
+7, g0
, g1
, g2
, g3
, g4
, g5
, g6
, g7
);
243 for (i
= 0; i
< 64; i
+= 8)
245 long f0
= (long)GET_H_FR (i
);
246 long f1
= (long)GET_H_FR (i
+1);
247 long f2
= (long)GET_H_FR (i
+2);
248 long f3
= (long)GET_H_FR (i
+3);
249 long f4
= (long)GET_H_FR (i
+4);
250 long f5
= (long)GET_H_FR (i
+5);
251 long f6
= (long)GET_H_FR (i
+6);
252 long f7
= (long)GET_H_FR (i
+7);
254 if ((f0
| f1
| f2
| f3
| f4
| f5
| f6
| f7
) != 0)
256 "\tfr%02d - fr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
257 i
, i
+7, f0
, f1
, f2
, f3
, f4
, f5
, f6
, f7
);
261 "\tlr/lcr/cc/ccc: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
262 (long)GET_H_SPR (272),
263 (long)GET_H_SPR (273),
264 (long)GET_H_SPR (256),
265 (long)GET_H_SPR (263));
272 /* Handle the MTRAP insn. */
274 frv_mtrap (SIM_CPU
*current_cpu
)
276 SIM_DESC sd
= CPU_STATE (current_cpu
);
278 /* Check the status of media exceptions in MSR0. */
279 SI msr
= GET_MSR (0);
280 if (GET_MSR_AOVF (msr
)
281 || (GET_MSR_MTT (msr
) && STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_fr550
))
282 frv_queue_program_interrupt (current_cpu
, FRV_MP_EXCEPTION
);
285 /* Handle the BREAK insn. */
287 frv_break (SIM_CPU
*current_cpu
)
290 SIM_DESC sd
= CPU_STATE (current_cpu
);
292 if (STATE_ENVIRONMENT (sd
) != OPERATING_ENVIRONMENT
)
294 /* Invalidate the insn cache because the debugger will presumably
295 replace the breakpoint insn with the real one. */
296 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
299 frv_queue_break_interrupt (current_cpu
);
302 /* Return from trap. */
304 frv_rett (SIM_CPU
*current_cpu
, PCADDR pc
, BI debug_field
)
307 /* if (normal running mode and debug_field==0
311 else if (debug running mode and debug_field==1)
315 change to normal running mode
317 int psr_s
= GET_H_PSR_S ();
318 int psr_et
= GET_H_PSR_ET ();
320 /* Check for exceptions in the priority order listed in the FRV Architecture
324 /* Halt if PSR.ET is not set. See chapter 6 of the LSI. */
327 SIM_DESC sd
= CPU_STATE (current_cpu
);
328 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
331 /* privileged_instruction interrupt will have already been queued by
332 frv_detect_insn_access_interrupts. */
337 /* Halt if PSR.S is set. See chapter 6 of the LSI. */
340 SIM_DESC sd
= CPU_STATE (current_cpu
);
341 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
344 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
347 else if (! CPU_DEBUG_STATE (current_cpu
) && debug_field
== 0)
349 USI psr
= GET_PSR ();
350 /* Return from normal running state. */
351 new_pc
= GET_H_SPR (H_SPR_PCSR
);
353 SET_PSR_S (psr
, GET_PSR_PS (psr
));
354 sim_queue_fn_si_write (current_cpu
, frvbf_h_spr_set
, H_SPR_PSR
, psr
);
356 else if (CPU_DEBUG_STATE (current_cpu
) && debug_field
== 1)
358 USI psr
= GET_PSR ();
359 /* Return from debug state. */
360 new_pc
= GET_H_SPR (H_SPR_BPCSR
);
361 SET_PSR_ET (psr
, GET_H_BPSR_BET ());
362 SET_PSR_S (psr
, GET_H_BPSR_BS ());
363 sim_queue_fn_si_write (current_cpu
, frvbf_h_spr_set
, H_SPR_PSR
, psr
);
364 CPU_DEBUG_STATE (current_cpu
) = 0;
372 /* Functions for handling non-excepting instruction side effects. */
373 static SI
next_available_nesr (SIM_CPU
*current_cpu
, SI current_index
)
375 FRV_REGISTER_CONTROL
*control
= CPU_REGISTER_CONTROL (current_cpu
);
376 if (control
->spr
[H_SPR_NECR
].implemented
)
379 USI necr
= GET_NECR ();
381 /* See if any NESRs are implemented. First need to check the validity of
383 if (! GET_NECR_VALID (necr
))
386 limit
= GET_NECR_NEN (necr
);
387 for (++current_index
; current_index
< limit
; ++current_index
)
389 SI nesr
= GET_NESR (current_index
);
390 if (! GET_NESR_VALID (nesr
))
391 return current_index
;
397 static SI
next_valid_nesr (SIM_CPU
*current_cpu
, SI current_index
)
399 FRV_REGISTER_CONTROL
*control
= CPU_REGISTER_CONTROL (current_cpu
);
400 if (control
->spr
[H_SPR_NECR
].implemented
)
403 USI necr
= GET_NECR ();
405 /* See if any NESRs are implemented. First need to check the validity of
407 if (! GET_NECR_VALID (necr
))
410 limit
= GET_NECR_NEN (necr
);
411 for (++current_index
; current_index
< limit
; ++current_index
)
413 SI nesr
= GET_NESR (current_index
);
414 if (GET_NESR_VALID (nesr
))
415 return current_index
;
422 frvbf_check_non_excepting_load (
423 SIM_CPU
*current_cpu
, SI base_index
, SI disp_index
, SI target_index
,
424 SI immediate_disp
, QI data_size
, BI is_float
427 BI rc
= 1; /* perform the load. */
428 SIM_DESC sd
= CPU_STATE (current_cpu
);
438 FRV_REGISTER_CONTROL
*control
;
440 SI address
= GET_H_GR (base_index
);
442 address
+= GET_H_GR (disp_index
);
444 address
+= immediate_disp
;
446 /* Check for interrupt factors. */
464 if (target_index
& 1)
470 if (target_index
& 3)
475 IADDR pc
= GET_H_PC ();
476 sim_engine_abort (sd
, current_cpu
, pc
,
477 "check_non_excepting_load: Incorrect data_size\n");
482 control
= CPU_REGISTER_CONTROL (current_cpu
);
483 if (control
->spr
[H_SPR_NECR
].implemented
)
486 do_elos
= GET_NECR_VALID (necr
) && GET_NECR_ELOS (necr
);
491 /* NECR, NESR, NEEAR are only implemented for the full frv machine. */
494 ne_index
= next_available_nesr (current_cpu
, NO_NESR
);
495 if (ne_index
== NO_NESR
)
497 IADDR pc
= GET_H_PC ();
498 sim_engine_abort (sd
, current_cpu
, pc
,
499 "No available NESR register\n");
502 /* Fill in the basic fields of the NESR. */
503 nesr
= GET_NESR (ne_index
);
504 SET_NESR_VALID (nesr
);
506 SET_NESR_DRN (nesr
, target_index
);
507 SET_NESR_SIZE (nesr
, data_size
);
508 SET_NESR_NEAN (nesr
, ne_index
);
512 CLEAR_NESR_FR (nesr
);
514 /* Set the corresponding NEEAR. */
515 SET_NEEAR (ne_index
, address
);
517 SET_NESR_DAEC (nesr
, 0);
518 SET_NESR_REC (nesr
, 0);
519 SET_NESR_EC (nesr
, 0);
522 /* Set the NE flag corresponding to the target register if an interrupt
524 daec is not checked here yet, but is declared for future reference. */
526 NE_base
= H_SPR_FNER0
;
528 NE_base
= H_SPR_GNER0
;
530 GET_NE_FLAGS (NE_flags
, NE_base
);
533 SET_NE_FLAG (NE_flags
, target_index
);
535 SET_NESR_REC (nesr
, NESR_REGISTER_NOT_ALIGNED
);
540 SET_NE_FLAG (NE_flags
, target_index
);
542 SET_NESR_EC (nesr
, NESR_MEM_ADDRESS_NOT_ALIGNED
);
546 SET_NESR (ne_index
, nesr
);
548 /* If no interrupt factor was detected then set the NE flag on the
549 target register if the NE flag on one of the input registers
551 if (! rec
&& ! ec
&& ! daec
)
553 BI ne_flag
= GET_NE_FLAG (NE_flags
, base_index
);
555 ne_flag
|= GET_NE_FLAG (NE_flags
, disp_index
);
558 SET_NE_FLAG (NE_flags
, target_index
);
559 rc
= 0; /* Do not perform the load. */
562 CLEAR_NE_FLAG (NE_flags
, target_index
);
565 SET_NE_FLAGS (NE_base
, NE_flags
);
567 return rc
; /* perform the load? */
570 /* Record state for media exception: media_cr_not_aligned. */
572 frvbf_media_cr_not_aligned (SIM_CPU
*current_cpu
)
574 SIM_DESC sd
= CPU_STATE (current_cpu
);
576 /* On some machines this generates an illegal_instruction interrupt. */
577 switch (STATE_ARCHITECTURE (sd
)->mach
)
579 /* Note: there is a discrepancy between V2.2 of the FR400
580 instruction manual and the various FR4xx LSI specs. The former
581 claims that unaligned registers cause an mp_exception while the
582 latter say it's an illegal_instruction. The LSI specs appear
583 to be correct since MTT is fixed at 1. */
587 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
590 frv_set_mp_exception_registers (current_cpu
, MTT_CR_NOT_ALIGNED
, 0);
595 /* Record state for media exception: media_acc_not_aligned. */
597 frvbf_media_acc_not_aligned (SIM_CPU
*current_cpu
)
599 SIM_DESC sd
= CPU_STATE (current_cpu
);
601 /* On some machines this generates an illegal_instruction interrupt. */
602 switch (STATE_ARCHITECTURE (sd
)->mach
)
604 /* See comment in frvbf_cr_not_aligned(). */
608 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
611 frv_set_mp_exception_registers (current_cpu
, MTT_ACC_NOT_ALIGNED
, 0);
616 /* Record state for media exception: media_register_not_aligned. */
618 frvbf_media_register_not_aligned (SIM_CPU
*current_cpu
)
620 SIM_DESC sd
= CPU_STATE (current_cpu
);
622 /* On some machines this generates an illegal_instruction interrupt. */
623 switch (STATE_ARCHITECTURE (sd
)->mach
)
625 /* See comment in frvbf_cr_not_aligned(). */
629 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
632 frv_set_mp_exception_registers (current_cpu
, MTT_INVALID_FR
, 0);
637 /* Record state for media exception: media_overflow. */
639 frvbf_media_overflow (SIM_CPU
*current_cpu
, int sie
)
641 frv_set_mp_exception_registers (current_cpu
, MTT_OVERFLOW
, sie
);
644 /* Queue a division exception. */
646 frvbf_division_exception (SIM_CPU
*current_cpu
, enum frv_dtt dtt
,
647 int target_index
, int non_excepting
)
649 /* If there was an overflow and it is masked, then record it in
651 USI isr
= GET_ISR ();
652 if ((dtt
& FRV_DTT_OVERFLOW
) && GET_ISR_EDE (isr
))
654 dtt
&= ~FRV_DTT_OVERFLOW
;
658 if (dtt
!= FRV_DTT_NO_EXCEPTION
)
662 /* Non excepting instruction, simply set the NE flag for the target
665 GET_NE_FLAGS (NE_flags
, H_SPR_GNER0
);
666 SET_NE_FLAG (NE_flags
, target_index
);
667 SET_NE_FLAGS (H_SPR_GNER0
, NE_flags
);
670 frv_queue_division_exception_interrupt (current_cpu
, dtt
);
676 frvbf_check_recovering_store (
677 SIM_CPU
*current_cpu
, PCADDR address
, SI regno
, int size
, int is_float
680 FRV_CACHE
*cache
= CPU_DATA_CACHE (current_cpu
);
683 CPU_RSTR_INVALIDATE(current_cpu
) = 0;
685 for (reg_ix
= next_valid_nesr (current_cpu
, NO_NESR
);
687 reg_ix
= next_valid_nesr (current_cpu
, reg_ix
))
689 if (address
== GET_H_SPR (H_SPR_NEEAR0
+ reg_ix
))
691 SI nesr
= GET_NESR (reg_ix
);
692 int nesr_drn
= GET_NESR_DRN (nesr
);
693 BI nesr_fr
= GET_NESR_FR (nesr
);
696 /* Invalidate cache block containing this address.
697 If we need to count cycles, then the cache operation will be
698 initiated from the model profiling functions.
699 See frvbf_model_.... */
702 CPU_RSTR_INVALIDATE(current_cpu
) = 1;
703 CPU_LOAD_ADDRESS (current_cpu
) = address
;
706 frv_cache_invalidate (cache
, address
, 1/* flush */);
708 /* Copy the stored value to the register indicated by NESR.DRN. */
709 for (remain
= size
; remain
> 0; remain
-= 4)
714 value
= GET_H_FR (regno
);
716 value
= GET_H_GR (regno
);
731 sim_queue_fn_sf_write (current_cpu
, frvbf_h_fr_set
, nesr_drn
,
734 sim_queue_fn_si_write (current_cpu
, frvbf_h_gr_set
, nesr_drn
,
740 break; /* Only consider the first matching register. */
742 } /* loop over active neear registers. */
746 frvbf_check_acc_range (SIM_CPU
*current_cpu
, SI regno
)
748 /* Only applicable to fr550 */
749 SIM_DESC sd
= CPU_STATE (current_cpu
);
750 if (STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_fr550
)
753 /* On the fr550, media insns in slots 0 and 2 can only access
754 accumulators acc0-acc3. Insns in slots 1 and 3 can only access
755 accumulators acc4-acc7 */
756 switch (frv_current_fm_slot
)
761 return 1; /* all is ok */
766 return 1; /* all is ok */
770 /* The specified accumulator is out of range. Queue an illegal_instruction
772 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
777 frvbf_check_swap_address (SIM_CPU
*current_cpu
, SI address
)
779 /* Only applicable to fr550 */
780 SIM_DESC sd
= CPU_STATE (current_cpu
);
781 if (STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_fr550
)
784 /* Adress must be aligned on a word boundary. */
786 frv_queue_data_access_exception_interrupt (current_cpu
);
790 clear_nesr_neear (SIM_CPU
*current_cpu
, SI target_index
, BI is_float
)
794 /* Only implemented for full frv. */
795 SIM_DESC sd
= CPU_STATE (current_cpu
);
796 if (STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_frv
)
799 /* Clear the appropriate NESR and NEEAR registers. */
800 for (reg_ix
= next_valid_nesr (current_cpu
, NO_NESR
);
802 reg_ix
= next_valid_nesr (current_cpu
, reg_ix
))
805 /* The register is available, now check if it is active. */
806 nesr
= GET_NESR (reg_ix
);
807 if (GET_NESR_FR (nesr
) == is_float
)
809 if (target_index
< 0 || GET_NESR_DRN (nesr
) == target_index
)
811 SET_NESR (reg_ix
, 0);
812 SET_NEEAR (reg_ix
, 0);
820 SIM_CPU
*current_cpu
,
830 GET_NE_FLAGS (NE_flags
, NE_base
);
831 if (target_index
>= 0)
832 CLEAR_NE_FLAG (NE_flags
, target_index
);
840 SET_NE_FLAGS (NE_base
, NE_flags
);
843 /* Return 1 if the given register is available, 0 otherwise. TARGET_INDEX==-1
844 means to check for any register available. */
846 which_registers_available (
847 SIM_CPU
*current_cpu
, int *hi_available
, int *lo_available
, int is_float
851 frv_fr_registers_available (current_cpu
, hi_available
, lo_available
);
853 frv_gr_registers_available (current_cpu
, hi_available
, lo_available
);
857 frvbf_clear_ne_flags (SIM_CPU
*current_cpu
, SI target_index
, BI is_float
)
864 FRV_REGISTER_CONTROL
*control
;
866 /* Check for availability of the target register(s). */
867 which_registers_available (current_cpu
, & hi_available
, & lo_available
,
870 /* Check to make sure that the target register is available. */
871 if (! frv_check_register_access (current_cpu
, target_index
,
872 hi_available
, lo_available
))
875 /* Determine whether we're working with GR or FR registers. */
877 NE_base
= H_SPR_FNER0
;
879 NE_base
= H_SPR_GNER0
;
881 /* Always clear the appropriate NE flags. */
882 clear_ne_flags (current_cpu
, target_index
, hi_available
, lo_available
,
885 /* Clear the appropriate NESR and NEEAR registers. */
886 control
= CPU_REGISTER_CONTROL (current_cpu
);
887 if (control
->spr
[H_SPR_NECR
].implemented
)
890 if (GET_NECR_VALID (necr
) && GET_NECR_ELOS (necr
))
891 clear_nesr_neear (current_cpu
, target_index
, is_float
);
896 frvbf_commit (SIM_CPU
*current_cpu
, SI target_index
, BI is_float
)
905 FRV_REGISTER_CONTROL
*control
;
907 /* Check for availability of the target register(s). */
908 which_registers_available (current_cpu
, & hi_available
, & lo_available
,
911 /* Check to make sure that the target register is available. */
912 if (! frv_check_register_access (current_cpu
, target_index
,
913 hi_available
, lo_available
))
916 /* Determine whether we're working with GR or FR registers. */
918 NE_base
= H_SPR_FNER0
;
920 NE_base
= H_SPR_GNER0
;
922 /* Determine whether a ne exception is pending. */
923 GET_NE_FLAGS (NE_flags
, NE_base
);
924 if (target_index
>= 0)
925 NE_flag
= GET_NE_FLAG (NE_flags
, target_index
);
928 NE_flag
= (hi_available
&& NE_flags
[0] != 0)
929 || (lo_available
&& NE_flags
[1] != 0);
932 /* Always clear the appropriate NE flags. */
933 clear_ne_flags (current_cpu
, target_index
, hi_available
, lo_available
,
936 control
= CPU_REGISTER_CONTROL (current_cpu
);
937 if (control
->spr
[H_SPR_NECR
].implemented
)
940 if (GET_NECR_VALID (necr
) && GET_NECR_ELOS (necr
) && NE_flag
)
942 /* Clear the appropriate NESR and NEEAR registers. */
943 clear_nesr_neear (current_cpu
, target_index
, is_float
);
944 frv_queue_program_interrupt (current_cpu
, FRV_COMMIT_EXCEPTION
);
949 /* Generate the appropriate fp_exception(s) based on the given status code. */
951 frvbf_fpu_error (CGEN_FPU
* fpu
, int status
)
953 struct frv_fp_exception_info fp_info
= {
954 FSR_NO_EXCEPTION
, FTT_IEEE_754_EXCEPTION
958 (sim_fpu_status_invalid_snan
|
959 sim_fpu_status_invalid_qnan
|
960 sim_fpu_status_invalid_isi
|
961 sim_fpu_status_invalid_idi
|
962 sim_fpu_status_invalid_zdz
|
963 sim_fpu_status_invalid_imz
|
964 sim_fpu_status_invalid_cvi
|
965 sim_fpu_status_invalid_cmp
|
966 sim_fpu_status_invalid_sqrt
))
967 fp_info
.fsr_mask
|= FSR_INVALID_OPERATION
;
969 if (status
& sim_fpu_status_invalid_div0
)
970 fp_info
.fsr_mask
|= FSR_DIVISION_BY_ZERO
;
972 if (status
& sim_fpu_status_inexact
)
973 fp_info
.fsr_mask
|= FSR_INEXACT
;
975 if (status
& sim_fpu_status_overflow
)
976 fp_info
.fsr_mask
|= FSR_OVERFLOW
;
978 if (status
& sim_fpu_status_underflow
)
979 fp_info
.fsr_mask
|= FSR_UNDERFLOW
;
981 if (status
& sim_fpu_status_denorm
)
983 fp_info
.fsr_mask
|= FSR_DENORMAL_INPUT
;
984 fp_info
.ftt
= FTT_DENORMAL_INPUT
;
987 if (fp_info
.fsr_mask
!= FSR_NO_EXCEPTION
)
989 SIM_CPU
*current_cpu
= (SIM_CPU
*)fpu
->owner
;
990 frv_queue_fp_exception_interrupt (current_cpu
, & fp_info
);