1 /* Simulator instruction operand reader for m32r.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 /* The labels have the case they have because the enum of insn types
29 is all uppercase and in the non-stdc case the fmt symbol is built
30 into the enum name. */
36 { M32RX_XINSN_ILLEGAL
, && case_read_READ_ILLEGAL
},
37 { M32RX_XINSN_ADD
, && case_read_READ_FMT_ADD
},
38 { M32RX_XINSN_ADD3
, && case_read_READ_FMT_ADD3
},
39 { M32RX_XINSN_AND
, && case_read_READ_FMT_ADD
},
40 { M32RX_XINSN_AND3
, && case_read_READ_FMT_AND3
},
41 { M32RX_XINSN_OR
, && case_read_READ_FMT_ADD
},
42 { M32RX_XINSN_OR3
, && case_read_READ_FMT_OR3
},
43 { M32RX_XINSN_XOR
, && case_read_READ_FMT_ADD
},
44 { M32RX_XINSN_XOR3
, && case_read_READ_FMT_AND3
},
45 { M32RX_XINSN_ADDI
, && case_read_READ_FMT_ADDI
},
46 { M32RX_XINSN_ADDV
, && case_read_READ_FMT_ADDV
},
47 { M32RX_XINSN_ADDV3
, && case_read_READ_FMT_ADDV3
},
48 { M32RX_XINSN_ADDX
, && case_read_READ_FMT_ADDX
},
49 { M32RX_XINSN_BC8
, && case_read_READ_FMT_BC8
},
50 { M32RX_XINSN_BC24
, && case_read_READ_FMT_BC24
},
51 { M32RX_XINSN_BEQ
, && case_read_READ_FMT_BEQ
},
52 { M32RX_XINSN_BEQZ
, && case_read_READ_FMT_BEQZ
},
53 { M32RX_XINSN_BGEZ
, && case_read_READ_FMT_BEQZ
},
54 { M32RX_XINSN_BGTZ
, && case_read_READ_FMT_BEQZ
},
55 { M32RX_XINSN_BLEZ
, && case_read_READ_FMT_BEQZ
},
56 { M32RX_XINSN_BLTZ
, && case_read_READ_FMT_BEQZ
},
57 { M32RX_XINSN_BNEZ
, && case_read_READ_FMT_BEQZ
},
58 { M32RX_XINSN_BL8
, && case_read_READ_FMT_BL8
},
59 { M32RX_XINSN_BL24
, && case_read_READ_FMT_BL24
},
60 { M32RX_XINSN_BCL8
, && case_read_READ_FMT_BCL8
},
61 { M32RX_XINSN_BCL24
, && case_read_READ_FMT_BCL24
},
62 { M32RX_XINSN_BNC8
, && case_read_READ_FMT_BC8
},
63 { M32RX_XINSN_BNC24
, && case_read_READ_FMT_BC24
},
64 { M32RX_XINSN_BNE
, && case_read_READ_FMT_BEQ
},
65 { M32RX_XINSN_BRA8
, && case_read_READ_FMT_BRA8
},
66 { M32RX_XINSN_BRA24
, && case_read_READ_FMT_BRA24
},
67 { M32RX_XINSN_BNCL8
, && case_read_READ_FMT_BCL8
},
68 { M32RX_XINSN_BNCL24
, && case_read_READ_FMT_BCL24
},
69 { M32RX_XINSN_CMP
, && case_read_READ_FMT_CMP
},
70 { M32RX_XINSN_CMPI
, && case_read_READ_FMT_CMPI
},
71 { M32RX_XINSN_CMPU
, && case_read_READ_FMT_CMP
},
72 { M32RX_XINSN_CMPUI
, && case_read_READ_FMT_CMPI
},
73 { M32RX_XINSN_CMPEQ
, && case_read_READ_FMT_CMP
},
74 { M32RX_XINSN_CMPZ
, && case_read_READ_FMT_CMPZ
},
75 { M32RX_XINSN_DIV
, && case_read_READ_FMT_DIV
},
76 { M32RX_XINSN_DIVU
, && case_read_READ_FMT_DIV
},
77 { M32RX_XINSN_REM
, && case_read_READ_FMT_DIV
},
78 { M32RX_XINSN_REMU
, && case_read_READ_FMT_DIV
},
79 { M32RX_XINSN_DIVH
, && case_read_READ_FMT_DIV
},
80 { M32RX_XINSN_JC
, && case_read_READ_FMT_JC
},
81 { M32RX_XINSN_JNC
, && case_read_READ_FMT_JC
},
82 { M32RX_XINSN_JL
, && case_read_READ_FMT_JL
},
83 { M32RX_XINSN_JMP
, && case_read_READ_FMT_JMP
},
84 { M32RX_XINSN_LD
, && case_read_READ_FMT_LD
},
85 { M32RX_XINSN_LD_D
, && case_read_READ_FMT_LD_D
},
86 { M32RX_XINSN_LDB
, && case_read_READ_FMT_LDB
},
87 { M32RX_XINSN_LDB_D
, && case_read_READ_FMT_LDB_D
},
88 { M32RX_XINSN_LDH
, && case_read_READ_FMT_LDH
},
89 { M32RX_XINSN_LDH_D
, && case_read_READ_FMT_LDH_D
},
90 { M32RX_XINSN_LDUB
, && case_read_READ_FMT_LDB
},
91 { M32RX_XINSN_LDUB_D
, && case_read_READ_FMT_LDB_D
},
92 { M32RX_XINSN_LDUH
, && case_read_READ_FMT_LDH
},
93 { M32RX_XINSN_LDUH_D
, && case_read_READ_FMT_LDH_D
},
94 { M32RX_XINSN_LD_PLUS
, && case_read_READ_FMT_LD_PLUS
},
95 { M32RX_XINSN_LD24
, && case_read_READ_FMT_LD24
},
96 { M32RX_XINSN_LDI8
, && case_read_READ_FMT_LDI8
},
97 { M32RX_XINSN_LDI16
, && case_read_READ_FMT_LDI16
},
98 { M32RX_XINSN_LOCK
, && case_read_READ_FMT_LOCK
},
99 { M32RX_XINSN_MACHI_A
, && case_read_READ_FMT_MACHI_A
},
100 { M32RX_XINSN_MACLO_A
, && case_read_READ_FMT_MACHI_A
},
101 { M32RX_XINSN_MACWHI_A
, && case_read_READ_FMT_MACHI_A
},
102 { M32RX_XINSN_MACWLO_A
, && case_read_READ_FMT_MACHI_A
},
103 { M32RX_XINSN_MUL
, && case_read_READ_FMT_ADD
},
104 { M32RX_XINSN_MULHI_A
, && case_read_READ_FMT_MULHI_A
},
105 { M32RX_XINSN_MULLO_A
, && case_read_READ_FMT_MULHI_A
},
106 { M32RX_XINSN_MULWHI_A
, && case_read_READ_FMT_MULHI_A
},
107 { M32RX_XINSN_MULWLO_A
, && case_read_READ_FMT_MULHI_A
},
108 { M32RX_XINSN_MV
, && case_read_READ_FMT_MV
},
109 { M32RX_XINSN_MVFACHI_A
, && case_read_READ_FMT_MVFACHI_A
},
110 { M32RX_XINSN_MVFACLO_A
, && case_read_READ_FMT_MVFACHI_A
},
111 { M32RX_XINSN_MVFACMI_A
, && case_read_READ_FMT_MVFACHI_A
},
112 { M32RX_XINSN_MVFC
, && case_read_READ_FMT_MVFC
},
113 { M32RX_XINSN_MVTACHI_A
, && case_read_READ_FMT_MVTACHI_A
},
114 { M32RX_XINSN_MVTACLO_A
, && case_read_READ_FMT_MVTACHI_A
},
115 { M32RX_XINSN_MVTC
, && case_read_READ_FMT_MVTC
},
116 { M32RX_XINSN_NEG
, && case_read_READ_FMT_MV
},
117 { M32RX_XINSN_NOP
, && case_read_READ_FMT_NOP
},
118 { M32RX_XINSN_NOT
, && case_read_READ_FMT_MV
},
119 { M32RX_XINSN_RAC_DSI
, && case_read_READ_FMT_RAC_DSI
},
120 { M32RX_XINSN_RACH_DSI
, && case_read_READ_FMT_RAC_DSI
},
121 { M32RX_XINSN_RTE
, && case_read_READ_FMT_RTE
},
122 { M32RX_XINSN_SETH
, && case_read_READ_FMT_SETH
},
123 { M32RX_XINSN_SLL
, && case_read_READ_FMT_ADD
},
124 { M32RX_XINSN_SLL3
, && case_read_READ_FMT_SLL3
},
125 { M32RX_XINSN_SLLI
, && case_read_READ_FMT_SLLI
},
126 { M32RX_XINSN_SRA
, && case_read_READ_FMT_ADD
},
127 { M32RX_XINSN_SRA3
, && case_read_READ_FMT_SLL3
},
128 { M32RX_XINSN_SRAI
, && case_read_READ_FMT_SLLI
},
129 { M32RX_XINSN_SRL
, && case_read_READ_FMT_ADD
},
130 { M32RX_XINSN_SRL3
, && case_read_READ_FMT_SLL3
},
131 { M32RX_XINSN_SRLI
, && case_read_READ_FMT_SLLI
},
132 { M32RX_XINSN_ST
, && case_read_READ_FMT_ST
},
133 { M32RX_XINSN_ST_D
, && case_read_READ_FMT_ST_D
},
134 { M32RX_XINSN_STB
, && case_read_READ_FMT_STB
},
135 { M32RX_XINSN_STB_D
, && case_read_READ_FMT_STB_D
},
136 { M32RX_XINSN_STH
, && case_read_READ_FMT_STH
},
137 { M32RX_XINSN_STH_D
, && case_read_READ_FMT_STH_D
},
138 { M32RX_XINSN_ST_PLUS
, && case_read_READ_FMT_ST_PLUS
},
139 { M32RX_XINSN_ST_MINUS
, && case_read_READ_FMT_ST_PLUS
},
140 { M32RX_XINSN_SUB
, && case_read_READ_FMT_ADD
},
141 { M32RX_XINSN_SUBV
, && case_read_READ_FMT_ADDV
},
142 { M32RX_XINSN_SUBX
, && case_read_READ_FMT_ADDX
},
143 { M32RX_XINSN_TRAP
, && case_read_READ_FMT_TRAP
},
144 { M32RX_XINSN_UNLOCK
, && case_read_READ_FMT_UNLOCK
},
145 { M32RX_XINSN_SATB
, && case_read_READ_FMT_SATB
},
146 { M32RX_XINSN_SATH
, && case_read_READ_FMT_SATB
},
147 { M32RX_XINSN_SAT
, && case_read_READ_FMT_SAT
},
148 { M32RX_XINSN_PCMPBZ
, && case_read_READ_FMT_CMPZ
},
149 { M32RX_XINSN_SADD
, && case_read_READ_FMT_SADD
},
150 { M32RX_XINSN_MACWU1
, && case_read_READ_FMT_MACWU1
},
151 { M32RX_XINSN_MSBLO
, && case_read_READ_FMT_MSBLO
},
152 { M32RX_XINSN_MULWU1
, && case_read_READ_FMT_MULWU1
},
153 { M32RX_XINSN_MACLH1
, && case_read_READ_FMT_MACWU1
},
154 { M32RX_XINSN_SC
, && case_read_READ_FMT_SC
},
155 { M32RX_XINSN_SNC
, && case_read_READ_FMT_SC
},
160 for (i
= 0; labels
[i
].label
!= 0; ++i
)
161 CPU_IDESC (current_cpu
) [labels
[i
].index
].read
= labels
[i
].label
;
163 #endif /* DEFINE_LABELS */
169 SWITCH (read
, decode
->read
)
172 CASE (read
, READ_ILLEGAL
) :
174 sim_engine_illegal_insn (current_cpu
, NULL_CIA
/*FIXME*/);
178 CASE (read
, READ_FMT_ADD
) : /* e.g. add $dr,$sr */
180 #define OPRND(f) par_exec->operands.fmt_add.f
181 EXTRACT_FMT_ADD_VARS
/* f-op1 f-r1 f-op2 f-r2 */
183 /* Fetch the input operands for the semantic handler. */
184 OPRND (dr
) = CPU (h_gr
[f_r1
]);
185 OPRND (sr
) = CPU (h_gr
[f_r2
]);
190 CASE (read
, READ_FMT_ADD3
) : /* e.g. add3 $dr,$sr,$hash$slo16 */
192 #define OPRND(f) par_exec->operands.fmt_add3.f
193 EXTRACT_FMT_ADD3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
194 EXTRACT_FMT_ADD3_CODE
195 /* Fetch the input operands for the semantic handler. */
196 OPRND (sr
) = CPU (h_gr
[f_r2
]);
197 OPRND (slo16
) = f_simm16
;
202 CASE (read
, READ_FMT_AND3
) : /* e.g. and3 $dr,$sr,$uimm16 */
204 #define OPRND(f) par_exec->operands.fmt_and3.f
205 EXTRACT_FMT_AND3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
206 EXTRACT_FMT_AND3_CODE
207 /* Fetch the input operands for the semantic handler. */
208 OPRND (sr
) = CPU (h_gr
[f_r2
]);
209 OPRND (uimm16
) = f_uimm16
;
214 CASE (read
, READ_FMT_OR3
) : /* e.g. or3 $dr,$sr,$hash$ulo16 */
216 #define OPRND(f) par_exec->operands.fmt_or3.f
217 EXTRACT_FMT_OR3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
219 /* Fetch the input operands for the semantic handler. */
220 OPRND (sr
) = CPU (h_gr
[f_r2
]);
221 OPRND (ulo16
) = f_uimm16
;
226 CASE (read
, READ_FMT_ADDI
) : /* e.g. addi $dr,$simm8 */
228 #define OPRND(f) par_exec->operands.fmt_addi.f
229 EXTRACT_FMT_ADDI_VARS
/* f-op1 f-r1 f-simm8 */
230 EXTRACT_FMT_ADDI_CODE
231 /* Fetch the input operands for the semantic handler. */
232 OPRND (dr
) = CPU (h_gr
[f_r1
]);
233 OPRND (simm8
) = f_simm8
;
238 CASE (read
, READ_FMT_ADDV
) : /* e.g. addv $dr,$sr */
240 #define OPRND(f) par_exec->operands.fmt_addv.f
241 EXTRACT_FMT_ADDV_VARS
/* f-op1 f-r1 f-op2 f-r2 */
242 EXTRACT_FMT_ADDV_CODE
243 /* Fetch the input operands for the semantic handler. */
244 OPRND (dr
) = CPU (h_gr
[f_r1
]);
245 OPRND (sr
) = CPU (h_gr
[f_r2
]);
250 CASE (read
, READ_FMT_ADDV3
) : /* e.g. addv3 $dr,$sr,$simm16 */
252 #define OPRND(f) par_exec->operands.fmt_addv3.f
253 EXTRACT_FMT_ADDV3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
254 EXTRACT_FMT_ADDV3_CODE
255 /* Fetch the input operands for the semantic handler. */
256 OPRND (sr
) = CPU (h_gr
[f_r2
]);
257 OPRND (simm16
) = f_simm16
;
262 CASE (read
, READ_FMT_ADDX
) : /* e.g. addx $dr,$sr */
264 #define OPRND(f) par_exec->operands.fmt_addx.f
265 EXTRACT_FMT_ADDX_VARS
/* f-op1 f-r1 f-op2 f-r2 */
266 EXTRACT_FMT_ADDX_CODE
267 /* Fetch the input operands for the semantic handler. */
268 OPRND (dr
) = CPU (h_gr
[f_r1
]);
269 OPRND (sr
) = CPU (h_gr
[f_r2
]);
270 OPRND (condbit
) = CPU (h_cond
);
275 CASE (read
, READ_FMT_BC8
) : /* e.g. bc.s $disp8 */
277 #define OPRND(f) par_exec->operands.fmt_bc8.f
278 EXTRACT_FMT_BC8_VARS
/* f-op1 f-r1 f-disp8 */
280 /* Fetch the input operands for the semantic handler. */
281 OPRND (condbit
) = CPU (h_cond
);
282 OPRND (disp8
) = f_disp8
;
287 CASE (read
, READ_FMT_BC24
) : /* e.g. bc.l $disp24 */
289 #define OPRND(f) par_exec->operands.fmt_bc24.f
290 EXTRACT_FMT_BC24_VARS
/* f-op1 f-r1 f-disp24 */
291 EXTRACT_FMT_BC24_CODE
292 /* Fetch the input operands for the semantic handler. */
293 OPRND (condbit
) = CPU (h_cond
);
294 OPRND (disp24
) = f_disp24
;
299 CASE (read
, READ_FMT_BEQ
) : /* e.g. beq $src1,$src2,$disp16 */
301 #define OPRND(f) par_exec->operands.fmt_beq.f
302 EXTRACT_FMT_BEQ_VARS
/* f-op1 f-r1 f-op2 f-r2 f-disp16 */
304 /* Fetch the input operands for the semantic handler. */
305 OPRND (src1
) = CPU (h_gr
[f_r1
]);
306 OPRND (src2
) = CPU (h_gr
[f_r2
]);
307 OPRND (disp16
) = f_disp16
;
312 CASE (read
, READ_FMT_BEQZ
) : /* e.g. beqz $src2,$disp16 */
314 #define OPRND(f) par_exec->operands.fmt_beqz.f
315 EXTRACT_FMT_BEQZ_VARS
/* f-op1 f-r1 f-op2 f-r2 f-disp16 */
316 EXTRACT_FMT_BEQZ_CODE
317 /* Fetch the input operands for the semantic handler. */
318 OPRND (src2
) = CPU (h_gr
[f_r2
]);
319 OPRND (disp16
) = f_disp16
;
324 CASE (read
, READ_FMT_BL8
) : /* e.g. bl.s $disp8 */
326 #define OPRND(f) par_exec->operands.fmt_bl8.f
327 EXTRACT_FMT_BL8_VARS
/* f-op1 f-r1 f-disp8 */
329 /* Fetch the input operands for the semantic handler. */
330 OPRND (pc
) = CPU (h_pc
);
331 OPRND (disp8
) = f_disp8
;
336 CASE (read
, READ_FMT_BL24
) : /* e.g. bl.l $disp24 */
338 #define OPRND(f) par_exec->operands.fmt_bl24.f
339 EXTRACT_FMT_BL24_VARS
/* f-op1 f-r1 f-disp24 */
340 EXTRACT_FMT_BL24_CODE
341 /* Fetch the input operands for the semantic handler. */
342 OPRND (pc
) = CPU (h_pc
);
343 OPRND (disp24
) = f_disp24
;
348 CASE (read
, READ_FMT_BCL8
) : /* e.g. bcl.s $disp8 */
350 #define OPRND(f) par_exec->operands.fmt_bcl8.f
351 EXTRACT_FMT_BCL8_VARS
/* f-op1 f-r1 f-disp8 */
352 EXTRACT_FMT_BCL8_CODE
353 /* Fetch the input operands for the semantic handler. */
354 OPRND (condbit
) = CPU (h_cond
);
355 OPRND (pc
) = CPU (h_pc
);
356 OPRND (disp8
) = f_disp8
;
361 CASE (read
, READ_FMT_BCL24
) : /* e.g. bcl.l $disp24 */
363 #define OPRND(f) par_exec->operands.fmt_bcl24.f
364 EXTRACT_FMT_BCL24_VARS
/* f-op1 f-r1 f-disp24 */
365 EXTRACT_FMT_BCL24_CODE
366 /* Fetch the input operands for the semantic handler. */
367 OPRND (condbit
) = CPU (h_cond
);
368 OPRND (pc
) = CPU (h_pc
);
369 OPRND (disp24
) = f_disp24
;
374 CASE (read
, READ_FMT_BRA8
) : /* e.g. bra.s $disp8 */
376 #define OPRND(f) par_exec->operands.fmt_bra8.f
377 EXTRACT_FMT_BRA8_VARS
/* f-op1 f-r1 f-disp8 */
378 EXTRACT_FMT_BRA8_CODE
379 /* Fetch the input operands for the semantic handler. */
380 OPRND (disp8
) = f_disp8
;
385 CASE (read
, READ_FMT_BRA24
) : /* e.g. bra.l $disp24 */
387 #define OPRND(f) par_exec->operands.fmt_bra24.f
388 EXTRACT_FMT_BRA24_VARS
/* f-op1 f-r1 f-disp24 */
389 EXTRACT_FMT_BRA24_CODE
390 /* Fetch the input operands for the semantic handler. */
391 OPRND (disp24
) = f_disp24
;
396 CASE (read
, READ_FMT_CMP
) : /* e.g. cmp $src1,$src2 */
398 #define OPRND(f) par_exec->operands.fmt_cmp.f
399 EXTRACT_FMT_CMP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
401 /* Fetch the input operands for the semantic handler. */
402 OPRND (src1
) = CPU (h_gr
[f_r1
]);
403 OPRND (src2
) = CPU (h_gr
[f_r2
]);
408 CASE (read
, READ_FMT_CMPI
) : /* e.g. cmpi $src2,$simm16 */
410 #define OPRND(f) par_exec->operands.fmt_cmpi.f
411 EXTRACT_FMT_CMPI_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
412 EXTRACT_FMT_CMPI_CODE
413 /* Fetch the input operands for the semantic handler. */
414 OPRND (src2
) = CPU (h_gr
[f_r2
]);
415 OPRND (simm16
) = f_simm16
;
420 CASE (read
, READ_FMT_CMPZ
) : /* e.g. cmpz $src2 */
422 #define OPRND(f) par_exec->operands.fmt_cmpz.f
423 EXTRACT_FMT_CMPZ_VARS
/* f-op1 f-r1 f-op2 f-r2 */
424 EXTRACT_FMT_CMPZ_CODE
425 /* Fetch the input operands for the semantic handler. */
426 OPRND (src2
) = CPU (h_gr
[f_r2
]);
431 CASE (read
, READ_FMT_DIV
) : /* e.g. div $dr,$sr */
433 #define OPRND(f) par_exec->operands.fmt_div.f
434 EXTRACT_FMT_DIV_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
436 /* Fetch the input operands for the semantic handler. */
437 OPRND (dr
) = CPU (h_gr
[f_r1
]);
438 OPRND (sr
) = CPU (h_gr
[f_r2
]);
443 CASE (read
, READ_FMT_JC
) : /* e.g. jc $sr */
445 #define OPRND(f) par_exec->operands.fmt_jc.f
446 EXTRACT_FMT_JC_VARS
/* f-op1 f-r1 f-op2 f-r2 */
448 /* Fetch the input operands for the semantic handler. */
449 OPRND (condbit
) = CPU (h_cond
);
450 OPRND (sr
) = CPU (h_gr
[f_r2
]);
455 CASE (read
, READ_FMT_JL
) : /* e.g. jl $sr */
457 #define OPRND(f) par_exec->operands.fmt_jl.f
458 EXTRACT_FMT_JL_VARS
/* f-op1 f-r1 f-op2 f-r2 */
460 /* Fetch the input operands for the semantic handler. */
461 OPRND (pc
) = CPU (h_pc
);
462 OPRND (sr
) = CPU (h_gr
[f_r2
]);
467 CASE (read
, READ_FMT_JMP
) : /* e.g. jmp $sr */
469 #define OPRND(f) par_exec->operands.fmt_jmp.f
470 EXTRACT_FMT_JMP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
472 /* Fetch the input operands for the semantic handler. */
473 OPRND (sr
) = CPU (h_gr
[f_r2
]);
478 CASE (read
, READ_FMT_LD
) : /* e.g. ld $dr,@$sr */
480 #define OPRND(f) par_exec->operands.fmt_ld.f
481 EXTRACT_FMT_LD_VARS
/* f-op1 f-r1 f-op2 f-r2 */
483 /* Fetch the input operands for the semantic handler. */
484 OPRND (h_memory_sr
) = GETMEMSI (current_cpu
, CPU (h_gr
[f_r2
]));
485 OPRND (sr
) = CPU (h_gr
[f_r2
]);
490 CASE (read
, READ_FMT_LD_D
) : /* e.g. ld $dr,@($slo16,$sr) */
492 #define OPRND(f) par_exec->operands.fmt_ld_d.f
493 EXTRACT_FMT_LD_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
494 EXTRACT_FMT_LD_D_CODE
495 /* Fetch the input operands for the semantic handler. */
496 OPRND (h_memory_add__VM_sr_slo16
) = GETMEMSI (current_cpu
, ADDSI (CPU (h_gr
[f_r2
]), f_simm16
));
497 OPRND (sr
) = CPU (h_gr
[f_r2
]);
498 OPRND (slo16
) = f_simm16
;
503 CASE (read
, READ_FMT_LDB
) : /* e.g. ldb $dr,@$sr */
505 #define OPRND(f) par_exec->operands.fmt_ldb.f
506 EXTRACT_FMT_LDB_VARS
/* f-op1 f-r1 f-op2 f-r2 */
508 /* Fetch the input operands for the semantic handler. */
509 OPRND (h_memory_sr
) = GETMEMQI (current_cpu
, CPU (h_gr
[f_r2
]));
510 OPRND (sr
) = CPU (h_gr
[f_r2
]);
515 CASE (read
, READ_FMT_LDB_D
) : /* e.g. ldb $dr,@($slo16,$sr) */
517 #define OPRND(f) par_exec->operands.fmt_ldb_d.f
518 EXTRACT_FMT_LDB_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
519 EXTRACT_FMT_LDB_D_CODE
520 /* Fetch the input operands for the semantic handler. */
521 OPRND (h_memory_add__VM_sr_slo16
) = GETMEMQI (current_cpu
, ADDSI (CPU (h_gr
[f_r2
]), f_simm16
));
522 OPRND (sr
) = CPU (h_gr
[f_r2
]);
523 OPRND (slo16
) = f_simm16
;
528 CASE (read
, READ_FMT_LDH
) : /* e.g. ldh $dr,@$sr */
530 #define OPRND(f) par_exec->operands.fmt_ldh.f
531 EXTRACT_FMT_LDH_VARS
/* f-op1 f-r1 f-op2 f-r2 */
533 /* Fetch the input operands for the semantic handler. */
534 OPRND (h_memory_sr
) = GETMEMHI (current_cpu
, CPU (h_gr
[f_r2
]));
535 OPRND (sr
) = CPU (h_gr
[f_r2
]);
540 CASE (read
, READ_FMT_LDH_D
) : /* e.g. ldh $dr,@($slo16,$sr) */
542 #define OPRND(f) par_exec->operands.fmt_ldh_d.f
543 EXTRACT_FMT_LDH_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
544 EXTRACT_FMT_LDH_D_CODE
545 /* Fetch the input operands for the semantic handler. */
546 OPRND (h_memory_add__VM_sr_slo16
) = GETMEMHI (current_cpu
, ADDSI (CPU (h_gr
[f_r2
]), f_simm16
));
547 OPRND (sr
) = CPU (h_gr
[f_r2
]);
548 OPRND (slo16
) = f_simm16
;
553 CASE (read
, READ_FMT_LD_PLUS
) : /* e.g. ld $dr,@$sr+ */
555 #define OPRND(f) par_exec->operands.fmt_ld_plus.f
556 EXTRACT_FMT_LD_PLUS_VARS
/* f-op1 f-r1 f-op2 f-r2 */
557 EXTRACT_FMT_LD_PLUS_CODE
558 /* Fetch the input operands for the semantic handler. */
559 OPRND (h_memory_sr
) = GETMEMSI (current_cpu
, CPU (h_gr
[f_r2
]));
560 OPRND (sr
) = CPU (h_gr
[f_r2
]);
565 CASE (read
, READ_FMT_LD24
) : /* e.g. ld24 $dr,$uimm24 */
567 #define OPRND(f) par_exec->operands.fmt_ld24.f
568 EXTRACT_FMT_LD24_VARS
/* f-op1 f-r1 f-uimm24 */
569 EXTRACT_FMT_LD24_CODE
570 /* Fetch the input operands for the semantic handler. */
571 OPRND (uimm24
) = f_uimm24
;
576 CASE (read
, READ_FMT_LDI8
) : /* e.g. ldi8 $dr,$simm8 */
578 #define OPRND(f) par_exec->operands.fmt_ldi8.f
579 EXTRACT_FMT_LDI8_VARS
/* f-op1 f-r1 f-simm8 */
580 EXTRACT_FMT_LDI8_CODE
581 /* Fetch the input operands for the semantic handler. */
582 OPRND (simm8
) = f_simm8
;
587 CASE (read
, READ_FMT_LDI16
) : /* e.g. ldi16 $dr,$hash$slo16 */
589 #define OPRND(f) par_exec->operands.fmt_ldi16.f
590 EXTRACT_FMT_LDI16_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
591 EXTRACT_FMT_LDI16_CODE
592 /* Fetch the input operands for the semantic handler. */
593 OPRND (slo16
) = f_simm16
;
598 CASE (read
, READ_FMT_LOCK
) : /* e.g. lock $dr,@$sr */
600 #define OPRND(f) par_exec->operands.fmt_lock.f
601 EXTRACT_FMT_LOCK_VARS
/* f-op1 f-r1 f-op2 f-r2 */
602 EXTRACT_FMT_LOCK_CODE
603 /* Fetch the input operands for the semantic handler. */
604 OPRND (h_memory_sr
) = GETMEMSI (current_cpu
, CPU (h_gr
[f_r2
]));
605 OPRND (sr
) = CPU (h_gr
[f_r2
]);
610 CASE (read
, READ_FMT_MACHI_A
) : /* e.g. machi $src1,$src2,$acc */
612 #define OPRND(f) par_exec->operands.fmt_machi_a.f
613 EXTRACT_FMT_MACHI_A_VARS
/* f-op1 f-r1 f-acc f-op23 f-r2 */
614 EXTRACT_FMT_MACHI_A_CODE
615 /* Fetch the input operands for the semantic handler. */
616 OPRND (acc
) = m32rx_h_accums_get (current_cpu
, f_acc
);
617 OPRND (src1
) = CPU (h_gr
[f_r1
]);
618 OPRND (src2
) = CPU (h_gr
[f_r2
]);
623 CASE (read
, READ_FMT_MULHI_A
) : /* e.g. mulhi $src1,$src2,$acc */
625 #define OPRND(f) par_exec->operands.fmt_mulhi_a.f
626 EXTRACT_FMT_MULHI_A_VARS
/* f-op1 f-r1 f-acc f-op23 f-r2 */
627 EXTRACT_FMT_MULHI_A_CODE
628 /* Fetch the input operands for the semantic handler. */
629 OPRND (src1
) = CPU (h_gr
[f_r1
]);
630 OPRND (src2
) = CPU (h_gr
[f_r2
]);
635 CASE (read
, READ_FMT_MV
) : /* e.g. mv $dr,$sr */
637 #define OPRND(f) par_exec->operands.fmt_mv.f
638 EXTRACT_FMT_MV_VARS
/* f-op1 f-r1 f-op2 f-r2 */
640 /* Fetch the input operands for the semantic handler. */
641 OPRND (sr
) = CPU (h_gr
[f_r2
]);
646 CASE (read
, READ_FMT_MVFACHI_A
) : /* e.g. mvfachi $dr,$accs */
648 #define OPRND(f) par_exec->operands.fmt_mvfachi_a.f
649 EXTRACT_FMT_MVFACHI_A_VARS
/* f-op1 f-r1 f-op2 f-accs f-op3 */
650 EXTRACT_FMT_MVFACHI_A_CODE
651 /* Fetch the input operands for the semantic handler. */
652 OPRND (accs
) = m32rx_h_accums_get (current_cpu
, f_accs
);
657 CASE (read
, READ_FMT_MVFC
) : /* e.g. mvfc $dr,$scr */
659 #define OPRND(f) par_exec->operands.fmt_mvfc.f
660 EXTRACT_FMT_MVFC_VARS
/* f-op1 f-r1 f-op2 f-r2 */
661 EXTRACT_FMT_MVFC_CODE
662 /* Fetch the input operands for the semantic handler. */
663 OPRND (scr
) = m32rx_h_cr_get (current_cpu
, f_r2
);
668 CASE (read
, READ_FMT_MVTACHI_A
) : /* e.g. mvtachi $src1,$accs */
670 #define OPRND(f) par_exec->operands.fmt_mvtachi_a.f
671 EXTRACT_FMT_MVTACHI_A_VARS
/* f-op1 f-r1 f-op2 f-accs f-op3 */
672 EXTRACT_FMT_MVTACHI_A_CODE
673 /* Fetch the input operands for the semantic handler. */
674 OPRND (accs
) = m32rx_h_accums_get (current_cpu
, f_accs
);
675 OPRND (src1
) = CPU (h_gr
[f_r1
]);
680 CASE (read
, READ_FMT_MVTC
) : /* e.g. mvtc $sr,$dcr */
682 #define OPRND(f) par_exec->operands.fmt_mvtc.f
683 EXTRACT_FMT_MVTC_VARS
/* f-op1 f-r1 f-op2 f-r2 */
684 EXTRACT_FMT_MVTC_CODE
685 /* Fetch the input operands for the semantic handler. */
686 OPRND (sr
) = CPU (h_gr
[f_r2
]);
691 CASE (read
, READ_FMT_NOP
) : /* e.g. nop */
693 #define OPRND(f) par_exec->operands.fmt_nop.f
694 EXTRACT_FMT_NOP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
696 /* Fetch the input operands for the semantic handler. */
701 CASE (read
, READ_FMT_RAC_DSI
) : /* e.g. rac $accd,$accs,$imm1 */
703 #define OPRND(f) par_exec->operands.fmt_rac_dsi.f
704 EXTRACT_FMT_RAC_DSI_VARS
/* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
705 EXTRACT_FMT_RAC_DSI_CODE
706 /* Fetch the input operands for the semantic handler. */
707 OPRND (accs
) = m32rx_h_accums_get (current_cpu
, f_accs
);
708 OPRND (imm1
) = f_imm1
;
713 CASE (read
, READ_FMT_RTE
) : /* e.g. rte */
715 #define OPRND(f) par_exec->operands.fmt_rte.f
716 EXTRACT_FMT_RTE_VARS
/* f-op1 f-r1 f-op2 f-r2 */
718 /* Fetch the input operands for the semantic handler. */
719 OPRND (h_bsm_0
) = CPU (h_bsm
);
720 OPRND (h_bie_0
) = CPU (h_bie
);
721 OPRND (h_bcond_0
) = CPU (h_bcond
);
722 OPRND (h_bpc_0
) = CPU (h_bpc
);
727 CASE (read
, READ_FMT_SETH
) : /* e.g. seth $dr,$hash$hi16 */
729 #define OPRND(f) par_exec->operands.fmt_seth.f
730 EXTRACT_FMT_SETH_VARS
/* f-op1 f-r1 f-op2 f-r2 f-hi16 */
731 EXTRACT_FMT_SETH_CODE
732 /* Fetch the input operands for the semantic handler. */
733 OPRND (hi16
) = f_hi16
;
738 CASE (read
, READ_FMT_SLL3
) : /* e.g. sll3 $dr,$sr,$simm16 */
740 #define OPRND(f) par_exec->operands.fmt_sll3.f
741 EXTRACT_FMT_SLL3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
742 EXTRACT_FMT_SLL3_CODE
743 /* Fetch the input operands for the semantic handler. */
744 OPRND (sr
) = CPU (h_gr
[f_r2
]);
745 OPRND (simm16
) = f_simm16
;
750 CASE (read
, READ_FMT_SLLI
) : /* e.g. slli $dr,$uimm5 */
752 #define OPRND(f) par_exec->operands.fmt_slli.f
753 EXTRACT_FMT_SLLI_VARS
/* f-op1 f-r1 f-shift-op2 f-uimm5 */
754 EXTRACT_FMT_SLLI_CODE
755 /* Fetch the input operands for the semantic handler. */
756 OPRND (dr
) = CPU (h_gr
[f_r1
]);
757 OPRND (uimm5
) = f_uimm5
;
762 CASE (read
, READ_FMT_ST
) : /* e.g. st $src1,@$src2 */
764 #define OPRND(f) par_exec->operands.fmt_st.f
765 EXTRACT_FMT_ST_VARS
/* f-op1 f-r1 f-op2 f-r2 */
767 /* Fetch the input operands for the semantic handler. */
768 OPRND (src2
) = CPU (h_gr
[f_r2
]);
769 OPRND (src1
) = CPU (h_gr
[f_r1
]);
774 CASE (read
, READ_FMT_ST_D
) : /* e.g. st $src1,@($slo16,$src2) */
776 #define OPRND(f) par_exec->operands.fmt_st_d.f
777 EXTRACT_FMT_ST_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
778 EXTRACT_FMT_ST_D_CODE
779 /* Fetch the input operands for the semantic handler. */
780 OPRND (src2
) = CPU (h_gr
[f_r2
]);
781 OPRND (slo16
) = f_simm16
;
782 OPRND (src1
) = CPU (h_gr
[f_r1
]);
787 CASE (read
, READ_FMT_STB
) : /* e.g. stb $src1,@$src2 */
789 #define OPRND(f) par_exec->operands.fmt_stb.f
790 EXTRACT_FMT_STB_VARS
/* f-op1 f-r1 f-op2 f-r2 */
792 /* Fetch the input operands for the semantic handler. */
793 OPRND (src2
) = CPU (h_gr
[f_r2
]);
794 OPRND (src1
) = CPU (h_gr
[f_r1
]);
799 CASE (read
, READ_FMT_STB_D
) : /* e.g. stb $src1,@($slo16,$src2) */
801 #define OPRND(f) par_exec->operands.fmt_stb_d.f
802 EXTRACT_FMT_STB_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
803 EXTRACT_FMT_STB_D_CODE
804 /* Fetch the input operands for the semantic handler. */
805 OPRND (src2
) = CPU (h_gr
[f_r2
]);
806 OPRND (slo16
) = f_simm16
;
807 OPRND (src1
) = CPU (h_gr
[f_r1
]);
812 CASE (read
, READ_FMT_STH
) : /* e.g. sth $src1,@$src2 */
814 #define OPRND(f) par_exec->operands.fmt_sth.f
815 EXTRACT_FMT_STH_VARS
/* f-op1 f-r1 f-op2 f-r2 */
817 /* Fetch the input operands for the semantic handler. */
818 OPRND (src2
) = CPU (h_gr
[f_r2
]);
819 OPRND (src1
) = CPU (h_gr
[f_r1
]);
824 CASE (read
, READ_FMT_STH_D
) : /* e.g. sth $src1,@($slo16,$src2) */
826 #define OPRND(f) par_exec->operands.fmt_sth_d.f
827 EXTRACT_FMT_STH_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
828 EXTRACT_FMT_STH_D_CODE
829 /* Fetch the input operands for the semantic handler. */
830 OPRND (src2
) = CPU (h_gr
[f_r2
]);
831 OPRND (slo16
) = f_simm16
;
832 OPRND (src1
) = CPU (h_gr
[f_r1
]);
837 CASE (read
, READ_FMT_ST_PLUS
) : /* e.g. st $src1,@+$src2 */
839 #define OPRND(f) par_exec->operands.fmt_st_plus.f
840 EXTRACT_FMT_ST_PLUS_VARS
/* f-op1 f-r1 f-op2 f-r2 */
841 EXTRACT_FMT_ST_PLUS_CODE
842 /* Fetch the input operands for the semantic handler. */
843 OPRND (src2
) = CPU (h_gr
[f_r2
]);
844 OPRND (src1
) = CPU (h_gr
[f_r1
]);
849 CASE (read
, READ_FMT_TRAP
) : /* e.g. trap $uimm4 */
851 #define OPRND(f) par_exec->operands.fmt_trap.f
852 EXTRACT_FMT_TRAP_VARS
/* f-op1 f-r1 f-op2 f-uimm4 */
853 EXTRACT_FMT_TRAP_CODE
854 /* Fetch the input operands for the semantic handler. */
855 OPRND (pc
) = CPU (h_pc
);
856 OPRND (h_cr_0
) = m32rx_h_cr_get (current_cpu
, ((HOSTUINT
) 0));
857 OPRND (uimm4
) = f_uimm4
;
862 CASE (read
, READ_FMT_UNLOCK
) : /* e.g. unlock $src1,@$src2 */
864 #define OPRND(f) par_exec->operands.fmt_unlock.f
865 EXTRACT_FMT_UNLOCK_VARS
/* f-op1 f-r1 f-op2 f-r2 */
866 EXTRACT_FMT_UNLOCK_CODE
867 /* Fetch the input operands for the semantic handler. */
868 OPRND (h_lock_0
) = CPU (h_lock
);
869 OPRND (src2
) = CPU (h_gr
[f_r2
]);
870 OPRND (src1
) = CPU (h_gr
[f_r1
]);
875 CASE (read
, READ_FMT_SATB
) : /* e.g. satb $dr,$sr */
877 #define OPRND(f) par_exec->operands.fmt_satb.f
878 EXTRACT_FMT_SATB_VARS
/* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
879 EXTRACT_FMT_SATB_CODE
880 /* Fetch the input operands for the semantic handler. */
881 OPRND (sr
) = CPU (h_gr
[f_r2
]);
886 CASE (read
, READ_FMT_SAT
) : /* e.g. sat $dr,$sr */
888 #define OPRND(f) par_exec->operands.fmt_sat.f
889 EXTRACT_FMT_SAT_VARS
/* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
891 /* Fetch the input operands for the semantic handler. */
892 OPRND (condbit
) = CPU (h_cond
);
893 OPRND (sr
) = CPU (h_gr
[f_r2
]);
898 CASE (read
, READ_FMT_SADD
) : /* e.g. sadd */
900 #define OPRND(f) par_exec->operands.fmt_sadd.f
901 EXTRACT_FMT_SADD_VARS
/* f-op1 f-r1 f-op2 f-r2 */
902 EXTRACT_FMT_SADD_CODE
903 /* Fetch the input operands for the semantic handler. */
904 OPRND (h_accums_1
) = m32rx_h_accums_get (current_cpu
, ((HOSTUINT
) 1));
905 OPRND (h_accums_0
) = m32rx_h_accums_get (current_cpu
, ((HOSTUINT
) 0));
910 CASE (read
, READ_FMT_MACWU1
) : /* e.g. macwu1 $src1,$src2 */
912 #define OPRND(f) par_exec->operands.fmt_macwu1.f
913 EXTRACT_FMT_MACWU1_VARS
/* f-op1 f-r1 f-op2 f-r2 */
914 EXTRACT_FMT_MACWU1_CODE
915 /* Fetch the input operands for the semantic handler. */
916 OPRND (h_accums_1
) = m32rx_h_accums_get (current_cpu
, ((HOSTUINT
) 1));
917 OPRND (src1
) = CPU (h_gr
[f_r1
]);
918 OPRND (src2
) = CPU (h_gr
[f_r2
]);
923 CASE (read
, READ_FMT_MSBLO
) : /* e.g. msblo $src1,$src2 */
925 #define OPRND(f) par_exec->operands.fmt_msblo.f
926 EXTRACT_FMT_MSBLO_VARS
/* f-op1 f-r1 f-op2 f-r2 */
927 EXTRACT_FMT_MSBLO_CODE
928 /* Fetch the input operands for the semantic handler. */
929 OPRND (accum
) = m32rx_h_accum_get (current_cpu
);
930 OPRND (src1
) = CPU (h_gr
[f_r1
]);
931 OPRND (src2
) = CPU (h_gr
[f_r2
]);
936 CASE (read
, READ_FMT_MULWU1
) : /* e.g. mulwu1 $src1,$src2 */
938 #define OPRND(f) par_exec->operands.fmt_mulwu1.f
939 EXTRACT_FMT_MULWU1_VARS
/* f-op1 f-r1 f-op2 f-r2 */
940 EXTRACT_FMT_MULWU1_CODE
941 /* Fetch the input operands for the semantic handler. */
942 OPRND (src1
) = CPU (h_gr
[f_r1
]);
943 OPRND (src2
) = CPU (h_gr
[f_r2
]);
948 CASE (read
, READ_FMT_SC
) : /* e.g. sc */
950 #define OPRND(f) par_exec->operands.fmt_sc.f
951 EXTRACT_FMT_SC_VARS
/* f-op1 f-r1 f-op2 f-r2 */
953 /* Fetch the input operands for the semantic handler. */
954 OPRND (condbit
) = CPU (h_cond
);
960 ENDSWITCH (read
) /* End of read switch. */
963 #endif /* DEFINE_SWITCH */