1 /* dv-m68hc11spi.c -- Simulation of the 68HC11 SPI
2 Copyright (C) 2000 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@worldnet.fr)
4 (From a driver model Contributed by Cygnus Solutions.)
6 This file is part of the program GDB, the GNU debugger.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 #include "dv-sockser.h"
28 #include "sim-assert.h"
33 m68hc11spi - m68hc11 SPI interface
38 Implements the m68hc11 Synchronous Serial Peripheral Interface
39 described in the m68hc11 user guide (Chapter 8 in pink book).
40 The SPI I/O controller is directly connected to the CPU
41 interrupt. The simulator implements:
45 - Write collision detection
57 Reset port. This port is only used to simulate a reset of the SPI
58 I/O controller. It should be connected to the RESET output of the cpu.
72 static const struct hw_port_descriptor m68hc11spi_ports
[] =
74 { "reset", RESET_PORT
, 0, input_port
, },
82 /* Information about next character to be transmited. */
83 unsigned char tx_char
;
87 unsigned char rx_char
;
88 unsigned char rx_clear_scsr
;
89 unsigned char clk_pin
;
91 /* SPI clock rate (twice the real clock). */
94 /* Periodic SPI event. */
95 struct hw_event
* spi_event
;
100 /* Finish off the partially created hw device. Attach our local
101 callbacks. Wire up our port names etc */
103 static hw_io_read_buffer_method m68hc11spi_io_read_buffer
;
104 static hw_io_write_buffer_method m68hc11spi_io_write_buffer
;
105 static hw_port_event_method m68hc11spi_port_event
;
106 static hw_ioctl_method m68hc11spi_ioctl
;
108 #define M6811_SPI_FIRST_REG (M6811_SPCR)
109 #define M6811_SPI_LAST_REG (M6811_SPDR)
113 attach_m68hc11spi_regs (struct hw
*me
,
114 struct m68hc11spi
*controller
)
116 hw_attach_address (hw_parent (me
), 0, io_map
,
118 M6811_SPI_LAST_REG
- M6811_SPI_FIRST_REG
+ 1,
123 m68hc11spi_finish (struct hw
*me
)
125 struct m68hc11spi
*controller
;
127 controller
= HW_ZALLOC (me
, struct m68hc11spi
);
128 me
->overlap_mode_hw
= 1;
129 set_hw_data (me
, controller
);
130 set_hw_io_read_buffer (me
, m68hc11spi_io_read_buffer
);
131 set_hw_io_write_buffer (me
, m68hc11spi_io_write_buffer
);
132 set_hw_ports (me
, m68hc11spi_ports
);
133 set_hw_port_event (me
, m68hc11spi_port_event
);
135 set_hw_ioctl (me
, m68hc11spi_ioctl
);
137 me
->to_ioctl
= m68hc11spi_ioctl
;
140 /* Attach ourself to our parent bus. */
141 attach_m68hc11spi_regs (me
, controller
);
143 /* Initialize to reset state. */
144 controller
->spi_event
= NULL
;
145 controller
->rx_clear_scsr
= 0;
150 /* An event arrives on an interrupt port */
153 m68hc11spi_port_event (struct hw
*me
,
160 struct m68hc11spi
*controller
;
164 controller
= hw_data (me
);
166 cpu
= STATE_CPU (sd
, 0);
171 HW_TRACE ((me
, "SPI reset"));
173 /* Reset the state of SPI registers. */
174 controller
->rx_clear_scsr
= 0;
175 if (controller
->spi_event
)
177 hw_event_queue_deschedule (me
, controller
->spi_event
);
178 controller
->spi_event
= 0;
182 m68hc11spi_io_write_buffer (me
, &val
, io_map
,
183 (unsigned_word
) M6811_SPCR
, 1);
188 hw_abort (me
, "Event on unknown port %d", my_port
);
194 set_bit_port (struct hw
*me
, sim_cpu
*cpu
, int port
, int mask
, int value
)
196 /* TODO: Post an event to inform other devices that pin 'port' changes.
197 This has only a sense if we provide some device that is logically
198 connected to these pin ports (SCLK and MOSI) and that handles
201 cpu
->ios
[port
] |= mask
;
203 cpu
->ios
[port
] &= ~mask
;
207 /* When a character is sent/received by the SPI, the PD2..PD5 line
208 are driven by the following signals:
211 -----+---------+--------+---/-+-------
213 MISO +---------+--------+---/-+
215 CLK _______/ \____/ \__ CPOL=0, CPHA=0
217 \____/ \___/ CPOL=1, CPHA=0
219 __/ \____/ \___/ CPOL=0, CPHA=1
221 \____/ \____/ \__ CPOL=1, CPHA=1
224 \__________________________//___/
233 #define SPI_START_BIT 0
234 #define SPI_MIDDLE_BIT 1
237 m68hc11spi_clock (struct hw
*me
, void *data
)
240 struct m68hc11spi
* controller
;
242 int check_interrupt
= 0;
244 controller
= hw_data (me
);
246 cpu
= STATE_CPU (sd
, 0);
248 /* Cleanup current event. */
249 if (controller
->spi_event
)
251 hw_event_queue_deschedule (me
, controller
->spi_event
);
252 controller
->spi_event
= 0;
255 /* Change a bit of data at each two SPI event. */
256 if (controller
->mode
== SPI_START_BIT
)
258 /* Reflect the bit value on bit 2 of port D. */
259 set_bit_port (me
, cpu
, M6811_PORTD
, (1 << 2),
260 (controller
->tx_char
& (1 << controller
->tx_bit
)));
261 controller
->tx_bit
--;
262 controller
->mode
= SPI_MIDDLE_BIT
;
266 controller
->mode
= SPI_START_BIT
;
269 /* Change the SPI clock at each event on bit 4 of port D. */
270 controller
->clk_pin
= ~controller
->clk_pin
;
271 set_bit_port (me
, cpu
, M6811_PORTD
, (1 << 4), controller
->clk_pin
);
273 /* Transmit is now complete for this byte. */
274 if (controller
->mode
== SPI_START_BIT
&& controller
->tx_bit
< 0)
276 controller
->rx_clear_scsr
= 0;
277 cpu
->ios
[M6811_SPSR
] |= M6811_SPIF
;
278 if (cpu
->ios
[M6811_SPCR
] & M6811_SPIE
)
283 controller
->spi_event
= hw_event_queue_schedule (me
, controller
->clock
,
289 interrupts_update_pending (&cpu
->cpu_interrupts
);
292 /* Flags of the SPCR register. */
293 io_reg_desc spcr_desc
[] = {
294 { M6811_SPIE
, "SPIE ", "Serial Peripheral Interrupt Enable" },
295 { M6811_SPE
, "SPE ", "Serial Peripheral System Enable" },
296 { M6811_DWOM
, "DWOM ", "Port D Wire-OR mode option" },
297 { M6811_MSTR
, "MSTR ", "Master Mode Select" },
298 { M6811_CPOL
, "CPOL ", "Clock Polarity" },
299 { M6811_CPHA
, "CPHA ", "Clock Phase" },
300 { M6811_SPR1
, "SPR1 ", "SPI Clock Rate Select" },
301 { M6811_SPR0
, "SPR0 ", "SPI Clock Rate Select" },
306 /* Flags of the SPSR register. */
307 io_reg_desc spsr_desc
[] = {
308 { M6811_SPIF
, "SPIF ", "SPI Transfer Complete flag" },
309 { M6811_WCOL
, "WCOL ", "Write Collision" },
310 { M6811_MODF
, "MODF ", "Mode Fault" },
315 m68hc11spi_info (struct hw
*me
)
320 struct m68hc11spi
*controller
;
324 cpu
= STATE_CPU (sd
, 0);
325 controller
= hw_data (me
);
327 sim_io_printf (sd
, "M68HC11 SPI:\n");
329 base
= cpu_get_io_base (cpu
);
331 val
= cpu
->ios
[M6811_SPCR
];
332 print_io_byte (sd
, "SPCR", spcr_desc
, val
, base
+ M6811_SPCR
);
333 sim_io_printf (sd
, "\n");
335 val
= cpu
->ios
[M6811_SPSR
];
336 print_io_byte (sd
, "SPSR", spsr_desc
, val
, base
+ M6811_SPSR
);
337 sim_io_printf (sd
, "\n");
339 if (controller
->spi_event
)
343 t
= hw_event_remain_time (me
, controller
->spi_event
);
344 sim_io_printf (sd
, " SPI operation finished in %ld cycles\n",
350 m68hc11spi_ioctl (struct hw
*me
,
351 hw_ioctl_request request
,
354 m68hc11spi_info (me
);
358 /* generic read/write */
361 m68hc11spi_io_read_buffer (struct hw
*me
,
368 struct m68hc11spi
*controller
;
372 HW_TRACE ((me
, "read 0x%08lx %d", (long) base
, (int) nr_bytes
));
375 cpu
= STATE_CPU (sd
, 0);
376 controller
= hw_data (me
);
381 controller
->rx_clear_scsr
= cpu
->ios
[M6811_SCSR
]
382 & (M6811_SPIF
| M6811_WCOL
| M6811_MODF
);
385 val
= cpu
->ios
[base
];
389 if (controller
->rx_clear_scsr
)
391 cpu
->ios
[M6811_SPSR
] &= ~controller
->rx_clear_scsr
;
392 controller
->rx_clear_scsr
= 0;
394 val
= controller
->rx_char
;
400 *((unsigned8
*) dest
) = val
;
405 m68hc11spi_io_write_buffer (struct hw
*me
,
412 struct m68hc11spi
*controller
;
416 HW_TRACE ((me
, "write 0x%08lx %d", (long) base
, (int) nr_bytes
));
419 cpu
= STATE_CPU (sd
, 0);
420 controller
= hw_data (me
);
422 val
= *((const unsigned8
*) source
);
426 cpu
->ios
[M6811_SPCR
] = val
;
428 /* The SPI clock rate is 2, 4, 16, 32 of the internal CPU clock.
429 We have to drive the clock pin and need a 2x faster clock. */
430 switch (val
& (M6811_SPR1
| M6811_SPR0
))
433 controller
->clock
= 1;
437 controller
->clock
= 2;
441 controller
->clock
= 8;
445 controller
->clock
= 16;
449 /* Set the clock pin. */
450 if ((val
& M6811_CPOL
)
451 && (controller
->spi_event
== 0
452 || ((val
& M6811_CPHA
) && controller
->mode
== 1)))
453 controller
->clk_pin
= 1;
455 controller
->clk_pin
= 0;
457 set_bit_port (me
, cpu
, M6811_PORTD
, (1 << 4), controller
->clk_pin
);
460 /* Can't write to SPSR. */
465 if (!(cpu
->ios
[M6811_SPCR
] & M6811_SPE
))
470 /* If transfer is taking place, a write to SPDR
471 generates a collision. */
472 if (controller
->spi_event
)
474 cpu
->ios
[M6811_SPSR
] |= M6811_WCOL
;
478 /* Refuse the write if there was no read of SPSR. */
481 /* Prepare to send a byte. */
482 controller
->tx_char
= val
;
483 controller
->tx_bit
= 7;
484 controller
->mode
= 0;
486 /* Toggle clock pin internal value when CPHA is 0 so that
487 it will really change in the middle of a bit. */
488 if (!(cpu
->ios
[M6811_SPCR
] & M6811_CPHA
))
489 controller
->clk_pin
= ~controller
->clk_pin
;
491 cpu
->ios
[M6811_SPDR
] = val
;
493 /* Activate transmission. */
494 m68hc11spi_clock (me
, NULL
);
504 const struct hw_descriptor dv_m68hc11spi_descriptor
[] = {
505 { "m68hc11spi", m68hc11spi_finish
, },