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1 /* interrupts.c -- 68HC11 Interrupts Emulation
2 Copyright 1999, 2000 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@worldnet.fr)
5 This file is part of GDB, GAS, and the GNU binutils.
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 1, or (at your option) any later version.
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23 struct interrupt_def idefs
[] = {
24 /* Serial interrupts. */
25 { M6811_INT_SCI
, M6811_SCSR
, M6811_TDRE
, M6811_SCCR2
, M6811_TIE
},
26 { M6811_INT_SCI
, M6811_SCSR
, M6811_TC
, M6811_SCCR2
, M6811_TCIE
},
27 { M6811_INT_SCI
, M6811_SCSR
, M6811_RDRF
, M6811_SCCR2
, M6811_RIE
},
28 { M6811_INT_SCI
, M6811_SCSR
, M6811_IDLE
, M6811_SCCR2
, M6811_ILIE
},
31 { M6811_INT_SPI
, M6811_SPSR
, M6811_SPIF
, M6811_SPCR
, M6811_SPIE
},
33 /* Realtime interrupts. */
34 { M6811_INT_TCTN
, M6811_TFLG2
, M6811_TOF
, M6811_TMSK2
, M6811_TOI
},
35 { M6811_INT_RT
, M6811_TFLG2
, M6811_RTIF
, M6811_TMSK2
, M6811_RTII
},
37 /* Output compare interrupts. */
38 { M6811_INT_OUTCMP1
, M6811_TFLG1
, M6811_OC1F
, M6811_TMSK1
, M6811_OC1I
},
39 { M6811_INT_OUTCMP2
, M6811_TFLG1
, M6811_OC2F
, M6811_TMSK1
, M6811_OC2I
},
40 { M6811_INT_OUTCMP3
, M6811_TFLG1
, M6811_OC3F
, M6811_TMSK1
, M6811_OC3I
},
41 { M6811_INT_OUTCMP4
, M6811_TFLG1
, M6811_OC4F
, M6811_TMSK1
, M6811_OC4I
},
42 { M6811_INT_OUTCMP5
, M6811_TFLG1
, M6811_OC5F
, M6811_TMSK1
, M6811_OC5I
},
44 /* Input compare interrupts. */
45 { M6811_INT_INCMP1
, M6811_TFLG1
, M6811_IC1F
, M6811_TMSK1
, M6811_IC1I
},
46 { M6811_INT_INCMP2
, M6811_TFLG1
, M6811_IC2F
, M6811_TMSK1
, M6811_IC2I
},
47 { M6811_INT_INCMP3
, M6811_TFLG1
, M6811_IC3F
, M6811_TMSK1
, M6811_IC3I
},
49 { M6811_INT_COPRESET
, M6811_CONFIG
, M6811_NOCOP
, 0, 0 },
50 { M6811_INT_COPFAIL
, M6811_CONFIG
, M6811_NOCOP
, 0, 0 }
54 #define TableSize(X) (sizeof X / sizeof(X[0]))
55 #define CYCLES_MAX ((((signed64) 1) << 62) - 1)
57 /* Initialize the interrupts of the processor. */
59 interrupts_initialize (struct _sim_cpu
*proc
)
61 struct interrupts
*interrupts
= &proc
->cpu_interrupts
;
64 interrupts
->cpu
= proc
;
65 interrupts
->pending_mask
= 0;
66 interrupts
->vectors_addr
= 0xffc0;
67 interrupts
->nb_interrupts_raised
= 0;
68 interrupts
->min_mask_cycles
= CYCLES_MAX
;
69 interrupts
->max_mask_cycles
= 0;
70 interrupts
->start_mask_cycle
= -1;
71 interrupts
->xirq_start_mask_cycle
= -1;
72 interrupts
->xirq_max_mask_cycles
= 0;
73 interrupts
->xirq_min_mask_cycles
= CYCLES_MAX
;
75 for (i
= 0; i
< M6811_INT_NUMBER
; i
++)
77 interrupts
->interrupt_order
[i
] = i
;
83 /* Update the mask of pending interrupts. This operation must be called
84 when the state of some 68HC11 IO registers changes. It looks the
85 different registers that indicate a pending interrupt (timer, SCI, SPI,
86 ...) and records the interrupt if it's there and enabled. */
88 interrupts_update_pending (struct interrupts
*interrupts
)
93 ioregs
= &interrupts
->cpu
->ios
[0];
95 for (i
= 0; i
< TableSize(idefs
); i
++)
97 struct interrupt_def
*idef
= &idefs
[i
];
100 /* Look if the interrupt is enabled. */
101 if (idef
->enable_paddr
)
103 data
= ioregs
[idef
->enable_paddr
];
104 if (!(data
& idef
->enabled_mask
))
107 interrupts
->pending_mask
&= ~(1 << idef
->int_number
);
112 /* Interrupt is enabled, see if it's there. */
113 data
= ioregs
[idef
->int_paddr
];
114 if (!(data
& idef
->int_mask
))
117 interrupts
->pending_mask
&= ~(1 << idef
->int_number
);
122 interrupts
->pending_mask
|= (1 << idef
->int_number
);
127 /* Finds the current active and non-masked interrupt.
128 Returns the interrupt number (index in the vector table) or -1
129 if no interrupt can be serviced. */
131 interrupts_get_current (struct interrupts
*interrupts
)
135 if (interrupts
->pending_mask
== 0)
138 /* SWI and illegal instructions are simulated by an interrupt.
139 They are not maskable. */
140 if (interrupts
->pending_mask
& (1 << M6811_INT_SWI
))
142 interrupts
->pending_mask
&= ~(1 << M6811_INT_SWI
);
143 return M6811_INT_SWI
;
145 if (interrupts
->pending_mask
& (1 << M6811_INT_ILLEGAL
))
147 interrupts
->pending_mask
&= ~(1 << M6811_INT_ILLEGAL
);
148 return M6811_INT_ILLEGAL
;
151 /* If there is a non maskable interrupt, go for it (unless we are masked
153 if (interrupts
->pending_mask
& (1 << M6811_INT_XIRQ
))
155 if (cpu_get_ccr_X (interrupts
->cpu
) == 0)
157 interrupts
->pending_mask
&= ~(1 << M6811_INT_XIRQ
);
158 return M6811_INT_XIRQ
;
163 /* Interrupts are masked, do nothing. */
164 if (cpu_get_ccr_I (interrupts
->cpu
) == 1)
169 /* Returns the first interrupt number which is pending.
170 The interrupt priority is specified by the table `interrupt_order'.
171 For these interrupts, the pending mask is cleared when the program
172 performs some actions on the corresponding device. If the device
173 is not reset, the interrupt remains and will be re-raised when
174 we return from the interrupt (see 68HC11 pink book). */
175 for (i
= 0; i
< M6811_INT_NUMBER
; i
++)
177 enum M6811_INT int_number
= interrupts
->interrupt_order
[i
];
179 if (interrupts
->pending_mask
& (1 << int_number
))
188 /* Process the current interrupt if there is one. This operation must
189 be called after each instruction to handle the interrupts. If interrupts
190 are masked, it does nothing. */
192 interrupts_process (struct interrupts
*interrupts
)
197 /* See if interrupts are enabled/disabled and keep track of the
198 number of cycles the interrupts are masked. Such information is
199 then reported by the info command. */
200 ccr
= cpu_get_ccr (interrupts
->cpu
);
201 if (ccr
& M6811_I_BIT
)
203 if (interrupts
->start_mask_cycle
< 0)
204 interrupts
->start_mask_cycle
= cpu_current_cycle (interrupts
->cpu
);
206 else if (interrupts
->start_mask_cycle
>= 0
207 && (ccr
& M6811_I_BIT
) == 0)
209 signed64 t
= cpu_current_cycle (interrupts
->cpu
);
211 t
-= interrupts
->start_mask_cycle
;
212 if (t
< interrupts
->min_mask_cycles
)
213 interrupts
->min_mask_cycles
= t
;
214 if (t
> interrupts
->max_mask_cycles
)
215 interrupts
->max_mask_cycles
= t
;
216 interrupts
->start_mask_cycle
= -1;
218 if (ccr
& M6811_X_BIT
)
220 if (interrupts
->xirq_start_mask_cycle
< 0)
221 interrupts
->xirq_start_mask_cycle
222 = cpu_current_cycle (interrupts
->cpu
);
224 else if (interrupts
->xirq_start_mask_cycle
>= 0
225 && (ccr
& M6811_X_BIT
) == 0)
227 signed64 t
= cpu_current_cycle (interrupts
->cpu
);
229 t
-= interrupts
->xirq_start_mask_cycle
;
230 if (t
< interrupts
->xirq_min_mask_cycles
)
231 interrupts
->xirq_min_mask_cycles
= t
;
232 if (t
> interrupts
->xirq_max_mask_cycles
)
233 interrupts
->xirq_max_mask_cycles
= t
;
234 interrupts
->xirq_start_mask_cycle
= -1;
237 id
= interrupts_get_current (interrupts
);
242 cpu_push_all (interrupts
->cpu
);
243 addr
= memory_read16 (interrupts
->cpu
,
244 interrupts
->vectors_addr
+ id
* 2);
245 cpu_call (interrupts
->cpu
, addr
);
247 /* Now, protect from nested interrupts. */
248 if (id
== M6811_INT_XIRQ
)
250 cpu_set_ccr_X (interrupts
->cpu
, 1);
254 cpu_set_ccr_I (interrupts
->cpu
, 1);
257 interrupts
->nb_interrupts_raised
++;
258 cpu_add_cycles (interrupts
->cpu
, 14);
265 interrupts_raise (struct interrupts
*interrupts
, enum M6811_INT number
)
267 interrupts
->pending_mask
|= (1 << number
);
268 interrupts
->nb_interrupts_raised
++;
274 interrupts_info (SIM_DESC sd
, struct interrupts
*interrupts
)
278 if (interrupts
->start_mask_cycle
>= 0)
280 t
= cpu_current_cycle (interrupts
->cpu
);
282 t
-= interrupts
->start_mask_cycle
;
283 if (t
> interrupts
->max_mask_cycles
)
284 interrupts
->max_mask_cycles
= t
;
286 if (interrupts
->xirq_start_mask_cycle
>= 0)
288 t
= cpu_current_cycle (interrupts
->cpu
);
290 t
-= interrupts
->xirq_start_mask_cycle
;
291 if (t
> interrupts
->xirq_max_mask_cycles
)
292 interrupts
->xirq_max_mask_cycles
= t
;
295 sim_io_printf (sd
, "Interrupts Info:\n");
296 sim_io_printf (sd
, " Interrupts raised: %lu\n",
297 interrupts
->nb_interrupts_raised
);
299 t
= interrupts
->min_mask_cycles
== CYCLES_MAX
?
300 interrupts
->max_mask_cycles
:
301 interrupts
->min_mask_cycles
;
302 sim_io_printf (sd
, " Shortest interrupts masked sequence: %s\n",
303 cycle_to_string (interrupts
->cpu
, t
));
305 t
= interrupts
->max_mask_cycles
;
306 sim_io_printf (sd
, " Longest interrupts masked sequence: %s\n",
307 cycle_to_string (interrupts
->cpu
, t
));
309 t
= interrupts
->xirq_min_mask_cycles
== CYCLES_MAX
?
310 interrupts
->xirq_max_mask_cycles
:
311 interrupts
->xirq_min_mask_cycles
;
312 sim_io_printf (sd
, " XIRQ Min interrupts masked sequence: %s\n",
313 cycle_to_string (interrupts
->cpu
, t
));
315 t
= interrupts
->xirq_max_mask_cycles
;
316 sim_io_printf (sd
, " XIRQ Max interrupts masked sequence: %s\n",
317 cycle_to_string (interrupts
->cpu
, t
));