1 2015-03-23 Mike Frysinger <vapier@gentoo.org>
3 * configure: Regenerate.
4 * configure.ac (mips_extra_objs): Delete.
5 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
6 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
8 2015-03-23 Mike Frysinger <vapier@gentoo.org>
10 * configure: Regenerate.
11 * configure.ac: Delete sim_hw checks for dv-sockser.
13 2015-03-16 Mike Frysinger <vapier@gentoo.org>
15 * config.in, configure: Regenerate.
16 * tconfig.in: Rename file ...
17 * tconfig.h: ... here.
19 2015-03-15 Mike Frysinger <vapier@gentoo.org>
21 * tconfig.in: Delete includes.
22 [HAVE_DV_SOCKSER]: Delete.
24 2015-03-14 Mike Frysinger <vapier@gentoo.org>
26 * Makefile.in (SIM_RUN_OBJS): Delete.
28 2015-03-14 Mike Frysinger <vapier@gentoo.org>
30 * configure.ac (AC_CHECK_HEADERS): Delete.
31 * aclocal.m4, configure: Regenerate.
33 2014-08-19 Alan Modra <amodra@gmail.com>
35 * configure: Regenerate.
37 2014-08-15 Roland McGrath <mcgrathr@google.com>
39 * configure: Regenerate.
40 * config.in: Regenerate.
42 2014-03-04 Mike Frysinger <vapier@gentoo.org>
44 * configure: Regenerate.
46 2013-09-23 Alan Modra <amodra@gmail.com>
48 * configure: Regenerate.
50 2013-06-03 Mike Frysinger <vapier@gentoo.org>
52 * aclocal.m4, configure: Regenerate.
54 2013-05-10 Freddie Chopin <freddie_chopin@op.pl>
58 2013-03-26 Mike Frysinger <vapier@gentoo.org>
60 * configure: Regenerate.
62 2013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
64 * configure.ac: Address use of dv-sockser.o.
65 * tconfig.in: Conditionalize use of dv_sockser_install.
66 * configure: Regenerated.
67 * config.in: Regenerated.
69 2012-10-04 Chao-ying Fu <fu@mips.com>
70 Steve Ellcey <sellcey@mips.com>
72 * mips/mips3264r2.igen (rdhwr): New.
74 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
76 * configure.ac: Always link against dv-sockser.o.
77 * configure: Regenerate.
79 2012-06-15 Joel Brobecker <brobecker@adacore.com>
81 * config.in, configure: Regenerate.
83 2012-05-18 Nick Clifton <nickc@redhat.com>
86 * interp.c: Include config.h before system header files.
88 2012-03-24 Mike Frysinger <vapier@gentoo.org>
90 * aclocal.m4, config.in, configure: Regenerate.
92 2011-12-03 Mike Frysinger <vapier@gentoo.org>
94 * aclocal.m4: New file.
95 * configure: Regenerate.
97 2011-10-19 Mike Frysinger <vapier@gentoo.org>
99 * configure: Regenerate after common/acinclude.m4 update.
101 2011-10-17 Mike Frysinger <vapier@gentoo.org>
103 * configure.ac: Change include to common/acinclude.m4.
105 2011-10-17 Mike Frysinger <vapier@gentoo.org>
107 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
108 call. Replace common.m4 include with SIM_AC_COMMON.
109 * configure: Regenerate.
111 2011-07-08 Hans-Peter Nilsson <hp@axis.com>
113 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
115 (tmp-mach-multi): Exit early when igen fails.
117 2011-07-05 Mike Frysinger <vapier@gentoo.org>
119 * interp.c (sim_do_command): Delete.
121 2011-02-14 Mike Frysinger <vapier@gentoo.org>
123 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
124 (tx3904sio_fifo_reset): Likewise.
125 * interp.c (sim_monitor): Likewise.
127 2010-04-14 Mike Frysinger <vapier@gentoo.org>
129 * interp.c (sim_write): Add const to buffer arg.
131 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
133 * interp.c: Don't include sysdep.h
135 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
137 * configure: Regenerate.
139 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
141 * config.in: Regenerate.
142 * configure: Likewise.
144 * configure: Regenerate.
146 2008-07-11 Hans-Peter Nilsson <hp@axis.com>
148 * configure: Regenerate to track ../common/common.m4 changes.
151 2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
152 Daniel Jacobowitz <dan@codesourcery.com>
153 Joseph Myers <joseph@codesourcery.com>
155 * configure: Regenerate.
157 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
159 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
160 that unconditionally allows fmt_ps.
161 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
162 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
163 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
164 filter from 64,f to 32,f.
165 (PREFX): Change filter from 64 to 32.
166 (LDXC1, LUXC1): Provide separate mips32r2 implementations
167 that use do_load_double instead of do_load. Make both LUXC1
168 versions unpredictable if SizeFGR () != 64.
169 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
170 instead of do_store. Remove unused variable. Make both SUXC1
171 versions unpredictable if SizeFGR () != 64.
173 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
175 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
176 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
177 shifts for that case.
179 2007-09-04 Nick Clifton <nickc@redhat.com>
181 * interp.c (options enum): Add OPTION_INFO_MEMORY.
182 (display_mem_info): New static variable.
183 (mips_option_handler): Handle OPTION_INFO_MEMORY.
184 (mips_options): Add info-memory and memory-info.
185 (sim_open): After processing the command line and board
186 specification, check display_mem_info. If it is set then
187 call the real handler for the --memory-info command line
190 2007-08-24 Joel Brobecker <brobecker@adacore.com>
192 * configure.ac: Change license of multi-run.c to GPL version 3.
193 * configure: Regenerate.
195 2007-06-28 Richard Sandiford <richard@codesourcery.com>
197 * configure.ac, configure: Revert last patch.
199 2007-06-26 Richard Sandiford <richard@codesourcery.com>
201 * configure.ac (sim_mipsisa3264_configs): New variable.
202 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
203 every configuration support all four targets, using the triplet to
204 determine the default.
205 * configure: Regenerate.
207 2007-06-25 Richard Sandiford <richard@codesourcery.com>
209 * Makefile.in (m16run.o): New rule.
211 2007-05-15 Thiemo Seufer <ths@mips.com>
213 * mips3264r2.igen (DSHD): Fix compile warning.
215 2007-05-14 Thiemo Seufer <ths@mips.com>
217 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
218 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
219 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
220 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
223 2007-03-01 Thiemo Seufer <ths@mips.com>
225 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
228 2007-02-20 Thiemo Seufer <ths@mips.com>
230 * dsp.igen: Update copyright notice.
231 * dsp2.igen: Fix copyright notice.
233 2007-02-20 Thiemo Seufer <ths@mips.com>
234 Chao-Ying Fu <fu@mips.com>
236 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
237 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
238 Add dsp2 to sim_igen_machine.
239 * configure: Regenerate.
240 * dsp.igen (do_ph_op): Add MUL support when op = 2.
241 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
242 (mulq_rs.ph): Use do_ph_mulq.
243 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
244 * mips.igen: Add dsp2 model and include dsp2.igen.
245 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
246 for *mips32r2, *mips64r2, *dsp.
247 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
248 for *mips32r2, *mips64r2, *dsp2.
249 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
251 2007-02-19 Thiemo Seufer <ths@mips.com>
252 Nigel Stephens <nigel@mips.com>
254 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
255 jumps with hazard barrier.
257 2007-02-19 Thiemo Seufer <ths@mips.com>
258 Nigel Stephens <nigel@mips.com>
260 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
261 after each call to sim_io_write.
263 2007-02-19 Thiemo Seufer <ths@mips.com>
264 Nigel Stephens <nigel@mips.com>
266 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
267 supported by this simulator.
268 (decode_coproc): Recognise additional CP0 Config registers
271 2007-02-19 Thiemo Seufer <ths@mips.com>
272 Nigel Stephens <nigel@mips.com>
273 David Ung <davidu@mips.com>
275 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
276 uninterpreted formats. If fmt is one of the uninterpreted types
277 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
278 fmt_word, and fmt_uninterpreted_64 like fmt_long.
279 (store_fpr): When writing an invalid odd register, set the
280 matching even register to fmt_unknown, not the following register.
281 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
282 the the memory window at offset 0 set by --memory-size command
284 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
286 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
288 (sim_monitor): When returning the memory size to the MIPS
289 application, use the value in STATE_MEM_SIZE, not an arbitrary
291 (cop_lw): Don' mess around with FPR_STATE, just pass
292 fmt_uninterpreted_32 to StoreFPR.
294 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
296 * mips.igen (not_word_value): Single version for mips32, mips64
299 2007-02-19 Thiemo Seufer <ths@mips.com>
300 Nigel Stephens <nigel@mips.com>
302 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
305 2007-02-17 Thiemo Seufer <ths@mips.com>
307 * configure.ac (mips*-sde-elf*): Move in front of generic machine
309 * configure: Regenerate.
311 2007-02-17 Thiemo Seufer <ths@mips.com>
313 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
314 Add mdmx to sim_igen_machine.
315 (mipsisa64*-*-*): Likewise. Remove dsp.
316 (mipsisa32*-*-*): Remove dsp.
317 * configure: Regenerate.
319 2007-02-13 Thiemo Seufer <ths@mips.com>
321 * configure.ac: Add mips*-sde-elf* target.
322 * configure: Regenerate.
324 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
326 * acconfig.h: Remove.
327 * config.in, configure: Regenerate.
329 2006-11-07 Thiemo Seufer <ths@mips.com>
331 * dsp.igen (do_w_op): Fix compiler warning.
333 2006-08-29 Thiemo Seufer <ths@mips.com>
334 David Ung <davidu@mips.com>
336 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
338 * configure: Regenerate.
339 * mips.igen (model): Add smartmips.
340 (MADDU): Increment ACX if carry.
341 (do_mult): Clear ACX.
342 (ROR,RORV): Add smartmips.
343 (include): Include smartmips.igen.
344 * sim-main.h (ACX): Set to REGISTERS[89].
345 * smartmips.igen: New file.
347 2006-08-29 Thiemo Seufer <ths@mips.com>
348 David Ung <davidu@mips.com>
350 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
351 mips3264r2.igen. Add missing dependency rules.
352 * m16e.igen: Support for mips16e save/restore instructions.
354 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
356 * configure: Regenerated.
358 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
360 * configure: Regenerated.
362 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
364 * configure: Regenerated.
366 2006-05-15 Chao-ying Fu <fu@mips.com>
368 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
370 2006-04-18 Nick Clifton <nickc@redhat.com>
372 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
375 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
377 * configure: Regenerate.
379 2005-12-14 Chao-ying Fu <fu@mips.com>
381 * Makefile.in (SIM_OBJS): Add dsp.o.
382 (dsp.o): New dependency.
383 (IGEN_INCLUDE): Add dsp.igen.
384 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
385 mipsisa64*-*-*): Add dsp to sim_igen_machine.
386 * configure: Regenerate.
387 * mips.igen: Add dsp model and include dsp.igen.
388 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
389 because these instructions are extended in DSP ASE.
390 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
391 adding 6 DSP accumulator registers and 1 DSP control register.
392 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
393 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
394 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
395 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
396 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
397 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
398 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
399 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
400 DSPCR_CCOND_SMASK): New define.
401 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
402 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
404 2005-07-08 Ian Lance Taylor <ian@airs.com>
406 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
408 2005-06-16 David Ung <davidu@mips.com>
409 Nigel Stephens <nigel@mips.com>
411 * mips.igen: New mips16e model and include m16e.igen.
412 (check_u64): Add mips16e tag.
413 * m16e.igen: New file for MIPS16e instructions.
414 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
415 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
417 * configure: Regenerate.
419 2005-05-26 David Ung <davidu@mips.com>
421 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
422 tags to all instructions which are applicable to the new ISAs.
423 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
425 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
427 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
429 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
430 * configure: Regenerate.
432 2005-03-23 Mark Kettenis <kettenis@gnu.org>
434 * configure: Regenerate.
436 2005-01-14 Andrew Cagney <cagney@gnu.org>
438 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
439 explicit call to AC_CONFIG_HEADER.
440 * configure: Regenerate.
442 2005-01-12 Andrew Cagney <cagney@gnu.org>
444 * configure.ac: Update to use ../common/common.m4.
445 * configure: Re-generate.
447 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
449 * configure: Regenerated to track ../common/aclocal.m4 changes.
451 2005-01-07 Andrew Cagney <cagney@gnu.org>
453 * configure.ac: Rename configure.in, require autoconf 2.59.
454 * configure: Re-generate.
456 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
458 * configure: Regenerate for ../common/aclocal.m4 update.
460 2004-09-24 Monika Chaddha <monika@acmet.com>
462 Committed by Andrew Cagney.
463 * m16.igen (CMP, CMPI): Fix assembler.
465 2004-08-18 Chris Demetriou <cgd@broadcom.com>
467 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
468 * configure: Regenerate.
470 2004-06-25 Chris Demetriou <cgd@broadcom.com>
472 * configure.in (sim_m16_machine): Include mipsIII.
473 * configure: Regenerate.
475 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
477 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
479 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
481 2004-04-10 Chris Demetriou <cgd@broadcom.com>
483 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
485 2004-04-09 Chris Demetriou <cgd@broadcom.com>
487 * mips.igen (check_fmt): Remove.
488 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
489 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
490 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
491 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
492 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
493 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
494 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
495 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
496 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
497 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
499 2004-04-09 Chris Demetriou <cgd@broadcom.com>
501 * sb1.igen (check_sbx): New function.
502 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
504 2004-03-29 Chris Demetriou <cgd@broadcom.com>
505 Richard Sandiford <rsandifo@redhat.com>
507 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
508 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
509 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
510 separate implementations for mipsIV and mipsV. Use new macros to
511 determine whether the restrictions apply.
513 2004-01-19 Chris Demetriou <cgd@broadcom.com>
515 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
516 (check_mult_hilo): Improve comments.
517 (check_div_hilo): Likewise. Also, fork off a new version
518 to handle mips32/mips64 (since there are no hazards to check
521 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
523 * mips.igen (do_dmultx): Fix check for negative operands.
525 2003-05-16 Ian Lance Taylor <ian@airs.com>
527 * Makefile.in (SHELL): Make sure this is defined.
528 (various): Use $(SHELL) whenever we invoke move-if-change.
530 2003-05-03 Chris Demetriou <cgd@broadcom.com>
532 * cp1.c: Tweak attribution slightly.
535 * mdmx.igen: Likewise.
536 * mips3d.igen: Likewise.
537 * sb1.igen: Likewise.
539 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
541 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
544 2003-02-27 Andrew Cagney <cagney@redhat.com>
546 * interp.c (sim_open): Rename _bfd to bfd.
547 (sim_create_inferior): Ditto.
549 2003-01-14 Chris Demetriou <cgd@broadcom.com>
551 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
553 2003-01-14 Chris Demetriou <cgd@broadcom.com>
555 * mips.igen (EI, DI): Remove.
557 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
559 * Makefile.in (tmp-run-multi): Fix mips16 filter.
561 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
562 Andrew Cagney <ac131313@redhat.com>
563 Gavin Romig-Koch <gavin@redhat.com>
564 Graydon Hoare <graydon@redhat.com>
565 Aldy Hernandez <aldyh@redhat.com>
566 Dave Brolley <brolley@redhat.com>
567 Chris Demetriou <cgd@broadcom.com>
569 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
570 (sim_mach_default): New variable.
571 (mips64vr-*-*, mips64vrel-*-*): New configurations.
572 Add a new simulator generator, MULTI.
573 * configure: Regenerate.
574 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
575 (multi-run.o): New dependency.
576 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
577 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
578 (tmp-multi): Combine them.
579 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
580 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
581 (distclean-extra): New rule.
582 * sim-main.h: Include bfd.h.
583 (MIPS_MACH): New macro.
584 * mips.igen (vr4120, vr5400, vr5500): New models.
585 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
586 * vr.igen: Replace with new version.
588 2003-01-04 Chris Demetriou <cgd@broadcom.com>
590 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
591 * configure: Regenerate.
593 2002-12-31 Chris Demetriou <cgd@broadcom.com>
595 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
596 * mips.igen: Remove all invocations of check_branch_bug and
599 2002-12-16 Chris Demetriou <cgd@broadcom.com>
601 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
603 2002-07-30 Chris Demetriou <cgd@broadcom.com>
605 * mips.igen (do_load_double, do_store_double): New functions.
606 (LDC1, SDC1): Rename to...
607 (LDC1b, SDC1b): respectively.
608 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
610 2002-07-29 Michael Snyder <msnyder@redhat.com>
612 * cp1.c (fp_recip2): Modify initialization expression so that
613 GCC will recognize it as constant.
615 2002-06-18 Chris Demetriou <cgd@broadcom.com>
617 * mdmx.c (SD_): Delete.
618 (Unpredictable): Re-define, for now, to directly invoke
619 unpredictable_action().
620 (mdmx_acc_op): Fix error in .ob immediate handling.
622 2002-06-18 Andrew Cagney <cagney@redhat.com>
624 * interp.c (sim_firmware_command): Initialize `address'.
626 2002-06-16 Andrew Cagney <ac131313@redhat.com>
628 * configure: Regenerated to track ../common/aclocal.m4 changes.
630 2002-06-14 Chris Demetriou <cgd@broadcom.com>
631 Ed Satterthwaite <ehs@broadcom.com>
633 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
634 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
635 * mips.igen: Include mips3d.igen.
636 (mips3d): New model name for MIPS-3D ASE instructions.
637 (CVT.W.fmt): Don't use this instruction for word (source) format
639 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
640 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
641 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
642 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
643 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
644 (RSquareRoot1, RSquareRoot2): New macros.
645 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
646 (fp_rsqrt2): New functions.
647 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
648 * configure: Regenerate.
650 2002-06-13 Chris Demetriou <cgd@broadcom.com>
651 Ed Satterthwaite <ehs@broadcom.com>
653 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
654 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
655 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
656 (convert): Note that this function is not used for paired-single
658 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
659 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
660 (check_fmt_p): Enable paired-single support.
661 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
662 (PUU.PS): New instructions.
663 (CVT.S.fmt): Don't use this instruction for paired-single format
665 * sim-main.h (FP_formats): New value 'fmt_ps.'
666 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
667 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
669 2002-06-12 Chris Demetriou <cgd@broadcom.com>
671 * mips.igen: Fix formatting of function calls in
674 2002-06-12 Chris Demetriou <cgd@broadcom.com>
676 * mips.igen (MOVN, MOVZ): Trace result.
677 (TNEI): Print "tnei" as the opcode name in traces.
678 (CEIL.W): Add disassembly string for traces.
679 (RSQRT.fmt): Make location of disassembly string consistent
680 with other instructions.
682 2002-06-12 Chris Demetriou <cgd@broadcom.com>
684 * mips.igen (X): Delete unused function.
686 2002-06-08 Andrew Cagney <cagney@redhat.com>
688 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
690 2002-06-07 Chris Demetriou <cgd@broadcom.com>
691 Ed Satterthwaite <ehs@broadcom.com>
693 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
694 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
695 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
696 (fp_nmsub): New prototypes.
697 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
698 (NegMultiplySub): New defines.
699 * mips.igen (RSQRT.fmt): Use RSquareRoot().
700 (MADD.D, MADD.S): Replace with...
701 (MADD.fmt): New instruction.
702 (MSUB.D, MSUB.S): Replace with...
703 (MSUB.fmt): New instruction.
704 (NMADD.D, NMADD.S): Replace with...
705 (NMADD.fmt): New instruction.
706 (NMSUB.D, MSUB.S): Replace with...
707 (NMSUB.fmt): New instruction.
709 2002-06-07 Chris Demetriou <cgd@broadcom.com>
710 Ed Satterthwaite <ehs@broadcom.com>
712 * cp1.c: Fix more comment spelling and formatting.
713 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
714 (denorm_mode): New function.
715 (fpu_unary, fpu_binary): Round results after operation, collect
716 status from rounding operations, and update the FCSR.
717 (convert): Collect status from integer conversions and rounding
718 operations, and update the FCSR. Adjust NaN values that result
719 from conversions. Convert to use sim_io_eprintf rather than
720 fprintf, and remove some debugging code.
721 * cp1.h (fenr_FS): New define.
723 2002-06-07 Chris Demetriou <cgd@broadcom.com>
725 * cp1.c (convert): Remove unusable debugging code, and move MIPS
726 rounding mode to sim FP rounding mode flag conversion code into...
727 (rounding_mode): New function.
729 2002-06-07 Chris Demetriou <cgd@broadcom.com>
731 * cp1.c: Clean up formatting of a few comments.
732 (value_fpr): Reformat switch statement.
734 2002-06-06 Chris Demetriou <cgd@broadcom.com>
735 Ed Satterthwaite <ehs@broadcom.com>
738 * sim-main.h: Include cp1.h.
739 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
740 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
741 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
742 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
743 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
744 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
745 * cp1.c: Don't include sim-fpu.h; already included by
746 sim-main.h. Clean up formatting of some comments.
747 (NaN, Equal, Less): Remove.
748 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
749 (fp_cmp): New functions.
750 * mips.igen (do_c_cond_fmt): Remove.
751 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
752 Compare. Add result tracing.
753 (CxC1): Remove, replace with...
754 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
755 (DMxC1): Remove, replace with...
756 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
757 (MxC1): Remove, replace with...
758 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
760 2002-06-04 Chris Demetriou <cgd@broadcom.com>
762 * sim-main.h (FGRIDX): Remove, replace all uses with...
763 (FGR_BASE): New macro.
764 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
765 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
766 (NR_FGR, FGR): Likewise.
767 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
768 * mips.igen: Likewise.
770 2002-06-04 Chris Demetriou <cgd@broadcom.com>
772 * cp1.c: Add an FSF Copyright notice to this file.
774 2002-06-04 Chris Demetriou <cgd@broadcom.com>
775 Ed Satterthwaite <ehs@broadcom.com>
777 * cp1.c (Infinity): Remove.
778 * sim-main.h (Infinity): Likewise.
780 * cp1.c (fp_unary, fp_binary): New functions.
781 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
782 (fp_sqrt): New functions, implemented in terms of the above.
783 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
784 (Recip, SquareRoot): Remove (replaced by functions above).
785 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
786 (fp_recip, fp_sqrt): New prototypes.
787 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
788 (Recip, SquareRoot): Replace prototypes with #defines which
789 invoke the functions above.
791 2002-06-03 Chris Demetriou <cgd@broadcom.com>
793 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
794 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
795 file, remove PARAMS from prototypes.
796 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
797 simulator state arguments.
798 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
799 pass simulator state arguments.
800 * cp1.c (SD): Redefine as CPU_STATE(cpu).
801 (store_fpr, convert): Remove 'sd' argument.
802 (value_fpr): Likewise. Convert to use 'SD' instead.
804 2002-06-03 Chris Demetriou <cgd@broadcom.com>
806 * cp1.c (Min, Max): Remove #if 0'd functions.
807 * sim-main.h (Min, Max): Remove.
809 2002-06-03 Chris Demetriou <cgd@broadcom.com>
811 * cp1.c: fix formatting of switch case and default labels.
812 * interp.c: Likewise.
813 * sim-main.c: Likewise.
815 2002-06-03 Chris Demetriou <cgd@broadcom.com>
817 * cp1.c: Clean up comments which describe FP formats.
818 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
820 2002-06-03 Chris Demetriou <cgd@broadcom.com>
821 Ed Satterthwaite <ehs@broadcom.com>
823 * configure.in (mipsisa64sb1*-*-*): New target for supporting
824 Broadcom SiByte SB-1 processor configurations.
825 * configure: Regenerate.
826 * sb1.igen: New file.
827 * mips.igen: Include sb1.igen.
829 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
830 * mdmx.igen: Add "sb1" model to all appropriate functions and
832 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
833 (ob_func, ob_acc): Reference the above.
834 (qh_acc): Adjust to keep the same size as ob_acc.
835 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
836 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
838 2002-06-03 Chris Demetriou <cgd@broadcom.com>
840 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
842 2002-06-02 Chris Demetriou <cgd@broadcom.com>
843 Ed Satterthwaite <ehs@broadcom.com>
845 * mips.igen (mdmx): New (pseudo-)model.
846 * mdmx.c, mdmx.igen: New files.
847 * Makefile.in (SIM_OBJS): Add mdmx.o.
848 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
850 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
851 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
852 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
853 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
854 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
855 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
856 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
857 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
858 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
859 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
860 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
861 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
862 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
863 (qh_fmtsel): New macros.
864 (_sim_cpu): New member "acc".
865 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
866 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
868 2002-05-01 Chris Demetriou <cgd@broadcom.com>
870 * interp.c: Use 'deprecated' rather than 'depreciated.'
871 * sim-main.h: Likewise.
873 2002-05-01 Chris Demetriou <cgd@broadcom.com>
875 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
876 which wouldn't compile anyway.
877 * sim-main.h (unpredictable_action): New function prototype.
878 (Unpredictable): Define to call igen function unpredictable().
879 (NotWordValue): New macro to call igen function not_word_value().
880 (UndefinedResult): Remove.
881 * interp.c (undefined_result): Remove.
882 (unpredictable_action): New function.
883 * mips.igen (not_word_value, unpredictable): New functions.
884 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
885 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
886 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
887 NotWordValue() to check for unpredictable inputs, then
888 Unpredictable() to handle them.
890 2002-02-24 Chris Demetriou <cgd@broadcom.com>
892 * mips.igen: Fix formatting of calls to Unpredictable().
894 2002-04-20 Andrew Cagney <ac131313@redhat.com>
896 * interp.c (sim_open): Revert previous change.
898 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
900 * interp.c (sim_open): Disable chunk of code that wrote code in
901 vector table entries.
903 2002-03-19 Chris Demetriou <cgd@broadcom.com>
905 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
906 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
909 2002-03-19 Chris Demetriou <cgd@broadcom.com>
911 * cp1.c: Fix many formatting issues.
913 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
915 * cp1.c (fpu_format_name): New function to replace...
916 (DOFMT): This. Delete, and update all callers.
917 (fpu_rounding_mode_name): New function to replace...
918 (RMMODE): This. Delete, and update all callers.
920 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
922 * interp.c: Move FPU support routines from here to...
923 * cp1.c: Here. New file.
924 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
927 2002-03-12 Chris Demetriou <cgd@broadcom.com>
929 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
930 * mips.igen (mips32, mips64): New models, add to all instructions
931 and functions as appropriate.
932 (loadstore_ea, check_u64): New variant for model mips64.
933 (check_fmt_p): New variant for models mipsV and mips64, remove
934 mipsV model marking fro other variant.
937 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
938 for mips32 and mips64.
939 (DCLO, DCLZ): New instructions for mips64.
941 2002-03-07 Chris Demetriou <cgd@broadcom.com>
943 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
944 immediate or code as a hex value with the "%#lx" format.
945 (ANDI): Likewise, and fix printed instruction name.
947 2002-03-05 Chris Demetriou <cgd@broadcom.com>
949 * sim-main.h (UndefinedResult, Unpredictable): New macros
950 which currently do nothing.
952 2002-03-05 Chris Demetriou <cgd@broadcom.com>
954 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
955 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
956 (status_CU3): New definitions.
958 * sim-main.h (ExceptionCause): Add new values for MIPS32
959 and MIPS64: MDMX, MCheck, CacheErr. Update comments
960 for DebugBreakPoint and NMIReset to note their status in
962 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
963 (SignalExceptionCacheErr): New exception macros.
965 2002-03-05 Chris Demetriou <cgd@broadcom.com>
967 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
968 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
970 (SignalExceptionCoProcessorUnusable): Take as argument the
971 unusable coprocessor number.
973 2002-03-05 Chris Demetriou <cgd@broadcom.com>
975 * mips.igen: Fix formatting of all SignalException calls.
977 2002-03-05 Chris Demetriou <cgd@broadcom.com>
979 * sim-main.h (SIGNEXTEND): Remove.
981 2002-03-04 Chris Demetriou <cgd@broadcom.com>
983 * mips.igen: Remove gencode comment from top of file, fix
984 spelling in another comment.
986 2002-03-04 Chris Demetriou <cgd@broadcom.com>
988 * mips.igen (check_fmt, check_fmt_p): New functions to check
989 whether specific floating point formats are usable.
990 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
991 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
992 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
993 Use the new functions.
994 (do_c_cond_fmt): Remove format checks...
995 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
997 2002-03-03 Chris Demetriou <cgd@broadcom.com>
999 * mips.igen: Fix formatting of check_fpu calls.
1001 2002-03-03 Chris Demetriou <cgd@broadcom.com>
1003 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1005 2002-03-03 Chris Demetriou <cgd@broadcom.com>
1007 * mips.igen: Remove whitespace at end of lines.
1009 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1011 * mips.igen (loadstore_ea): New function to do effective
1012 address calculations.
1013 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1014 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1015 CACHE): Use loadstore_ea to do effective address computations.
1017 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1019 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1020 * mips.igen (LL, CxC1, MxC1): Likewise.
1022 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1024 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1025 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1026 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1027 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1028 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1029 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1030 Don't split opcode fields by hand, use the opcode field values
1033 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1035 * mips.igen (do_divu): Fix spacing.
1037 * mips.igen (do_dsllv): Move to be right before DSLLV,
1038 to match the rest of the do_<shift> functions.
1040 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1042 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1043 DSRL32, do_dsrlv): Trace inputs and results.
1045 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1047 * mips.igen (CACHE): Provide instruction-printing string.
1049 * interp.c (signal_exception): Comment tokens after #endif.
1051 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1053 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
1054 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1055 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1056 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1057 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1058 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1059 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
1060 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1062 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1064 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1065 instruction-printing string.
1066 (LWU): Use '64' as the filter flag.
1068 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1070 * mips.igen (SDXC1): Fix instruction-printing string.
1072 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1074 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1075 filter flags "32,f".
1077 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1079 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1082 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1084 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1085 add a comma) so that it more closely match the MIPS ISA
1086 documentation opcode partitioning.
1087 (PREF): Put useful names on opcode fields, and include
1088 instruction-printing string.
1090 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1092 * mips.igen (check_u64): New function which in the future will
1093 check whether 64-bit instructions are usable and signal an
1094 exception if not. Currently a no-op.
1095 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1096 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1097 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1098 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1100 * mips.igen (check_fpu): New function which in the future will
1101 check whether FPU instructions are usable and signal an exception
1102 if not. Currently a no-op.
1103 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1104 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1105 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1106 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1107 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1108 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1109 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1110 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1112 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1114 * mips.igen (do_load_left, do_load_right): Move to be immediately
1116 (do_store_left, do_store_right): Move to be immediately following
1119 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1121 * mips.igen (mipsV): New model name. Also, add it to
1122 all instructions and functions where it is appropriate.
1124 2002-02-18 Chris Demetriou <cgd@broadcom.com>
1126 * mips.igen: For all functions and instructions, list model
1127 names that support that instruction one per line.
1129 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1131 * mips.igen: Add some additional comments about supported
1132 models, and about which instructions go where.
1133 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1134 order as is used in the rest of the file.
1136 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1138 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1139 indicating that ALU32_END or ALU64_END are there to check
1141 (DADD): Likewise, but also remove previous comment about
1144 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1146 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1147 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1148 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1149 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1150 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1151 fields (i.e., add and move commas) so that they more closely
1152 match the MIPS ISA documentation opcode partitioning.
1154 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1156 * mips.igen (ADDI): Print immediate value.
1157 (BREAK): Print code.
1158 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1159 (SLL): Print "nop" specially, and don't run the code
1160 that does the shift for the "nop" case.
1162 2001-11-17 Fred Fish <fnf@redhat.com>
1164 * sim-main.h (float_operation): Move enum declaration outside
1165 of _sim_cpu struct declaration.
1167 2001-04-12 Jim Blandy <jimb@redhat.com>
1169 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1170 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1172 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1173 PENDING_FILL, and you can get the intended effect gracefully by
1174 calling PENDING_SCHED directly.
1176 2001-02-23 Ben Elliston <bje@redhat.com>
1178 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1179 already defined elsewhere.
1181 2001-02-19 Ben Elliston <bje@redhat.com>
1183 * sim-main.h (sim_monitor): Return an int.
1184 * interp.c (sim_monitor): Add return values.
1185 (signal_exception): Handle error conditions from sim_monitor.
1187 2001-02-08 Ben Elliston <bje@redhat.com>
1189 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1190 (store_memory): Likewise, pass cia to sim_core_write*.
1192 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
1194 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1195 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1197 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1199 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1200 * Makefile.in: Don't delete *.igen when cleaning directory.
1202 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1204 * m16.igen (break): Call SignalException not sim_engine_halt.
1206 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1208 From Jason Eckhardt:
1209 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1211 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1213 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1215 2000-05-24 Michael Hayes <mhayes@cygnus.com>
1217 * mips.igen (do_dmultx): Fix typo.
1219 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1221 * configure: Regenerated to track ../common/aclocal.m4 changes.
1223 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1225 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1227 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
1229 * sim-main.h (GPR_CLEAR): Define macro.
1231 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1233 * interp.c (decode_coproc): Output long using %lx and not %s.
1235 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
1237 * interp.c (sim_open): Sort & extend dummy memory regions for
1238 --board=jmr3904 for eCos.
1240 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
1242 * configure: Regenerated.
1244 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1246 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1247 calls, conditional on the simulator being in verbose mode.
1249 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1251 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1252 cache don't get ReservedInstruction traps.
1254 1999-11-29 Mark Salter <msalter@cygnus.com>
1256 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1257 to clear status bits in sdisr register. This is how the hardware works.
1259 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1260 being used by cygmon.
1262 1999-11-11 Andrew Haley <aph@cygnus.com>
1264 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1267 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1269 * mips.igen (MULT): Correct previous mis-applied patch.
1271 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1273 * mips.igen (delayslot32): Handle sequence like
1274 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1275 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1276 (MULT): Actually pass the third register...
1278 1999-09-03 Mark Salter <msalter@cygnus.com>
1280 * interp.c (sim_open): Added more memory aliases for additional
1281 hardware being touched by cygmon on jmr3904 board.
1283 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1285 * configure: Regenerated to track ../common/aclocal.m4 changes.
1287 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1289 * interp.c (sim_store_register): Handle case where client - GDB -
1290 specifies that a 4 byte register is 8 bytes in size.
1291 (sim_fetch_register): Ditto.
1293 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1295 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1296 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1297 (idt_monitor_base): Base address for IDT monitor traps.
1298 (pmon_monitor_base): Ditto for PMON.
1299 (lsipmon_monitor_base): Ditto for LSI PMON.
1300 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1301 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1302 (sim_firmware_command): New function.
1303 (mips_option_handler): Call it for OPTION_FIRMWARE.
1304 (sim_open): Allocate memory for idt_monitor region. If "--board"
1305 option was given, add no monitor by default. Add BREAK hooks only if
1306 monitors are also there.
1308 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1310 * interp.c (sim_monitor): Flush output before reading input.
1312 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1314 * tconfig.in (SIM_HANDLES_LMA): Always define.
1316 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1318 From Mark Salter <msalter@cygnus.com>:
1319 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1320 (sim_open): Add setup for BSP board.
1322 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1324 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1325 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1326 them as unimplemented.
1328 1999-05-08 Felix Lee <flee@cygnus.com>
1330 * configure: Regenerated to track ../common/aclocal.m4 changes.
1332 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1334 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1336 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1338 * configure.in: Any mips64vr5*-*-* target should have
1339 -DTARGET_ENABLE_FR=1.
1340 (default_endian): Any mips64vr*el-*-* target should default to
1342 * configure: Re-generate.
1344 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1346 * mips.igen (ldl): Extend from _16_, not 32.
1348 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1350 * interp.c (sim_store_register): Force registers written to by GDB
1351 into an un-interpreted state.
1353 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1355 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1356 CPU, start periodic background I/O polls.
1357 (tx3904sio_poll): New function: periodic I/O poller.
1359 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1361 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1363 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1365 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1368 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1370 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1371 (load_word): Call SIM_CORE_SIGNAL hook on error.
1372 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1373 starting. For exception dispatching, pass PC instead of NULL_CIA.
1374 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1375 * sim-main.h (COP0_BADVADDR): Define.
1376 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1377 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1378 (_sim_cpu): Add exc_* fields to store register value snapshots.
1379 * mips.igen (*): Replace memory-related SignalException* calls
1380 with references to SIM_CORE_SIGNAL hook.
1382 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1384 * sim-main.c (*): Minor warning cleanups.
1386 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1388 * m16.igen (DADDIU5): Correct type-o.
1390 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1392 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1395 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1397 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1399 (interp.o): Add dependency on itable.h
1400 (oengine.c, gencode): Delete remaining references.
1401 (BUILT_SRC_FROM_GEN): Clean up.
1403 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1406 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1407 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1408 tmp-run-hack) : New.
1409 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1410 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1411 Drop the "64" qualifier to get the HACK generator working.
1412 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1413 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1414 qualifier to get the hack generator working.
1415 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1416 (DSLL): Use do_dsll.
1417 (DSLLV): Use do_dsllv.
1418 (DSRA): Use do_dsra.
1419 (DSRL): Use do_dsrl.
1420 (DSRLV): Use do_dsrlv.
1421 (BC1): Move *vr4100 to get the HACK generator working.
1422 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1423 get the HACK generator working.
1424 (MACC) Rename to get the HACK generator working.
1425 (DMACC,MACCS,DMACCS): Add the 64.
1427 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1429 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1430 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1432 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1434 * mips/interp.c (DEBUG): Cleanups.
1436 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1438 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1439 (tx3904sio_tickle): fflush after a stdout character output.
1441 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1443 * interp.c (sim_close): Uninstall modules.
1445 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1447 * sim-main.h, interp.c (sim_monitor): Change to global
1450 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1452 * configure.in (vr4100): Only include vr4100 instructions in
1454 * configure: Re-generate.
1455 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1457 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1459 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1460 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1463 * configure.in (sim_default_gen, sim_use_gen): Replace with
1465 (--enable-sim-igen): Delete config option. Always using IGEN.
1466 * configure: Re-generate.
1468 * Makefile.in (gencode): Kill, kill, kill.
1471 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1473 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1474 bit mips16 igen simulator.
1475 * configure: Re-generate.
1477 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1478 as part of vr4100 ISA.
1479 * vr.igen: Mark all instructions as 64 bit only.
1481 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1483 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1486 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1488 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1489 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1490 * configure: Re-generate.
1492 * m16.igen (BREAK): Define breakpoint instruction.
1493 (JALX32): Mark instruction as mips16 and not r3900.
1494 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1496 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1498 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1500 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1501 insn as a debug breakpoint.
1503 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1505 (PENDING_SCHED): Clean up trace statement.
1506 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1507 (PENDING_FILL): Delay write by only one cycle.
1508 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1510 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1512 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1514 (pending_tick): Move incrementing of index to FOR statement.
1515 (pending_tick): Only update PENDING_OUT after a write has occured.
1517 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1519 * configure: Re-generate.
1521 * interp.c (sim_engine_run OLD): Delete explicit call to
1522 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1524 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1526 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1527 interrupt level number to match changed SignalExceptionInterrupt
1530 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1532 * interp.c: #include "itable.h" if WITH_IGEN.
1533 (get_insn_name): New function.
1534 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1535 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1537 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1539 * configure: Rebuilt to inhale new common/aclocal.m4.
1541 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1543 * dv-tx3904sio.c: Include sim-assert.h.
1545 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1547 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1548 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1549 Reorganize target-specific sim-hardware checks.
1550 * configure: rebuilt.
1551 * interp.c (sim_open): For tx39 target boards, set
1552 OPERATING_ENVIRONMENT, add tx3904sio devices.
1553 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1554 ROM executables. Install dv-sockser into sim-modules list.
1556 * dv-tx3904irc.c: Compiler warning clean-up.
1557 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1558 frequent hw-trace messages.
1560 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1562 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1564 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1566 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1568 * vr.igen: New file.
1569 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1570 * mips.igen: Define vr4100 model. Include vr.igen.
1571 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1573 * mips.igen (check_mf_hilo): Correct check.
1575 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1577 * sim-main.h (interrupt_event): Add prototype.
1579 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1580 register_ptr, register_value.
1581 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1583 * sim-main.h (tracefh): Make extern.
1585 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1587 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1588 Reduce unnecessarily high timer event frequency.
1589 * dv-tx3904cpu.c: Ditto for interrupt event.
1591 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1593 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1595 (interrupt_event): Made non-static.
1597 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1598 interchange of configuration values for external vs. internal
1601 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1603 * mips.igen (BREAK): Moved code to here for
1604 simulator-reserved break instructions.
1605 * gencode.c (build_instruction): Ditto.
1606 * interp.c (signal_exception): Code moved from here. Non-
1607 reserved instructions now use exception vector, rather
1609 * sim-main.h: Moved magic constants to here.
1611 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1613 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1614 register upon non-zero interrupt event level, clear upon zero
1616 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1617 by passing zero event value.
1618 (*_io_{read,write}_buffer): Endianness fixes.
1619 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1620 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1622 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1623 serial I/O and timer module at base address 0xFFFF0000.
1625 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1627 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1630 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1632 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1634 * configure: Update.
1636 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1638 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1639 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1640 * configure.in: Include tx3904tmr in hw_device list.
1641 * configure: Rebuilt.
1642 * interp.c (sim_open): Instantiate three timer instances.
1643 Fix address typo of tx3904irc instance.
1645 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1647 * interp.c (signal_exception): SystemCall exception now uses
1648 the exception vector.
1650 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1652 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1655 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1657 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1659 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1661 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1663 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1664 sim-main.h. Declare a struct hw_descriptor instead of struct
1665 hw_device_descriptor.
1667 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1669 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1670 right bits and then re-align left hand bytes to correct byte
1671 lanes. Fix incorrect computation in do_store_left when loading
1672 bytes from second word.
1674 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1676 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1677 * interp.c (sim_open): Only create a device tree when HW is
1680 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1681 * interp.c (signal_exception): Ditto.
1683 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1685 * gencode.c: Mark BEGEZALL as LIKELY.
1687 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1689 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1690 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1692 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1694 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1695 modules. Recognize TX39 target with "mips*tx39" pattern.
1696 * configure: Rebuilt.
1697 * sim-main.h (*): Added many macros defining bits in
1698 TX39 control registers.
1699 (SignalInterrupt): Send actual PC instead of NULL.
1700 (SignalNMIReset): New exception type.
1701 * interp.c (board): New variable for future use to identify
1702 a particular board being simulated.
1703 (mips_option_handler,mips_options): Added "--board" option.
1704 (interrupt_event): Send actual PC.
1705 (sim_open): Make memory layout conditional on board setting.
1706 (signal_exception): Initial implementation of hardware interrupt
1707 handling. Accept another break instruction variant for simulator
1709 (decode_coproc): Implement RFE instruction for TX39.
1710 (mips.igen): Decode RFE instruction as such.
1711 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1712 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1713 bbegin to implement memory map.
1714 * dv-tx3904cpu.c: New file.
1715 * dv-tx3904irc.c: New file.
1717 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1719 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1721 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1723 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1724 with calls to check_div_hilo.
1726 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1728 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1729 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1730 Add special r3900 version of do_mult_hilo.
1731 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1732 with calls to check_mult_hilo.
1733 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1734 with calls to check_div_hilo.
1736 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1738 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1739 Document a replacement.
1741 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1743 * interp.c (sim_monitor): Make mon_printf work.
1745 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1747 * sim-main.h (INSN_NAME): New arg `cpu'.
1749 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1751 * configure: Regenerated to track ../common/aclocal.m4 changes.
1753 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1755 * configure: Regenerated to track ../common/aclocal.m4 changes.
1758 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1760 * acconfig.h: New file.
1761 * configure.in: Reverted change of Apr 24; use sinclude again.
1763 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1765 * configure: Regenerated to track ../common/aclocal.m4 changes.
1768 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1770 * configure.in: Don't call sinclude.
1772 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1774 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1776 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1778 * mips.igen (ERET): Implement.
1780 * interp.c (decode_coproc): Return sign-extended EPC.
1782 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1784 * interp.c (signal_exception): Do not ignore Trap.
1785 (signal_exception): On TRAP, restart at exception address.
1786 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1787 (signal_exception): Update.
1788 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1789 so that TRAP instructions are caught.
1791 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1793 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1794 contains HI/LO access history.
1795 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1796 (HIACCESS, LOACCESS): Delete, replace with
1797 (HIHISTORY, LOHISTORY): New macros.
1798 (CHECKHILO): Delete all, moved to mips.igen
1800 * gencode.c (build_instruction): Do not generate checks for
1801 correct HI/LO register usage.
1803 * interp.c (old_engine_run): Delete checks for correct HI/LO
1806 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1807 check_mf_cycles): New functions.
1808 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1809 do_divu, domultx, do_mult, do_multu): Use.
1811 * tx.igen ("madd", "maddu"): Use.
1813 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1815 * mips.igen (DSRAV): Use function do_dsrav.
1816 (SRAV): Use new function do_srav.
1818 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1819 (B): Sign extend 11 bit immediate.
1820 (EXT-B*): Shift 16 bit immediate left by 1.
1821 (ADDIU*): Don't sign extend immediate value.
1823 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1825 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1827 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1830 * mips.igen (delayslot32, nullify_next_insn): New functions.
1831 (m16.igen): Always include.
1832 (do_*): Add more tracing.
1834 * m16.igen (delayslot16): Add NIA argument, could be called by a
1835 32 bit MIPS16 instruction.
1837 * interp.c (ifetch16): Move function from here.
1838 * sim-main.c (ifetch16): To here.
1840 * sim-main.c (ifetch16, ifetch32): Update to match current
1841 implementations of LH, LW.
1842 (signal_exception): Don't print out incorrect hex value of illegal
1845 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1847 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1850 * m16.igen: Implement MIPS16 instructions.
1852 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1853 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1854 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1855 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1856 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1857 bodies of corresponding code from 32 bit insn to these. Also used
1858 by MIPS16 versions of functions.
1860 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1861 (IMEM16): Drop NR argument from macro.
1863 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1865 * Makefile.in (SIM_OBJS): Add sim-main.o.
1867 * sim-main.h (address_translation, load_memory, store_memory,
1868 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1870 (pr_addr, pr_uword64): Declare.
1871 (sim-main.c): Include when H_REVEALS_MODULE_P.
1873 * interp.c (address_translation, load_memory, store_memory,
1874 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1876 * sim-main.c: To here. Fix compilation problems.
1878 * configure.in: Enable inlining.
1879 * configure: Re-config.
1881 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1883 * configure: Regenerated to track ../common/aclocal.m4 changes.
1885 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1887 * mips.igen: Include tx.igen.
1888 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1889 * tx.igen: New file, contains MADD and MADDU.
1891 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1892 the hardwired constant `7'.
1893 (store_memory): Ditto.
1894 (LOADDRMASK): Move definition to sim-main.h.
1896 mips.igen (MTC0): Enable for r3900.
1899 mips.igen (do_load_byte): Delete.
1900 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1901 do_store_right): New functions.
1902 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1904 configure.in: Let the tx39 use igen again.
1907 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1909 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1910 not an address sized quantity. Return zero for cache sizes.
1912 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1914 * mips.igen (r3900): r3900 does not support 64 bit integer
1917 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1919 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1921 * configure : Rebuild.
1923 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1925 * configure: Regenerated to track ../common/aclocal.m4 changes.
1927 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1929 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1931 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1933 * configure: Regenerated to track ../common/aclocal.m4 changes.
1934 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1936 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1938 * configure: Regenerated to track ../common/aclocal.m4 changes.
1940 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1942 * interp.c (Max, Min): Comment out functions. Not yet used.
1944 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1946 * configure: Regenerated to track ../common/aclocal.m4 changes.
1948 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1950 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1951 configurable settings for stand-alone simulator.
1953 * configure.in: Added X11 search, just in case.
1955 * configure: Regenerated.
1957 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1959 * interp.c (sim_write, sim_read, load_memory, store_memory):
1960 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1962 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1964 * sim-main.h (GETFCC): Return an unsigned value.
1966 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1968 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1969 (DADD): Result destination is RD not RT.
1971 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1973 * sim-main.h (HIACCESS, LOACCESS): Always define.
1975 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1977 * interp.c (sim_info): Delete.
1979 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1981 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1982 (mips_option_handler): New argument `cpu'.
1983 (sim_open): Update call to sim_add_option_table.
1985 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1987 * mips.igen (CxC1): Add tracing.
1989 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1991 * sim-main.h (Max, Min): Declare.
1993 * interp.c (Max, Min): New functions.
1995 * mips.igen (BC1): Add tracing.
1997 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1999 * interp.c Added memory map for stack in vr4100
2001 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2003 * interp.c (load_memory): Add missing "break"'s.
2005 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2007 * interp.c (sim_store_register, sim_fetch_register): Pass in
2008 length parameter. Return -1.
2010 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2012 * interp.c: Added hardware init hook, fixed warnings.
2014 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2016 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2018 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2020 * interp.c (ifetch16): New function.
2022 * sim-main.h (IMEM32): Rename IMEM.
2023 (IMEM16_IMMED): Define.
2025 (DELAY_SLOT): Update.
2027 * m16run.c (sim_engine_run): New file.
2029 * m16.igen: All instructions except LB.
2030 (LB): Call do_load_byte.
2031 * mips.igen (do_load_byte): New function.
2032 (LB): Call do_load_byte.
2034 * mips.igen: Move spec for insn bit size and high bit from here.
2035 * Makefile.in (tmp-igen, tmp-m16): To here.
2037 * m16.dc: New file, decode mips16 instructions.
2039 * Makefile.in (SIM_NO_ALL): Define.
2040 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2042 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2044 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2045 point unit to 32 bit registers.
2046 * configure: Re-generate.
2048 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2050 * configure.in (sim_use_gen): Make IGEN the default simulator
2051 generator for generic 32 and 64 bit mips targets.
2052 * configure: Re-generate.
2054 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2056 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2059 * interp.c (sim_fetch_register, sim_store_register): Read/write
2060 FGR from correct location.
2061 (sim_open): Set size of FGR's according to
2062 WITH_TARGET_FLOATING_POINT_BITSIZE.
2064 * sim-main.h (FGR): Store floating point registers in a separate
2067 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2069 * configure: Regenerated to track ../common/aclocal.m4 changes.
2071 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2073 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2075 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2077 * interp.c (pending_tick): New function. Deliver pending writes.
2079 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2080 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2081 it can handle mixed sized quantites and single bits.
2083 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2085 * interp.c (oengine.h): Do not include when building with IGEN.
2086 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2087 (sim_info): Ditto for PROCESSOR_64BIT.
2088 (sim_monitor): Replace ut_reg with unsigned_word.
2089 (*): Ditto for t_reg.
2090 (LOADDRMASK): Define.
2091 (sim_open): Remove defunct check that host FP is IEEE compliant,
2092 using software to emulate floating point.
2093 (value_fpr, ...): Always compile, was conditional on HASFPU.
2095 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2097 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2100 * interp.c (SD, CPU): Define.
2101 (mips_option_handler): Set flags in each CPU.
2102 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2103 (sim_close): Do not clear STATE, deleted anyway.
2104 (sim_write, sim_read): Assume CPU zero's vm should be used for
2106 (sim_create_inferior): Set the PC for all processors.
2107 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2109 (mips16_entry): Pass correct nr of args to store_word, load_word.
2110 (ColdReset): Cold reset all cpu's.
2111 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2112 (sim_monitor, load_memory, store_memory, signal_exception): Use
2113 `CPU' instead of STATE_CPU.
2116 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2119 * sim-main.h (signal_exception): Add sim_cpu arg.
2120 (SignalException*): Pass both SD and CPU to signal_exception.
2121 * interp.c (signal_exception): Update.
2123 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2125 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2126 address_translation): Ditto
2127 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2129 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2131 * configure: Regenerated to track ../common/aclocal.m4 changes.
2133 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2135 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2137 * mips.igen (model): Map processor names onto BFD name.
2139 * sim-main.h (CPU_CIA): Delete.
2140 (SET_CIA, GET_CIA): Define
2142 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2144 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2147 * configure.in (default_endian): Configure a big-endian simulator
2149 * configure: Re-generate.
2151 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2153 * configure: Regenerated to track ../common/aclocal.m4 changes.
2155 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2157 * interp.c (sim_monitor): Handle Densan monitor outbyte
2158 and inbyte functions.
2160 1997-12-29 Felix Lee <flee@cygnus.com>
2162 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2164 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2166 * Makefile.in (tmp-igen): Arrange for $zero to always be
2167 reset to zero after every instruction.
2169 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2171 * configure: Regenerated to track ../common/aclocal.m4 changes.
2174 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2176 * mips.igen (MSUB): Fix to work like MADD.
2177 * gencode.c (MSUB): Similarly.
2179 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2181 * configure: Regenerated to track ../common/aclocal.m4 changes.
2183 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2185 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2187 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2189 * sim-main.h (sim-fpu.h): Include.
2191 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2192 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2193 using host independant sim_fpu module.
2195 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2197 * interp.c (signal_exception): Report internal errors with SIGABRT
2200 * sim-main.h (C0_CONFIG): New register.
2201 (signal.h): No longer include.
2203 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2205 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2207 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2209 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2211 * mips.igen: Tag vr5000 instructions.
2212 (ANDI): Was missing mipsIV model, fix assembler syntax.
2213 (do_c_cond_fmt): New function.
2214 (C.cond.fmt): Handle mips I-III which do not support CC field
2216 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2217 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2219 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2220 vr5000 which saves LO in a GPR separatly.
2222 * configure.in (enable-sim-igen): For vr5000, select vr5000
2223 specific instructions.
2224 * configure: Re-generate.
2226 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2228 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2230 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2231 fmt_uninterpreted_64 bit cases to switch. Convert to
2234 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2236 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2237 as specified in IV3.2 spec.
2238 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2240 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2242 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2243 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2244 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2245 PENDING_FILL versions of instructions. Simplify.
2247 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2249 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2251 (MTHI, MFHI): Disable code checking HI-LO.
2253 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2255 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2257 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2259 * gencode.c (build_mips16_operands): Replace IPC with cia.
2261 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2262 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2264 (UndefinedResult): Replace function with macro/function
2266 (sim_engine_run): Don't save PC in IPC.
2268 * sim-main.h (IPC): Delete.
2271 * interp.c (signal_exception, store_word, load_word,
2272 address_translation, load_memory, store_memory, cache_op,
2273 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2274 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2275 current instruction address - cia - argument.
2276 (sim_read, sim_write): Call address_translation directly.
2277 (sim_engine_run): Rename variable vaddr to cia.
2278 (signal_exception): Pass cia to sim_monitor
2280 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2281 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2282 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2284 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2285 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2288 * interp.c (signal_exception): Pass restart address to
2291 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2292 idecode.o): Add dependency.
2294 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2296 (DELAY_SLOT): Update NIA not PC with branch address.
2297 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2299 * mips.igen: Use CIA not PC in branch calculations.
2300 (illegal): Call SignalException.
2301 (BEQ, ADDIU): Fix assembler.
2303 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2305 * m16.igen (JALX): Was missing.
2307 * configure.in (enable-sim-igen): New configuration option.
2308 * configure: Re-generate.
2310 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2312 * interp.c (load_memory, store_memory): Delete parameter RAW.
2313 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2314 bypassing {load,store}_memory.
2316 * sim-main.h (ByteSwapMem): Delete definition.
2318 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2320 * interp.c (sim_do_command, sim_commands): Delete mips specific
2321 commands. Handled by module sim-options.
2323 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2324 (WITH_MODULO_MEMORY): Define.
2326 * interp.c (sim_info): Delete code printing memory size.
2328 * interp.c (mips_size): Nee sim_size, delete function.
2330 (monitor, monitor_base, monitor_size): Delete global variables.
2331 (sim_open, sim_close): Delete code creating monitor and other
2332 memory regions. Use sim-memopts module, via sim_do_commandf, to
2333 manage memory regions.
2334 (load_memory, store_memory): Use sim-core for memory model.
2336 * interp.c (address_translation): Delete all memory map code
2337 except line forcing 32 bit addresses.
2339 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2341 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2344 * interp.c (logfh, logfile): Delete globals.
2345 (sim_open, sim_close): Delete code opening & closing log file.
2346 (mips_option_handler): Delete -l and -n options.
2347 (OPTION mips_options): Ditto.
2349 * interp.c (OPTION mips_options): Rename option trace to dinero.
2350 (mips_option_handler): Update.
2352 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2354 * interp.c (fetch_str): New function.
2355 (sim_monitor): Rewrite using sim_read & sim_write.
2356 (sim_open): Check magic number.
2357 (sim_open): Write monitor vectors into memory using sim_write.
2358 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2359 (sim_read, sim_write): Simplify - transfer data one byte at a
2361 (load_memory, store_memory): Clarify meaning of parameter RAW.
2363 * sim-main.h (isHOST): Defete definition.
2364 (isTARGET): Mark as depreciated.
2365 (address_translation): Delete parameter HOST.
2367 * interp.c (address_translation): Delete parameter HOST.
2369 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2373 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2374 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2376 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2378 * mips.igen: Add model filter field to records.
2380 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2382 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2384 interp.c (sim_engine_run): Do not compile function sim_engine_run
2385 when WITH_IGEN == 1.
2387 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2388 target architecture.
2390 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2391 igen. Replace with configuration variables sim_igen_flags /
2394 * m16.igen: New file. Copy mips16 insns here.
2395 * mips.igen: From here.
2397 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2399 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2401 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2403 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2405 * gencode.c (build_instruction): Follow sim_write's lead in using
2406 BigEndianMem instead of !ByteSwapMem.
2408 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2410 * configure.in (sim_gen): Dependent on target, select type of
2411 generator. Always select old style generator.
2413 configure: Re-generate.
2415 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2417 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2418 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2419 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2420 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2421 SIM_@sim_gen@_*, set by autoconf.
2423 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2425 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2427 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2428 CURRENT_FLOATING_POINT instead.
2430 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2431 (address_translation): Raise exception InstructionFetch when
2432 translation fails and isINSTRUCTION.
2434 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2435 sim_engine_run): Change type of of vaddr and paddr to
2437 (address_translation, prefetch, load_memory, store_memory,
2438 cache_op): Change type of vAddr and pAddr to address_word.
2440 * gencode.c (build_instruction): Change type of vaddr and paddr to
2443 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2445 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2446 macro to obtain result of ALU op.
2448 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2450 * interp.c (sim_info): Call profile_print.
2452 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2454 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2456 * sim-main.h (WITH_PROFILE): Do not define, defined in
2457 common/sim-config.h. Use sim-profile module.
2458 (simPROFILE): Delete defintion.
2460 * interp.c (PROFILE): Delete definition.
2461 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2462 (sim_close): Delete code writing profile histogram.
2463 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2465 (sim_engine_run): Delete code profiling the PC.
2467 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2469 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2471 * interp.c (sim_monitor): Make register pointers of type
2474 * sim-main.h: Make registers of type unsigned_word not
2477 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2479 * interp.c (sync_operation): Rename from SyncOperation, make
2480 global, add SD argument.
2481 (prefetch): Rename from Prefetch, make global, add SD argument.
2482 (decode_coproc): Make global.
2484 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2486 * gencode.c (build_instruction): Generate DecodeCoproc not
2487 decode_coproc calls.
2489 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2490 (SizeFGR): Move to sim-main.h
2491 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2492 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2493 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2495 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2496 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2497 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2498 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2499 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2500 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2502 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2504 (sim-alu.h): Include.
2505 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2506 (sim_cia): Typedef to instruction_address.
2508 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2510 * Makefile.in (interp.o): Rename generated file engine.c to
2515 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2517 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2519 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2521 * gencode.c (build_instruction): For "FPSQRT", output correct
2522 number of arguments to Recip.
2524 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2526 * Makefile.in (interp.o): Depends on sim-main.h
2528 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2530 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2531 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2532 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2533 STATE, DSSTATE): Define
2534 (GPR, FGRIDX, ..): Define.
2536 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2537 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2538 (GPR, FGRIDX, ...): Delete macros.
2540 * interp.c: Update names to match defines from sim-main.h
2542 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2544 * interp.c (sim_monitor): Add SD argument.
2545 (sim_warning): Delete. Replace calls with calls to
2547 (sim_error): Delete. Replace calls with sim_io_error.
2548 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2549 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2550 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2552 (mips_size): Rename from sim_size. Add SD argument.
2554 * interp.c (simulator): Delete global variable.
2555 (callback): Delete global variable.
2556 (mips_option_handler, sim_open, sim_write, sim_read,
2557 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2558 sim_size,sim_monitor): Use sim_io_* not callback->*.
2559 (sim_open): ZALLOC simulator struct.
2560 (PROFILE): Do not define.
2562 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2564 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2565 support.h with corresponding code.
2567 * sim-main.h (word64, uword64), support.h: Move definition to
2569 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2572 * Makefile.in: Update dependencies
2573 * interp.c: Do not include.
2575 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2577 * interp.c (address_translation, load_memory, store_memory,
2578 cache_op): Rename to from AddressTranslation et.al., make global,
2581 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2584 * interp.c (SignalException): Rename to signal_exception, make
2587 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2589 * sim-main.h (SignalException, SignalExceptionInterrupt,
2590 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2591 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2592 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2595 * interp.c, support.h: Use.
2597 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2599 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2600 to value_fpr / store_fpr. Add SD argument.
2601 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2602 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2604 * sim-main.h (ValueFPR, StoreFPR): Define.
2606 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2608 * interp.c (sim_engine_run): Check consistency between configure
2609 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2612 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2613 (mips_fpu): Configure WITH_FLOATING_POINT.
2614 (mips_endian): Configure WITH_TARGET_ENDIAN.
2615 * configure: Update.
2617 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2619 * configure: Regenerated to track ../common/aclocal.m4 changes.
2621 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2623 * configure: Regenerated.
2625 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2627 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2629 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2631 * gencode.c (print_igen_insn_models): Assume certain architectures
2632 include all mips* instructions.
2633 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2636 * Makefile.in (tmp.igen): Add target. Generate igen input from
2639 * gencode.c (FEATURE_IGEN): Define.
2640 (main): Add --igen option. Generate output in igen format.
2641 (process_instructions): Format output according to igen option.
2642 (print_igen_insn_format): New function.
2643 (print_igen_insn_models): New function.
2644 (process_instructions): Only issue warnings and ignore
2645 instructions when no FEATURE_IGEN.
2647 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2649 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2652 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2654 * configure: Regenerated to track ../common/aclocal.m4 changes.
2656 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2658 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2659 SIM_RESERVED_BITS): Delete, moved to common.
2660 (SIM_EXTRA_CFLAGS): Update.
2662 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2664 * configure.in: Configure non-strict memory alignment.
2665 * configure: Regenerated to track ../common/aclocal.m4 changes.
2667 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2669 * configure: Regenerated to track ../common/aclocal.m4 changes.
2671 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2673 * gencode.c (SDBBP,DERET): Added (3900) insns.
2674 (RFE): Turn on for 3900.
2675 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2676 (dsstate): Made global.
2677 (SUBTARGET_R3900): Added.
2678 (CANCELDELAYSLOT): New.
2679 (SignalException): Ignore SystemCall rather than ignore and
2680 terminate. Add DebugBreakPoint handling.
2681 (decode_coproc): New insns RFE, DERET; and new registers Debug
2682 and DEPC protected by SUBTARGET_R3900.
2683 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2685 * Makefile.in,configure.in: Add mips subtarget option.
2686 * configure: Update.
2688 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2690 * gencode.c: Add r3900 (tx39).
2693 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2695 * gencode.c (build_instruction): Don't need to subtract 4 for
2698 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2700 * interp.c: Correct some HASFPU problems.
2702 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2704 * configure: Regenerated to track ../common/aclocal.m4 changes.
2706 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2708 * interp.c (mips_options): Fix samples option short form, should
2711 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2713 * interp.c (sim_info): Enable info code. Was just returning.
2715 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2717 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2720 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2722 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2724 (build_instruction): Ditto for LL.
2726 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2728 * configure: Regenerated to track ../common/aclocal.m4 changes.
2730 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2732 * configure: Regenerated to track ../common/aclocal.m4 changes.
2735 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2737 * interp.c (sim_open): Add call to sim_analyze_program, update
2740 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2742 * interp.c (sim_kill): Delete.
2743 (sim_create_inferior): Add ABFD argument. Set PC from same.
2744 (sim_load): Move code initializing trap handlers from here.
2745 (sim_open): To here.
2746 (sim_load): Delete, use sim-hload.c.
2748 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2750 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2752 * configure: Regenerated to track ../common/aclocal.m4 changes.
2755 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2757 * interp.c (sim_open): Add ABFD argument.
2758 (sim_load): Move call to sim_config from here.
2759 (sim_open): To here. Check return status.
2761 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2763 * gencode.c (build_instruction): Two arg MADD should
2764 not assign result to $0.
2766 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2768 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2769 * sim/mips/configure.in: Regenerate.
2771 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2773 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2774 signed8, unsigned8 et.al. types.
2776 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2777 hosts when selecting subreg.
2779 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2781 * interp.c (sim_engine_run): Reset the ZERO register to zero
2782 regardless of FEATURE_WARN_ZERO.
2783 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2785 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2787 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2788 (SignalException): For BreakPoints ignore any mode bits and just
2790 (SignalException): Always set the CAUSE register.
2792 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2794 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2795 exception has been taken.
2797 * interp.c: Implement the ERET and mt/f sr instructions.
2799 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2801 * interp.c (SignalException): Don't bother restarting an
2804 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2806 * interp.c (SignalException): Really take an interrupt.
2807 (interrupt_event): Only deliver interrupts when enabled.
2809 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2811 * interp.c (sim_info): Only print info when verbose.
2812 (sim_info) Use sim_io_printf for output.
2814 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2816 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2819 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2821 * interp.c (sim_do_command): Check for common commands if a
2822 simulator specific command fails.
2824 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2826 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2827 and simBE when DEBUG is defined.
2829 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2831 * interp.c (interrupt_event): New function. Pass exception event
2832 onto exception handler.
2834 * configure.in: Check for stdlib.h.
2835 * configure: Regenerate.
2837 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2838 variable declaration.
2839 (build_instruction): Initialize memval1.
2840 (build_instruction): Add UNUSED attribute to byte, bigend,
2842 (build_operands): Ditto.
2844 * interp.c: Fix GCC warnings.
2845 (sim_get_quit_code): Delete.
2847 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2848 * Makefile.in: Ditto.
2849 * configure: Re-generate.
2851 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2853 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2855 * interp.c (mips_option_handler): New function parse argumes using
2857 (myname): Replace with STATE_MY_NAME.
2858 (sim_open): Delete check for host endianness - performed by
2860 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2861 (sim_open): Move much of the initialization from here.
2862 (sim_load): To here. After the image has been loaded and
2864 (sim_open): Move ColdReset from here.
2865 (sim_create_inferior): To here.
2866 (sim_open): Make FP check less dependant on host endianness.
2868 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2870 * interp.c (sim_set_callbacks): Delete.
2872 * interp.c (membank, membank_base, membank_size): Replace with
2873 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2874 (sim_open): Remove call to callback->init. gdb/run do this.
2878 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2880 * interp.c (big_endian_p): Delete, replaced by
2881 current_target_byte_order.
2883 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2885 * interp.c (host_read_long, host_read_word, host_swap_word,
2886 host_swap_long): Delete. Using common sim-endian.
2887 (sim_fetch_register, sim_store_register): Use H2T.
2888 (pipeline_ticks): Delete. Handled by sim-events.
2890 (sim_engine_run): Update.
2892 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2894 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2896 (SignalException): To here. Signal using sim_engine_halt.
2897 (sim_stop_reason): Delete, moved to common.
2899 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2901 * interp.c (sim_open): Add callback argument.
2902 (sim_set_callbacks): Delete SIM_DESC argument.
2905 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2907 * Makefile.in (SIM_OBJS): Add common modules.
2909 * interp.c (sim_set_callbacks): Also set SD callback.
2910 (set_endianness, xfer_*, swap_*): Delete.
2911 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2912 Change to functions using sim-endian macros.
2913 (control_c, sim_stop): Delete, use common version.
2914 (simulate): Convert into.
2915 (sim_engine_run): This function.
2916 (sim_resume): Delete.
2918 * interp.c (simulation): New variable - the simulator object.
2919 (sim_kind): Delete global - merged into simulation.
2920 (sim_load): Cleanup. Move PC assignment from here.
2921 (sim_create_inferior): To here.
2923 * sim-main.h: New file.
2924 * interp.c (sim-main.h): Include.
2926 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2928 * configure: Regenerated to track ../common/aclocal.m4 changes.
2930 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2932 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2934 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2936 * gencode.c (build_instruction): DIV instructions: check
2937 for division by zero and integer overflow before using
2938 host's division operation.
2940 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2942 * Makefile.in (SIM_OBJS): Add sim-load.o.
2943 * interp.c: #include bfd.h.
2944 (target_byte_order): Delete.
2945 (sim_kind, myname, big_endian_p): New static locals.
2946 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2947 after argument parsing. Recognize -E arg, set endianness accordingly.
2948 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2949 load file into simulator. Set PC from bfd.
2950 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2951 (set_endianness): Use big_endian_p instead of target_byte_order.
2953 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2955 * interp.c (sim_size): Delete prototype - conflicts with
2956 definition in remote-sim.h. Correct definition.
2958 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2960 * configure: Regenerated to track ../common/aclocal.m4 changes.
2963 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2965 * interp.c (sim_open): New arg `kind'.
2967 * configure: Regenerated to track ../common/aclocal.m4 changes.
2969 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2971 * configure: Regenerated to track ../common/aclocal.m4 changes.
2973 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2975 * interp.c (sim_open): Set optind to 0 before calling getopt.
2977 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2979 * configure: Regenerated to track ../common/aclocal.m4 changes.
2981 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2983 * interp.c : Replace uses of pr_addr with pr_uword64
2984 where the bit length is always 64 independent of SIM_ADDR.
2985 (pr_uword64) : added.
2987 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2989 * configure: Re-generate.
2991 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2993 * configure: Regenerate to track ../common/aclocal.m4 changes.
2995 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2997 * interp.c (sim_open): New SIM_DESC result. Argument is now
2999 (other sim_*): New SIM_DESC argument.
3001 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3003 * interp.c: Fix printing of addresses for non-64-bit targets.
3004 (pr_addr): Add function to print address based on size.
3006 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3008 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3010 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3012 * gencode.c (build_mips16_operands): Correct computation of base
3013 address for extended PC relative instruction.
3015 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3017 * interp.c (mips16_entry): Add support for floating point cases.
3018 (SignalException): Pass floating point cases to mips16_entry.
3019 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3021 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3023 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3024 and then set the state to fmt_uninterpreted.
3025 (COP_SW): Temporarily set the state to fmt_word while calling
3028 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3030 * gencode.c (build_instruction): The high order may be set in the
3031 comparison flags at any ISA level, not just ISA 4.
3033 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3035 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3036 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3037 * configure.in: sinclude ../common/aclocal.m4.
3038 * configure: Regenerated.
3040 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3042 * configure: Rebuild after change to aclocal.m4.
3044 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3046 * configure configure.in Makefile.in: Update to new configure
3047 scheme which is more compatible with WinGDB builds.
3048 * configure.in: Improve comment on how to run autoconf.
3049 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3050 * Makefile.in: Use autoconf substitution to install common
3053 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3055 * gencode.c (build_instruction): Use BigEndianCPU instead of
3058 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3060 * interp.c (sim_monitor): Make output to stdout visible in
3061 wingdb's I/O log window.
3063 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3065 * support.h: Undo previous change to SIGTRAP
3068 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3070 * interp.c (store_word, load_word): New static functions.
3071 (mips16_entry): New static function.
3072 (SignalException): Look for mips16 entry and exit instructions.
3073 (simulate): Use the correct index when setting fpr_state after
3074 doing a pending move.
3076 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3078 * interp.c: Fix byte-swapping code throughout to work on
3079 both little- and big-endian hosts.
3081 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3083 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3084 with gdb/config/i386/xm-windows.h.
3086 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3088 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3089 that messes up arithmetic shifts.
3091 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3093 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3094 SIGTRAP and SIGQUIT for _WIN32.
3096 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3098 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3099 force a 64 bit multiplication.
3100 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3101 destination register is 0, since that is the default mips16 nop
3104 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3106 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3107 (build_endian_shift): Don't check proc64.
3108 (build_instruction): Always set memval to uword64. Cast op2 to
3109 uword64 when shifting it left in memory instructions. Always use
3110 the same code for stores--don't special case proc64.
3112 * gencode.c (build_mips16_operands): Fix base PC value for PC
3114 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3116 * interp.c (simJALDELAYSLOT): Define.
3117 (JALDELAYSLOT): Define.
3118 (INDELAYSLOT, INJALDELAYSLOT): Define.
3119 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3121 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3123 * interp.c (sim_open): add flush_cache as a PMON routine
3124 (sim_monitor): handle flush_cache by ignoring it
3126 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3128 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3130 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3131 (BigEndianMem): Rename to ByteSwapMem and change sense.
3132 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3133 BigEndianMem references to !ByteSwapMem.
3134 (set_endianness): New function, with prototype.
3135 (sim_open): Call set_endianness.
3136 (sim_info): Use simBE instead of BigEndianMem.
3137 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3138 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3139 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3140 ifdefs, keeping the prototype declaration.
3141 (swap_word): Rewrite correctly.
3142 (ColdReset): Delete references to CONFIG. Delete endianness related
3143 code; moved to set_endianness.
3145 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3147 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3148 * interp.c (CHECKHILO): Define away.
3149 (simSIGINT): New macro.
3150 (membank_size): Increase from 1MB to 2MB.
3151 (control_c): New function.
3152 (sim_resume): Rename parameter signal to signal_number. Add local
3153 variable prev. Call signal before and after simulate.
3154 (sim_stop_reason): Add simSIGINT support.
3155 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3157 (sim_warning): Delete call to SignalException. Do call printf_filtered
3159 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3160 a call to sim_warning.
3162 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3164 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3165 16 bit instructions.
3167 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3169 Add support for mips16 (16 bit MIPS implementation):
3170 * gencode.c (inst_type): Add mips16 instruction encoding types.
3171 (GETDATASIZEINSN): Define.
3172 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3173 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3175 (MIPS16_DECODE): New table, for mips16 instructions.
3176 (bitmap_val): New static function.
3177 (struct mips16_op): Define.
3178 (mips16_op_table): New table, for mips16 operands.
3179 (build_mips16_operands): New static function.
3180 (process_instructions): If PC is odd, decode a mips16
3181 instruction. Break out instruction handling into new
3182 build_instruction function.
3183 (build_instruction): New static function, broken out of
3184 process_instructions. Check modifiers rather than flags for SHIFT
3185 bit count and m[ft]{hi,lo} direction.
3186 (usage): Pass program name to fprintf.
3187 (main): Remove unused variable this_option_optind. Change
3188 ``*loptarg++'' to ``loptarg++''.
3189 (my_strtoul): Parenthesize && within ||.
3190 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3191 (simulate): If PC is odd, fetch a 16 bit instruction, and
3192 increment PC by 2 rather than 4.
3193 * configure.in: Add case for mips16*-*-*.
3194 * configure: Rebuild.
3196 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3198 * interp.c: Allow -t to enable tracing in standalone simulator.
3199 Fix garbage output in trace file and error messages.
3201 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3203 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3204 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3205 * configure.in: Simplify using macros in ../common/aclocal.m4.
3206 * configure: Regenerated.
3207 * tconfig.in: New file.
3209 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3211 * interp.c: Fix bugs in 64-bit port.
3212 Use ansi function declarations for msvc compiler.
3213 Initialize and test file pointer in trace code.
3214 Prevent duplicate definition of LAST_EMED_REGNUM.
3216 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3218 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3220 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3222 * interp.c (SignalException): Check for explicit terminating
3224 * gencode.c: Pass instruction value through SignalException()
3225 calls for Trap, Breakpoint and Syscall.
3227 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3229 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3230 only used on those hosts that provide it.
3231 * configure.in: Add sqrt() to list of functions to be checked for.
3232 * config.in: Re-generated.
3233 * configure: Re-generated.
3235 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3237 * gencode.c (process_instructions): Call build_endian_shift when
3238 expanding STORE RIGHT, to fix swr.
3239 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3240 clear the high bits.
3241 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3242 Fix float to int conversions to produce signed values.
3244 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3246 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3247 (process_instructions): Correct handling of nor instruction.
3248 Correct shift count for 32 bit shift instructions. Correct sign
3249 extension for arithmetic shifts to not shift the number of bits in
3250 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3251 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3253 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3254 It's OK to have a mult follow a mult. What's not OK is to have a
3255 mult follow an mfhi.
3256 (Convert): Comment out incorrect rounding code.
3258 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3260 * interp.c (sim_monitor): Improved monitor printf
3261 simulation. Tidied up simulator warnings, and added "--log" option
3262 for directing warning message output.
3263 * gencode.c: Use sim_warning() rather than WARNING macro.
3265 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3267 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3268 getopt1.o, rather than on gencode.c. Link objects together.
3269 Don't link against -liberty.
3270 (gencode.o, getopt.o, getopt1.o): New targets.
3271 * gencode.c: Include <ctype.h> and "ansidecl.h".
3272 (AND): Undefine after including "ansidecl.h".
3273 (ULONG_MAX): Define if not defined.
3274 (OP_*): Don't define macros; now defined in opcode/mips.h.
3275 (main): Call my_strtoul rather than strtoul.
3276 (my_strtoul): New static function.
3278 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3280 * gencode.c (process_instructions): Generate word64 and uword64
3281 instead of `long long' and `unsigned long long' data types.
3282 * interp.c: #include sysdep.h to get signals, and define default
3284 * (Convert): Work around for Visual-C++ compiler bug with type
3286 * support.h: Make things compile under Visual-C++ by using
3287 __int64 instead of `long long'. Change many refs to long long
3288 into word64/uword64 typedefs.
3290 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3292 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3293 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3295 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3296 (AC_PROG_INSTALL): Added.
3297 (AC_PROG_CC): Moved to before configure.host call.
3298 * configure: Rebuilt.
3300 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3302 * configure.in: Define @SIMCONF@ depending on mips target.
3303 * configure: Rebuild.
3304 * Makefile.in (run): Add @SIMCONF@ to control simulator
3306 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3307 * interp.c: Remove some debugging, provide more detailed error
3308 messages, update memory accesses to use LOADDRMASK.
3310 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3312 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3313 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3315 * configure: Rebuild.
3316 * config.in: New file, generated by autoheader.
3317 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3318 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3319 HAVE_ANINT and HAVE_AINT, as appropriate.
3320 * Makefile.in (run): Use @LIBS@ rather than -lm.
3321 (interp.o): Depend upon config.h.
3322 (Makefile): Just rebuild Makefile.
3323 (clean): Remove stamp-h.
3324 (mostlyclean): Make the same as clean, not as distclean.
3325 (config.h, stamp-h): New targets.
3327 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3329 * interp.c (ColdReset): Fix boolean test. Make all simulator
3332 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3334 * interp.c (xfer_direct_word, xfer_direct_long,
3335 swap_direct_word, swap_direct_long, xfer_big_word,
3336 xfer_big_long, xfer_little_word, xfer_little_long,
3337 swap_word,swap_long): Added.
3338 * interp.c (ColdReset): Provide function indirection to
3339 host<->simulated_target transfer routines.
3340 * interp.c (sim_store_register, sim_fetch_register): Updated to
3341 make use of indirected transfer routines.
3343 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3345 * gencode.c (process_instructions): Ensure FP ABS instruction
3347 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3348 system call support.
3350 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3352 * interp.c (sim_do_command): Complain if callback structure not
3355 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3357 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3358 support for Sun hosts.
3359 * Makefile.in (gencode): Ensure the host compiler and libraries
3360 used for cross-hosted build.
3362 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3364 * interp.c, gencode.c: Some more (TODO) tidying.
3366 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3368 * gencode.c, interp.c: Replaced explicit long long references with
3369 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3370 * support.h (SET64LO, SET64HI): Macros added.
3372 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3374 * configure: Regenerate with autoconf 2.7.
3376 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3378 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3379 * support.h: Remove superfluous "1" from #if.
3380 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3382 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3384 * interp.c (StoreFPR): Control UndefinedResult() call on
3385 WARN_RESULT manifest.
3387 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3389 * gencode.c: Tidied instruction decoding, and added FP instruction
3392 * interp.c: Added dineroIII, and BSD profiling support. Also
3393 run-time FP handling.
3395 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3397 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3398 gencode.c, interp.c, support.h: created.