3 // Simulator definition for the MIPS DSP REV 2 ASE.
4 // Copyright (C) 2007-2025 Free Software Foundation, Inc.
5 // Contributed by MIPS Technologies, Inc.
6 // Written by Chao-ying Fu (fu@mips.com).
8 // This file is part of the MIPS sim
10 // This program is free software; you can redistribute it and/or modify
11 // it under the terms of the GNU General Public License as published by
12 // the Free Software Foundation; either version 3 of the License, or
13 // (at your option) any later version.
15 // This program is distributed in the hope that it will be useful,
16 // but WITHOUT ANY WARRANTY; without even the implied warranty of
17 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 // GNU General Public License for more details.
20 // You should have received a copy of the GNU General Public License
21 // along with this program. If not, see <http://www.gnu.org/licenses/>.
24 // op: 0 = ADD, 1 = SUB
25 // sat: 0 = no saturation, 1 = saturation
26 :function:::void:do_u_ph_op:int rd, int rs, int rt, int op, int sat
31 uint32_t v1 = GPR[rs];
32 uint32_t v2 = GPR[rt];
34 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
36 h1 = (uint16_t)(v1 & 0xffff);
37 h2 = (uint16_t)(v2 & 0xffff);
39 h0 = (uint32_t)h1 + (uint32_t)h2;
41 h0 = (uint32_t)h1 - (uint32_t)h2;
42 if (op == 0 && (h0 > (uint32_t)0x0000ffff)) // ADD SAT
44 DSPCR |= DSPCR_OUFLAG4;
48 else if (op == 1 && h1 < h2) // SUB SAT
50 DSPCR |= DSPCR_OUFLAG4;
54 result |= ((uint32_t)((uint16_t)h0) << i);
56 GPR[rd] = EXTEND32 (result);
59 // op: 0 = ADD, 1 = SUB
60 // round: 0 = no rounding, 1 = rounding
61 :function:::void:do_uh_qb_op:int rd, int rs, int rt, int op, int round
66 uint32_t v1 = GPR[rs];
67 uint32_t v2 = GPR[rt];
69 for (i = 0; i < 32; i += 8, v1 >>= 8, v2 >>= 8)
71 h1 = (uint8_t)(v1 & 0xff);
72 h2 = (uint8_t)(v2 & 0xff);
74 h0 = (uint32_t)h1 + (uint32_t)h2;
76 h0 = (uint32_t)h1 - (uint32_t)h2;
81 result |= ((uint32_t)((uint8_t)h0) << i);
83 GPR[rd] = EXTEND32 (result);
86 // op: 0 = EQ, 1 = LT, 2 = LE
87 :function:::void:do_qb_cmpgdu:int rd, int rs, int rt, int op
90 uint32_t v1 = GPR[rs];
91 uint32_t v2 = GPR[rt];
95 for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8)
97 h1 = (uint8_t)(v1 & 0xff);
98 h2 = (uint8_t)(v2 & 0xff);
99 mask = ~(1 << (DSPCR_CCOND_SHIFT + j));
103 result |= ((h1 == h2) << j);
104 DSPCR |= ((h1 == h2) << (DSPCR_CCOND_SHIFT + j));
106 else if (op == 1) // LT
108 result |= ((h1 < h2) << j);
109 DSPCR |= ((h1 < h2) << (DSPCR_CCOND_SHIFT + j));
113 result |= ((h1 <= h2) << j);
114 DSPCR |= ((h1 <= h2) << (DSPCR_CCOND_SHIFT + j));
117 GPR[rd] = EXTEND32 (result);
120 // op: 0 = DPA 1 = DPS
121 :function:::void:do_w_ph_dot_product:int ac, int rs, int rt, int op
124 uint32_t v1 = GPR[rs];
125 uint32_t v2 = GPR[rt];
128 uint32_t lo = DSPLO(ac);
129 uint32_t hi = DSPHI(ac);
130 int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo);
131 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
133 h1 = (int16_t)(v1 & 0xffff);
134 h2 = (int16_t)(v2 & 0xffff);
135 result = (int32_t)h1 * (int32_t)h2;
137 prod += (int64_t)result;
139 prod -= (int64_t)result;
141 DSPLO(ac) = EXTEND32 (prod);
142 DSPHI(ac) = EXTEND32 (prod >> 32);
145 // round: 0 = no rounding, 1 = rounding
146 :function:::void:do_w_mulq:int rd, int rs, int rt, int round
148 uint32_t v1 = GPR[rs];
149 uint32_t v2 = GPR[rt];
155 if (w1 == (int32_t) 0x80000000 && w2 == (int32_t) 0x80000000)
157 DSPCR |= DSPCR_OUFLAG5;
162 prod = ((int64_t) w1 * (int64_t) w2) << 1;
164 prod += 0x0000000080000000LL;
167 result = (uint32_t) prod;
168 GPR[rd] = EXTEND32 (result);
171 // round: 0 = no rounding, 1 = rounding
172 :function:::void:do_precr_sra:int rt, int rs, int sa, int round
174 uint32_t v1 = GPR[rt];
175 uint32_t v2 = GPR[rs];
176 int32_t w1 = (int32_t) v1;
177 int32_t w2 = (int32_t) v2;
181 if (round == 1 && (w1 & (1 << (sa - 1))))
186 if (round == 1 && (w2 & (1 << (sa - 1))))
191 result = (w1 << 16) | (w2 & 0xffff);
192 GPR[rt] = EXTEND32 (result);
195 // round: 0 = no rounding, 1 = rounding
196 :function:::void:do_qb_shra:int rd, int rt, int shift, int round
200 uint32_t v1 = GPR[rt];
202 for (i = 0; i < 32; i += 8, v1 >>= 8)
204 q0 = (int8_t)(v1 & 0xff);
207 if (round == 1 && (q0 & (1 << (shift - 1))))
208 q0 = (q0 >> shift) + 1;
212 result |= ((uint32_t)((uint8_t)q0) << i);
214 GPR[rd] = EXTEND32 (result);
217 :function:::void:do_ph_shrl:int rd, int rt, int shift
221 uint32_t v1 = GPR[rt];
223 for (i = 0; i < 32; i += 16, v1 >>= 16)
225 h0 = (uint16_t)(v1 & 0xffff);
227 result |= ((uint32_t)h0 << i);
229 GPR[rd] = EXTEND32 (result);
232 // op: 0 = ADD, 1 = SUB
233 // round: 0 = no rounding, 1 = rounding
234 :function:::void:do_qh_ph_op:int rd, int rs, int rt, int op, int round
239 uint32_t v1 = GPR[rs];
240 uint32_t v2 = GPR[rt];
242 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
244 h1 = (int16_t)(v1 & 0xffff);
245 h2 = (int16_t)(v2 & 0xffff);
247 h0 = (int32_t)h1 + (int32_t)h2;
249 h0 = (int32_t)h1 - (int32_t)h2;
254 result |= ((uint32_t)((uint16_t)h0) << i);
256 GPR[rd] = EXTEND32 (result);
259 // op: 0 = ADD, 1 = SUB
260 // round: 0 = no rounding, 1 = rounding
261 :function:::void:do_qh_w_op:int rd, int rs, int rt, int op, int round
264 int32_t v1 = (int32_t)GPR[rs];
265 int32_t v2 = (int32_t)GPR[rt];
267 v0 = (int64_t)v1 + (int64_t)v2;
269 v0 = (int64_t)v1 - (int64_t)v2;
274 GPR[rd] = EXTEND32 (v0);
277 // op: 0 = DPAX, 1 = DPSX
278 :function:::void:do_x_w_ph_dot_product:int ac, int rs, int rt, int op
281 uint32_t v1 = GPR[rs];
282 uint32_t v2 = GPR[rt];
285 uint32_t lo = DSPLO(ac);
286 uint32_t hi = DSPHI(ac);
287 int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo);
288 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16)
290 h1 = (int16_t)(v1 & 0xffff);
291 h2 = (int16_t)((v2 & 0xffff0000) >> 16);
292 result = (int32_t)h1 * (int32_t)h2;
294 prod += (int64_t)result;
296 prod -= (int64_t)result;
298 DSPLO(ac) = EXTEND32 (prod);
299 DSPHI(ac) = EXTEND32 (prod >> 32);
302 // op: 0 = DPAQX, 1 = DPSQX
303 // sat: 0 = no saturation, 1 = saturation of the accumulator
304 :function:::void:do_qx_w_ph_dot_product:int ac, int rs, int rt, int op, int sat
307 uint32_t v1 = GPR[rs];
308 uint32_t v2 = GPR[rt];
311 uint32_t lo = DSPLO(ac);
312 uint32_t hi = DSPHI(ac);
313 int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo);
315 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16)
317 h1 = (int16_t)(v1 & 0xffff);
318 h2 = (int16_t)((v2 & 0xffff0000) >> 16);
319 if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000)
321 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
325 result = ((int32_t)h1 * (int32_t)h2) << 1;
326 if (op == 0) // DPAQX
327 prod += (int64_t)result;
329 prod -= (int64_t)result;
331 // Saturation on the accumulator.
334 max = (int64_t) 0x7fffffffLL;
335 min = (int64_t) 0xffffffff80000000LL;
338 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
343 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
347 DSPLO(ac) = EXTEND32 (prod);
348 DSPHI(ac) = EXTEND32 (prod >> 32);
351 011111,00000,5.RT,5.RD,00001,010010:SPECIAL3:32::ABSQ_S.QB
352 "absq_s.qb r<RD>, r<RT>"
355 do_qb_s_absq (SD_, RD, RT);
358 011111,5.RS,5.RT,5.RD,01000,010000:SPECIAL3:32::ADDU.PH
359 "addu.ph r<RD>, r<RS>, r<RT>"
362 do_u_ph_op (SD_, RD, RS, RT, 0, 0);
365 011111,5.RS,5.RT,5.RD,01100,010000:SPECIAL3:32::ADDU_S.PH
366 "addu_s.ph r<RD>, r<RS>, r<RT>"
369 do_u_ph_op (SD_, RD, RS, RT, 0, 1);
372 011111,5.RS,5.RT,5.RD,00000,011000:SPECIAL3:32::ADDUH.QB
373 "adduh.qb r<RD>, r<RS>, r<RT>"
376 do_uh_qb_op (SD_, RD, RS, RT, 0, 0);
379 011111,5.RS,5.RT,5.RD,00010,011000:SPECIAL3:32::ADDUH_R.QB
380 "adduh_r.qb r<RD>, r<RS>, r<RT>"
383 do_uh_qb_op (SD_, RD, RS, RT, 0, 1);
386 011111,5.RS,5.RT,5.SA,00000,110001:SPECIAL3:32::APPEND
387 "append r<RT>, r<RS>, <SA>"
390 do_append (SD_, RT, RS, SA);
393 011111,5.RS,5.RT,000,2.BP,10000,110001:SPECIAL3:32::BALIGN
394 "balign r<RT>, r<RS>, <BP>"
397 do_balign (SD_, RT, RS, BP);
400 011111,5.RS,5.RT,5.RD,11000,010001:SPECIAL3:32::CMPGDU.EQ.QB
401 "cmpgdu.eq.qb r<RD>, r<RS>, r<RT>"
404 do_qb_cmpgdu (SD_, RD, RS, RT, 0);
407 011111,5.RS,5.RT,5.RD,11001,010001:SPECIAL3:32::CMPGDU.LT.QB
408 "cmpgdu.lt.qb r<RD>, r<RS>, r<RT>"
411 do_qb_cmpgdu (SD_, RD, RS, RT, 1);
414 011111,5.RS,5.RT,5.RD,11010,010001:SPECIAL3:32::CMPGDU.LE.QB
415 "cmpgdu.le.qb r<RD>, r<RS>, r<RT>"
418 do_qb_cmpgdu (SD_, RD, RS, RT, 2);
421 011111,5.RS,5.RT,000,2.AC,00000,110000:SPECIAL3:32::DPA.W.PH
422 "dpa.w.ph ac<AC>, r<RS>, r<RT>"
425 do_w_ph_dot_product (SD_, AC, RS, RT, 0);
428 011111,5.RS,5.RT,000,2.AC,00001,110000:SPECIAL3:32::DPS.W.PH
429 "dps.w.ph ac<AC>, r<RS>, r<RT>"
432 do_w_ph_dot_product (SD_, AC, RS, RT, 1);
435 011111,5.RS,5.RT,5.RD,01100,011000:SPECIAL3:32::MUL.PH
436 "mul.ph r<RD>, r<RS>, r<RT>"
439 do_ph_op (SD_, RD, RS, RT, 2, 0);
442 011111,5.RS,5.RT,5.RD,01110,011000:SPECIAL3:32::MUL_S.PH
443 "mul_s.ph r<RD>, r<RS>, r<RT>"
446 do_ph_op (SD_, RD, RS, RT, 2, 1);
449 011111,5.RS,5.RT,5.RD,10111,011000:SPECIAL3:32::MULQ_RS.W
450 "mulq_rs.w r<RD>, r<RS>, r<RT>"
453 do_w_mulq (SD_, RD, RS, RT, 1);
456 011111,5.RS,5.RT,5.RD,11110,010000:SPECIAL3:32::MULQ_S.PH
457 "mulq_s.ph r<RD>, r<RS>, r<RT>"
460 do_ph_mulq (SD_, RD, RS, RT, 0);
463 011111,5.RS,5.RT,5.RD,10110,011000:SPECIAL3:32::MULQ_S.W
464 "mulq_s.w r<RD>, r<RS>, r<RT>"
467 do_w_mulq (SD_, RD, RS, RT, 0);
470 011111,5.RS,5.RT,000,2.AC,00010,110000:SPECIAL3:32::MULSA.W.PH
471 "mulsa.w.ph ac<AC>, r<RS>, r<RT>"
474 do_ph_w_mulsa (SD_, AC, RS, RT);
477 011111,5.RS,5.RT,5.RD,01101,010001:SPECIAL3:32::PRECR.QB.PH
478 "precr.qb.ph r<RD>, r<RS>, r<RT>"
481 do_ph_qb_precr (SD_, RD, RS, RT);
484 011111,5.RS,5.RT,5.SA,11110,010001:SPECIAL3:32::PRECR_SRA.PH.W
485 "precr_sra.ph.w r<RT>, r<RS>, <SA>"
488 do_precr_sra (SD_, RT, RS, SA, 0);
491 011111,5.RS,5.RT,5.SA,11111,010001:SPECIAL3:32::PRECR_SRA_R.PH.W
492 "precr_sra_r.ph.w r<RT>, r<RS>, <SA>"
495 do_precr_sra (SD_, RT, RS, SA, 1);
498 011111,5.RS,5.RT,5.SA,00001,110001:SPECIAL3:32::PREPEND
499 "prepend r<RT>, r<RS>, <SA>"
502 do_prepend (SD_, RT, RS, SA);
505 011111,00,3.SHIFT3,5.RT,5.RD,00100,010011:SPECIAL3:32::SHRA.QB
506 "shra.qb r<RD>, r<RT>, <SHIFT3>"
509 do_qb_shra (SD_, RD, RT, SHIFT3, 0);
512 011111,00,3.SHIFT3,5.RT,5.RD,00101,010011:SPECIAL3:32::SHRA_R.QB
513 "shra_r.qb r<RD>, r<RT>, <SHIFT3>"
516 do_qb_shra (SD_, RD, RT, SHIFT3, 1);
519 011111,5.RS,5.RT,5.RD,00110,010011:SPECIAL3:32::SHRAV.QB
520 "shrav.qb r<RD>, r<RT>, r<RS>"
523 do_qb_shrav (SD_, RD, RT, RS, 0);
526 011111,5.RS,5.RT,5.RD,00111,010011:SPECIAL3:32::SHRAV_R.QB
527 "shrav_r.qb r<RD>, r<RT>, r<RS>"
530 do_qb_shrav (SD_, RD, RT, RS, 1);
533 011111,0,4.SHIFT4,5.RT,5.RD,11001,010011:SPECIAL3:32::SHRL.PH
534 "shrl.ph r<RD>, r<RT>, <SHIFT4>"
537 do_ph_shrl (SD_, RD, RT, SHIFT4);
540 011111,5.RS,5.RT,5.RD,11011,010011:SPECIAL3:32::SHRLV.PH
541 "shrlv.ph r<RD>, r<RT>, r<RS>"
544 do_ph_shrlv (SD_, RD, RT, RS);
547 011111,5.RS,5.RT,5.RD,01001,010000:SPECIAL3:32::SUBU.PH
548 "subu.ph r<RD>, r<RS>, r<RT>"
551 do_u_ph_op (SD_, RD, RS, RT, 1, 0);
554 011111,5.RS,5.RT,5.RD,01101,010000:SPECIAL3:32::SUBU_S.PH
555 "subu_s.ph r<RD>, r<RS>, r<RT>"
558 do_u_ph_op (SD_, RD, RS, RT, 1, 1);
561 011111,5.RS,5.RT,5.RD,00001,011000:SPECIAL3:32::SUBUH.QB
562 "subuh.qb r<RD>, r<RS>, r<RT>"
565 do_uh_qb_op (SD_, RD, RS, RT, 1, 0);
568 011111,5.RS,5.RT,5.RD,00011,011000:SPECIAL3:32::SUBUH_R.QB
569 "subuh_r.qb r<RD>, r<RS>, r<RT>"
572 do_uh_qb_op (SD_, RD, RS, RT, 1, 1);
575 011111,5.RS,5.RT,5.RD,01000,011000:SPECIAL3:32::ADDQH.PH
576 "addqh.ph r<RD>, r<RS>, r<RT>"
579 do_qh_ph_op (SD_, RD, RS, RT, 0, 0);
582 011111,5.RS,5.RT,5.RD,01010,011000:SPECIAL3:32::ADDQH_R.PH
583 "addqh_r.ph r<RD>, r<RS>, r<RT>"
586 do_qh_ph_op (SD_, RD, RS, RT, 0, 1);
589 011111,5.RS,5.RT,5.RD,10000,011000:SPECIAL3:32::ADDQH.W
590 "addqh.w r<RD>, r<RS>, r<RT>"
593 do_qh_w_op (SD_, RD, RS, RT, 0, 0);
596 011111,5.RS,5.RT,5.RD,10010,011000:SPECIAL3:32::ADDQH_R.W
597 "addqh_r.w r<RD>, r<RS>, r<RT>"
600 do_qh_w_op (SD_, RD, RS, RT, 0, 1);
603 011111,5.RS,5.RT,5.RD,01001,011000:SPECIAL3:32::SUBQH.PH
604 "subqh.ph r<RD>, r<RS>, r<RT>"
607 do_qh_ph_op (SD_, RD, RS, RT, 1, 0);
610 011111,5.RS,5.RT,5.RD,01011,011000:SPECIAL3:32::SUBQH_R.PH
611 "subqh_r.ph r<RD>, r<RS>, r<RT>"
614 do_qh_ph_op (SD_, RD, RS, RT, 1, 1);
617 011111,5.RS,5.RT,5.RD,10001,011000:SPECIAL3:32::SUBQH.W
618 "subqh.w r<RD>, r<RS>, r<RT>"
621 do_qh_w_op (SD_, RD, RS, RT, 1, 0);
624 011111,5.RS,5.RT,5.RD,10011,011000:SPECIAL3:32::SUBQH_R.W
625 "subqh_r.w r<RD>, r<RS>, r<RT>"
628 do_qh_w_op (SD_, RD, RS, RT, 1, 1);
631 011111,5.RS,5.RT,000,2.AC,01000,110000:SPECIAL3:32::DPAX.W.PH
632 "dpax.w.ph ac<AC>, r<RS>, r<RT>"
635 do_x_w_ph_dot_product (SD_, AC, RS, RT, 0);
638 011111,5.RS,5.RT,000,2.AC,01001,110000:SPECIAL3:32::DPSX.W.PH
639 "dpsx.w.ph ac<AC>, r<RS>, r<RT>"
642 do_x_w_ph_dot_product (SD_, AC, RS, RT, 1);
645 011111,5.RS,5.RT,000,2.AC,11000,110000:SPECIAL3:32::DPAQX_S.W.PH
646 "dpaqx_s.w.ph ac<AC>, r<RS>, r<RT>"
649 do_qx_w_ph_dot_product (SD_, AC, RS, RT, 0, 0);
652 011111,5.RS,5.RT,000,2.AC,11010,110000:SPECIAL3:32::DPAQX_SA.W.PH
653 "dpaqx_sa.w.ph ac<AC>, r<RS>, r<RT>"
656 do_qx_w_ph_dot_product (SD_, AC, RS, RT, 0, 1);
659 011111,5.RS,5.RT,000,2.AC,11001,110000:SPECIAL3:32::DPSQX_S.W.PH
660 "dpsqx_s.w.ph ac<AC>, r<RS>, r<RT>"
663 do_qx_w_ph_dot_product (SD_, AC, RS, RT, 1, 0);
666 011111,5.RS,5.RT,000,2.AC,11011,110000:SPECIAL3:32::DPSQX_SA.W.PH
667 "dpsqx_sa.w.ph ac<AC>, r<RS>, r<RT>"
670 do_qx_w_ph_dot_product (SD_, AC, RS, RT, 1, 1);