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[thirdparty/binutils-gdb.git] / sim / mips / interp.c
1 /*> interp.c <*/
2 /* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 NOTEs:
17
18 The IDT monitor (found on the VR4300 board), seems to lie about
19 register contents. It seems to treat the registers as sign-extended
20 32-bit values. This cause *REAL* problems when single-stepping 64-bit
21 code on the hardware.
22
23 */
24
25 #include "config.h"
26 #include "bfd.h"
27 #include "sim-main.h"
28 #include "sim-utils.h"
29 #include "sim-options.h"
30 #include "sim-assert.h"
31 #include "sim-hw.h"
32
33 #include "itable.h"
34
35
36 #include "config.h"
37
38 #include <stdio.h>
39 #include <stdarg.h>
40 #include <ansidecl.h>
41 #include <ctype.h>
42 #include <limits.h>
43 #include <math.h>
44 #ifdef HAVE_STDLIB_H
45 #include <stdlib.h>
46 #endif
47 #ifdef HAVE_STRING_H
48 #include <string.h>
49 #else
50 #ifdef HAVE_STRINGS_H
51 #include <strings.h>
52 #endif
53 #endif
54
55 #include "getopt.h"
56 #include "libiberty.h"
57 #include "bfd.h"
58 #include "gdb/callback.h" /* GDB simulator callback interface */
59 #include "gdb/remote-sim.h" /* GDB simulator interface */
60
61 char* pr_addr (SIM_ADDR addr);
62 char* pr_uword64 (uword64 addr);
63
64
65 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
66 #define CPU cpu
67 #define SD sd
68
69
70 /* The following reserved instruction value is used when a simulator
71 trap is required. NOTE: Care must be taken, since this value may be
72 used in later revisions of the MIPS ISA. */
73
74 #define RSVD_INSTRUCTION (0x00000039)
75 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
76
77 #define RSVD_INSTRUCTION_ARG_SHIFT 6
78 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
79
80
81 /* Bits in the Debug register */
82 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
83 #define Debug_DM 0x40000000 /* Debug Mode */
84 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
85
86 /*---------------------------------------------------------------------------*/
87 /*-- GDB simulator interface ------------------------------------------------*/
88 /*---------------------------------------------------------------------------*/
89
90 static void ColdReset (SIM_DESC sd);
91
92 /*---------------------------------------------------------------------------*/
93
94
95
96 #define DELAYSLOT() {\
97 if (STATE & simDELAYSLOT)\
98 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
99 STATE |= simDELAYSLOT;\
100 }
101
102 #define JALDELAYSLOT() {\
103 DELAYSLOT ();\
104 STATE |= simJALDELAYSLOT;\
105 }
106
107 #define NULLIFY() {\
108 STATE &= ~simDELAYSLOT;\
109 STATE |= simSKIPNEXT;\
110 }
111
112 #define CANCELDELAYSLOT() {\
113 DSSTATE = 0;\
114 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
115 }
116
117 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
118 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
119
120 /* Note that the monitor code essentially assumes this layout of memory.
121 If you change these, change the monitor code, too. */
122 /* FIXME Currently addresses are truncated to 32-bits, see
123 mips/sim-main.c:address_translation(). If that changes, then these
124 values will need to be extended, and tested for more carefully. */
125 #define K0BASE (0x80000000)
126 #define K0SIZE (0x20000000)
127 #define K1BASE (0xA0000000)
128 #define K1SIZE (0x20000000)
129
130 /* Simple run-time monitor support.
131
132 We emulate the monitor by placing magic reserved instructions at
133 the monitor's entry points; when we hit these instructions, instead
134 of raising an exception (as we would normally), we look at the
135 instruction and perform the appropriate monitory operation.
136
137 `*_monitor_base' are the physical addresses at which the corresponding
138 monitor vectors are located. `0' means none. By default,
139 install all three.
140 The RSVD_INSTRUCTION... macros specify the magic instructions we
141 use at the monitor entry points. */
142 static int firmware_option_p = 0;
143 static SIM_ADDR idt_monitor_base = 0xBFC00000;
144 static SIM_ADDR pmon_monitor_base = 0xBFC00500;
145 static SIM_ADDR lsipmon_monitor_base = 0xBFC00200;
146
147 static SIM_RC sim_firmware_command (SIM_DESC sd, char* arg);
148
149 #define MEM_SIZE (8 << 20) /* 8 MBytes */
150
151
152 #if WITH_TRACE_ANY_P
153 static char *tracefile = "trace.din"; /* default filename for trace log */
154 FILE *tracefh = NULL;
155 static void open_trace (SIM_DESC sd);
156 #else
157 #define open_trace(sd)
158 #endif
159
160 static const char * get_insn_name (sim_cpu *, int);
161
162 /* simulation target board. NULL=canonical */
163 static char* board = NULL;
164
165
166 static DECLARE_OPTION_HANDLER (mips_option_handler);
167
168 enum {
169 OPTION_DINERO_TRACE = OPTION_START,
170 OPTION_DINERO_FILE,
171 OPTION_FIRMWARE,
172 OPTION_INFO_MEMORY,
173 OPTION_BOARD
174 };
175
176 static int display_mem_info = 0;
177
178 static SIM_RC
179 mips_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt, char *arg,
180 int is_command)
181 {
182 int cpu_nr;
183 switch (opt)
184 {
185 case OPTION_DINERO_TRACE: /* ??? */
186 #if WITH_TRACE_ANY_P
187 /* Eventually the simTRACE flag could be treated as a toggle, to
188 allow external control of the program points being traced
189 (i.e. only from main onwards, excluding the run-time setup,
190 etc.). */
191 for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
192 {
193 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
194 if (arg == NULL)
195 STATE |= simTRACE;
196 else if (strcmp (arg, "yes") == 0)
197 STATE |= simTRACE;
198 else if (strcmp (arg, "no") == 0)
199 STATE &= ~simTRACE;
200 else if (strcmp (arg, "on") == 0)
201 STATE |= simTRACE;
202 else if (strcmp (arg, "off") == 0)
203 STATE &= ~simTRACE;
204 else
205 {
206 fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg);
207 return SIM_RC_FAIL;
208 }
209 }
210 return SIM_RC_OK;
211 #else /* !WITH_TRACE_ANY_P */
212 fprintf(stderr,"\
213 Simulator constructed without dinero tracing support (for performance).\n\
214 Re-compile simulator with \"-DWITH_TRACE_ANY_P\" to enable this option.\n");
215 return SIM_RC_FAIL;
216 #endif /* !WITH_TRACE_ANY_P */
217
218 case OPTION_DINERO_FILE:
219 #if WITH_TRACE_ANY_P
220 if (optarg != NULL) {
221 char *tmp;
222 tmp = (char *)malloc(strlen(optarg) + 1);
223 if (tmp == NULL)
224 {
225 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
226 return SIM_RC_FAIL;
227 }
228 else {
229 strcpy(tmp,optarg);
230 tracefile = tmp;
231 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
232 }
233 }
234 #endif /* WITH_TRACE_ANY_P */
235 return SIM_RC_OK;
236
237 case OPTION_FIRMWARE:
238 return sim_firmware_command (sd, arg);
239
240 case OPTION_BOARD:
241 {
242 if (arg)
243 {
244 board = zalloc(strlen(arg) + 1);
245 strcpy(board, arg);
246 }
247 return SIM_RC_OK;
248 }
249
250 case OPTION_INFO_MEMORY:
251 display_mem_info = 1;
252 break;
253 }
254
255 return SIM_RC_OK;
256 }
257
258
259 static const OPTION mips_options[] =
260 {
261 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
262 '\0', "on|off", "Enable dinero tracing",
263 mips_option_handler },
264 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
265 '\0', "FILE", "Write dinero trace to FILE",
266 mips_option_handler },
267 { {"firmware", required_argument, NULL, OPTION_FIRMWARE},
268 '\0', "[idt|pmon|lsipmon|none][@ADDRESS]", "Emulate ROM monitor",
269 mips_option_handler },
270 { {"board", required_argument, NULL, OPTION_BOARD},
271 '\0', "none" /* rely on compile-time string concatenation for other options */
272
273 #define BOARD_JMR3904 "jmr3904"
274 "|" BOARD_JMR3904
275 #define BOARD_JMR3904_PAL "jmr3904pal"
276 "|" BOARD_JMR3904_PAL
277 #define BOARD_JMR3904_DEBUG "jmr3904debug"
278 "|" BOARD_JMR3904_DEBUG
279 #define BOARD_BSP "bsp"
280 "|" BOARD_BSP
281
282 , "Customize simulation for a particular board.", mips_option_handler },
283
284 /* These next two options have the same names as ones found in the
285 memory_options[] array in common/sim-memopt.c. This is because
286 the intention is to provide an alternative handler for those two
287 options. We need an alternative handler because the memory
288 regions are not set up until after the command line arguments
289 have been parsed, and so we cannot display the memory info whilst
290 processing the command line. There is a hack in sim_open to
291 remove these handlers when we want the real --memory-info option
292 to work. */
293 { { "info-memory", no_argument, NULL, OPTION_INFO_MEMORY },
294 '\0', NULL, "List configured memory regions", mips_option_handler },
295 { { "memory-info", no_argument, NULL, OPTION_INFO_MEMORY },
296 '\0', NULL, NULL, mips_option_handler },
297
298 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
299 };
300
301
302 int interrupt_pending;
303
304 void
305 interrupt_event (SIM_DESC sd, void *data)
306 {
307 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
308 address_word cia = CPU_PC_GET (cpu);
309 if (SR & status_IE)
310 {
311 interrupt_pending = 0;
312 SignalExceptionInterrupt (1); /* interrupt "1" */
313 }
314 else if (!interrupt_pending)
315 sim_events_schedule (sd, 1, interrupt_event, data);
316 }
317
318
319 /*---------------------------------------------------------------------------*/
320 /*-- Device registration hook -----------------------------------------------*/
321 /*---------------------------------------------------------------------------*/
322 static void device_init(SIM_DESC sd) {
323 #ifdef DEVICE_INIT
324 extern void register_devices(SIM_DESC);
325 register_devices(sd);
326 #endif
327 }
328
329 /*---------------------------------------------------------------------------*/
330 /*-- GDB simulator interface ------------------------------------------------*/
331 /*---------------------------------------------------------------------------*/
332
333 static sim_cia
334 mips_pc_get (sim_cpu *cpu)
335 {
336 return PC;
337 }
338
339 static void
340 mips_pc_set (sim_cpu *cpu, sim_cia pc)
341 {
342 PC = pc;
343 }
344
345 static int mips_reg_fetch (SIM_CPU *, int, unsigned char *, int);
346 static int mips_reg_store (SIM_CPU *, int, unsigned char *, int);
347
348 SIM_DESC
349 sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
350 {
351 int i;
352 SIM_DESC sd = sim_state_alloc (kind, cb);
353 sim_cpu *cpu;
354
355 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
356
357 /* The cpu data is kept in a separately allocated chunk of memory. */
358 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
359 return 0;
360
361 cpu = STATE_CPU (sd, 0); /* FIXME */
362
363 /* FIXME: watchpoints code shouldn't need this */
364 STATE_WATCHPOINTS (sd)->pc = &(PC);
365 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
366 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
367
368 /* Initialize the mechanism for doing insn profiling. */
369 CPU_INSN_NAME (cpu) = get_insn_name;
370 CPU_MAX_INSNS (cpu) = nr_itable_entries;
371
372 STATE = 0;
373
374 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
375 return 0;
376 sim_add_option_table (sd, NULL, mips_options);
377
378
379 /* The parser will print an error message for us, so we silently return. */
380 if (sim_parse_args (sd, argv) != SIM_RC_OK)
381 {
382 /* Uninstall the modules to avoid memory leaks,
383 file descriptor leaks, etc. */
384 sim_module_uninstall (sd);
385 return 0;
386 }
387
388 /* handle board-specific memory maps */
389 if (board == NULL)
390 {
391 /* Allocate core managed memory */
392 sim_memopt *entry, *match = NULL;
393 address_word mem_size = 0;
394 int mapped = 0;
395
396 /* For compatibility with the old code - under this (at level one)
397 are the kernel spaces K0 & K1. Both of these map to a single
398 smaller sub region */
399 sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
400
401 /* Look for largest memory region defined on command-line at
402 phys address 0. */
403 for (entry = STATE_MEMOPT (sd); entry != NULL; entry = entry->next)
404 {
405 /* If we find an entry at address 0, then we will end up
406 allocating a new buffer in the "memory alias" command
407 below. The region at address 0 will be deleted. */
408 address_word size = (entry->modulo != 0
409 ? entry->modulo : entry->nr_bytes);
410 if (entry->addr == 0
411 && (!match || entry->level < match->level))
412 match = entry;
413 else if (entry->addr == K0BASE || entry->addr == K1BASE)
414 mapped = 1;
415 else
416 {
417 sim_memopt *alias;
418 for (alias = entry->alias; alias != NULL; alias = alias->next)
419 {
420 if (alias->addr == 0
421 && (!match || entry->level < match->level))
422 match = entry;
423 else if (alias->addr == K0BASE || alias->addr == K1BASE)
424 mapped = 1;
425 }
426 }
427 }
428
429 if (!mapped)
430 {
431 if (match)
432 {
433 /* Get existing memory region size. */
434 mem_size = (match->modulo != 0
435 ? match->modulo : match->nr_bytes);
436 /* Delete old region. */
437 sim_do_commandf (sd, "memory delete %d:0x%lx@%d",
438 match->space, match->addr, match->level);
439 }
440 else if (mem_size == 0)
441 mem_size = MEM_SIZE;
442 /* Limit to KSEG1 size (512MB) */
443 if (mem_size > K1SIZE)
444 mem_size = K1SIZE;
445 /* memory alias K1BASE@1,K1SIZE%MEMSIZE,K0BASE */
446 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
447 K1BASE, K1SIZE, (long)mem_size, K0BASE);
448 }
449
450 device_init(sd);
451 }
452 else if (board != NULL
453 && (strcmp(board, BOARD_BSP) == 0))
454 {
455 int i;
456
457 STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
458
459 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
460 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
461 0x9FC00000,
462 4 * 1024 * 1024, /* 4 MB */
463 0xBFC00000);
464
465 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
466 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
467 0x80000000,
468 4 * 1024 * 1024, /* 4 MB */
469 0xA0000000);
470
471 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
472 for (i=0; i<8; i++) /* 32 MB total */
473 {
474 unsigned size = 4 * 1024 * 1024; /* 4 MB */
475 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
476 0x88000000 + (i * size),
477 size,
478 0xA8000000 + (i * size));
479 }
480 }
481 #if (WITH_HW)
482 else if (board != NULL
483 && (strcmp(board, BOARD_JMR3904) == 0 ||
484 strcmp(board, BOARD_JMR3904_PAL) == 0 ||
485 strcmp(board, BOARD_JMR3904_DEBUG) == 0))
486 {
487 /* match VIRTUAL memory layout of JMR-TX3904 board */
488 int i;
489
490 /* --- disable monitor unless forced on by user --- */
491
492 if (! firmware_option_p)
493 {
494 idt_monitor_base = 0;
495 pmon_monitor_base = 0;
496 lsipmon_monitor_base = 0;
497 }
498
499 /* --- environment --- */
500
501 STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
502
503 /* --- memory --- */
504
505 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
506 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
507 0x9FC00000,
508 4 * 1024 * 1024, /* 4 MB */
509 0xBFC00000);
510
511 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
512 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
513 0x80000000,
514 4 * 1024 * 1024, /* 4 MB */
515 0xA0000000);
516
517 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
518 for (i=0; i<8; i++) /* 32 MB total */
519 {
520 unsigned size = 4 * 1024 * 1024; /* 4 MB */
521 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
522 0x88000000 + (i * size),
523 size,
524 0xA8000000 + (i * size));
525 }
526
527 /* Dummy memory regions for unsimulated devices - sorted by address */
528
529 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB1000000, 0x400); /* ISA I/O */
530 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */
531 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2500000, 0x004); /* LED/switch */
532 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2700000, 0x004); /* RTC */
533 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB3C00000, 0x004); /* RTC */
534 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF8000, 0x900); /* DRAMC */
535 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
536 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFE000, 0x01c); /* EBIF */
537 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
538
539
540 /* --- simulated devices --- */
541 sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
542 sim_hw_parse (sd, "/tx3904cpu");
543 sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
544 sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
545 sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
546 sim_hw_parse (sd, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
547 {
548 /* FIXME: poking at dv-sockser internals, use tcp backend if
549 --sockser_addr option was given.*/
550 extern char* sockser_addr;
551 if(sockser_addr == NULL)
552 sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend stdio");
553 else
554 sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend tcp");
555 }
556 sim_hw_parse (sd, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
557 sim_hw_parse (sd, "/tx3904sio@0xfffff400/backend stdio");
558
559 /* -- device connections --- */
560 sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu");
561 sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
562 sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
563 sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
564 sim_hw_parse (sd, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
565 sim_hw_parse (sd, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
566
567 /* add PAL timer & I/O module */
568 if(! strcmp(board, BOARD_JMR3904_PAL))
569 {
570 /* the device */
571 sim_hw_parse (sd, "/pal@0xffff0000");
572 sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64");
573
574 /* wire up interrupt ports to irc */
575 sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
576 sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc");
577 sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
578 }
579
580 if(! strcmp(board, BOARD_JMR3904_DEBUG))
581 {
582 /* -- DEBUG: glue interrupt generators --- */
583 sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
584 sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc");
585 sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc");
586 sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc");
587 sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc");
588 sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc");
589 sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc");
590 sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc");
591 sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc");
592 sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
593 sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
594 sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
595 sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
596 sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
597 sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
598 sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
599 sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
600 sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
601 sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
602 }
603
604 device_init(sd);
605 }
606 #endif
607
608 if (display_mem_info)
609 {
610 struct option_list * ol;
611 struct option_list * prev;
612
613 /* This is a hack. We want to execute the real --memory-info command
614 line switch which is handled in common/sim-memopts.c, not the
615 override we have defined in this file. So we remove the
616 mips_options array from the state options list. This is safe
617 because we have now processed all of the command line. */
618 for (ol = STATE_OPTIONS (sd), prev = NULL;
619 ol != NULL;
620 prev = ol, ol = ol->next)
621 if (ol->options == mips_options)
622 break;
623
624 SIM_ASSERT (ol != NULL);
625
626 if (prev == NULL)
627 STATE_OPTIONS (sd) = ol->next;
628 else
629 prev->next = ol->next;
630
631 sim_do_commandf (sd, "memory-info");
632 }
633
634 /* check for/establish the a reference program image */
635 if (sim_analyze_program (sd,
636 (STATE_PROG_ARGV (sd) != NULL
637 ? *STATE_PROG_ARGV (sd)
638 : NULL),
639 abfd) != SIM_RC_OK)
640 {
641 sim_module_uninstall (sd);
642 return 0;
643 }
644
645 /* Configure/verify the target byte order and other runtime
646 configuration options */
647 if (sim_config (sd) != SIM_RC_OK)
648 {
649 sim_module_uninstall (sd);
650 return 0;
651 }
652
653 if (sim_post_argv_init (sd) != SIM_RC_OK)
654 {
655 /* Uninstall the modules to avoid memory leaks,
656 file descriptor leaks, etc. */
657 sim_module_uninstall (sd);
658 return 0;
659 }
660
661 /* verify assumptions the simulator made about the host type system.
662 This macro does not return if there is a problem */
663 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
664 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
665
666 /* This is NASTY, in that we are assuming the size of specific
667 registers: */
668 {
669 int rn;
670 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
671 {
672 if (rn < 32)
673 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
674 else if ((rn >= FGR_BASE) && (rn < (FGR_BASE + NR_FGR)))
675 cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
676 else if ((rn >= 33) && (rn <= 37))
677 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
678 else if ((rn == SRIDX)
679 || (rn == FCR0IDX)
680 || (rn == FCR31IDX)
681 || ((rn >= 72) && (rn <= 89)))
682 cpu->register_widths[rn] = 32;
683 else
684 cpu->register_widths[rn] = 0;
685 }
686
687
688 }
689
690 if (STATE & simTRACE)
691 open_trace(sd);
692
693 /*
694 sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n",
695 idt_monitor_base,
696 pmon_monitor_base,
697 lsipmon_monitor_base);
698 */
699
700 /* Write the monitor trap address handlers into the monitor (eeprom)
701 address space. This can only be done once the target endianness
702 has been determined. */
703 if (idt_monitor_base != 0)
704 {
705 unsigned loop;
706 unsigned idt_monitor_size = 1 << 11;
707
708 /* the default monitor region */
709 sim_do_commandf (sd, "memory region 0x%x,0x%x",
710 idt_monitor_base, idt_monitor_size);
711
712 /* Entry into the IDT monitor is via fixed address vectors, and
713 not using machine instructions. To avoid clashing with use of
714 the MIPS TRAP system, we place our own (simulator specific)
715 "undefined" instructions into the relevant vector slots. */
716 for (loop = 0; (loop < idt_monitor_size); loop += 4)
717 {
718 address_word vaddr = (idt_monitor_base + loop);
719 unsigned32 insn = (RSVD_INSTRUCTION |
720 (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK)
721 << RSVD_INSTRUCTION_ARG_SHIFT));
722 H2T (insn);
723 sim_write (sd, vaddr, (unsigned char *)&insn, sizeof (insn));
724 }
725 }
726
727 if ((pmon_monitor_base != 0) || (lsipmon_monitor_base != 0))
728 {
729 /* The PMON monitor uses the same address space, but rather than
730 branching into it the address of a routine is loaded. We can
731 cheat for the moment, and direct the PMON routine to IDT style
732 instructions within the monitor space. This relies on the IDT
733 monitor not using the locations from 0xBFC00500 onwards as its
734 entry points.*/
735 unsigned loop;
736 for (loop = 0; (loop < 24); loop++)
737 {
738 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
739 switch (loop)
740 {
741 case 0: /* read */
742 value = 7;
743 break;
744 case 1: /* write */
745 value = 8;
746 break;
747 case 2: /* open */
748 value = 6;
749 break;
750 case 3: /* close */
751 value = 10;
752 break;
753 case 5: /* printf */
754 value = ((0x500 - 16) / 8); /* not an IDT reason code */
755 break;
756 case 8: /* cliexit */
757 value = 17;
758 break;
759 case 11: /* flush_cache */
760 value = 28;
761 break;
762 }
763
764 SIM_ASSERT (idt_monitor_base != 0);
765 value = ((unsigned int) idt_monitor_base + (value * 8));
766 H2T (value);
767
768 if (pmon_monitor_base != 0)
769 {
770 address_word vaddr = (pmon_monitor_base + (loop * 4));
771 sim_write (sd, vaddr, (unsigned char *)&value, sizeof (value));
772 }
773
774 if (lsipmon_monitor_base != 0)
775 {
776 address_word vaddr = (lsipmon_monitor_base + (loop * 4));
777 sim_write (sd, vaddr, (unsigned char *)&value, sizeof (value));
778 }
779 }
780
781 /* Write an abort sequence into the TRAP (common) exception vector
782 addresses. This is to catch code executing a TRAP (et.al.)
783 instruction without installing a trap handler. */
784 if ((idt_monitor_base != 0) ||
785 (pmon_monitor_base != 0) ||
786 (lsipmon_monitor_base != 0))
787 {
788 unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
789 HALT_INSTRUCTION /* BREAK */ };
790 H2T (halt[0]);
791 H2T (halt[1]);
792 sim_write (sd, 0x80000000, (unsigned char *) halt, sizeof (halt));
793 sim_write (sd, 0x80000180, (unsigned char *) halt, sizeof (halt));
794 sim_write (sd, 0x80000200, (unsigned char *) halt, sizeof (halt));
795 /* XXX: Write here unconditionally? */
796 sim_write (sd, 0xBFC00200, (unsigned char *) halt, sizeof (halt));
797 sim_write (sd, 0xBFC00380, (unsigned char *) halt, sizeof (halt));
798 sim_write (sd, 0xBFC00400, (unsigned char *) halt, sizeof (halt));
799 }
800 }
801
802 /* CPU specific initialization. */
803 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
804 {
805 SIM_CPU *cpu = STATE_CPU (sd, i);
806
807 CPU_REG_FETCH (cpu) = mips_reg_fetch;
808 CPU_REG_STORE (cpu) = mips_reg_store;
809 CPU_PC_FETCH (cpu) = mips_pc_get;
810 CPU_PC_STORE (cpu) = mips_pc_set;
811 }
812
813 return sd;
814 }
815
816 #if WITH_TRACE_ANY_P
817 static void
818 open_trace (SIM_DESC sd)
819 {
820 tracefh = fopen(tracefile,"wb+");
821 if (tracefh == NULL)
822 {
823 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
824 tracefh = stderr;
825 }
826 }
827 #endif
828
829 /* Return name of an insn, used by insn profiling. */
830 static const char *
831 get_insn_name (sim_cpu *cpu, int i)
832 {
833 return itable[i].name;
834 }
835
836 void
837 mips_sim_close (SIM_DESC sd, int quitting)
838 {
839 #if WITH_TRACE_ANY_P
840 if (tracefh != NULL && tracefh != stderr)
841 fclose(tracefh);
842 tracefh = NULL;
843 #endif
844 }
845
846 static int
847 mips_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
848 {
849 /* NOTE: gdb (the client) stores registers in target byte order
850 while the simulator uses host byte order */
851
852 /* Unfortunately this suffers from the same problem as the register
853 numbering one. We need to know what the width of each logical
854 register number is for the architecture being simulated. */
855
856 if (cpu->register_widths[rn] == 0)
857 {
858 sim_io_eprintf (CPU_STATE (cpu), "Invalid register width for %d (register store ignored)\n", rn);
859 return 0;
860 }
861
862 if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
863 {
864 cpu->fpr_state[rn - FGR_BASE] = fmt_uninterpreted;
865 if (cpu->register_widths[rn] == 32)
866 {
867 if (length == 8)
868 {
869 cpu->fgr[rn - FGR_BASE] =
870 (unsigned32) T2H_8 (*(unsigned64*)memory);
871 return 8;
872 }
873 else
874 {
875 cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
876 return 4;
877 }
878 }
879 else
880 {
881 if (length == 8)
882 {
883 cpu->fgr[rn - FGR_BASE] = T2H_8 (*(unsigned64*)memory);
884 return 8;
885 }
886 else
887 {
888 cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
889 return 4;
890 }
891 }
892 }
893
894 if (cpu->register_widths[rn] == 32)
895 {
896 if (length == 8)
897 {
898 cpu->registers[rn] =
899 (unsigned32) T2H_8 (*(unsigned64*)memory);
900 return 8;
901 }
902 else
903 {
904 cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
905 return 4;
906 }
907 }
908 else
909 {
910 if (length == 8)
911 {
912 cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
913 return 8;
914 }
915 else
916 {
917 cpu->registers[rn] = (signed32) T2H_4(*(unsigned32*)memory);
918 return 4;
919 }
920 }
921
922 return 0;
923 }
924
925 static int
926 mips_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
927 {
928 /* NOTE: gdb (the client) stores registers in target byte order
929 while the simulator uses host byte order */
930
931 if (cpu->register_widths[rn] == 0)
932 {
933 sim_io_eprintf (CPU_STATE (cpu), "Invalid register width for %d (register fetch ignored)\n", rn);
934 return 0;
935 }
936
937 /* Any floating point register */
938 if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
939 {
940 if (cpu->register_widths[rn] == 32)
941 {
942 if (length == 8)
943 {
944 *(unsigned64*)memory =
945 H2T_8 ((unsigned32) (cpu->fgr[rn - FGR_BASE]));
946 return 8;
947 }
948 else
949 {
950 *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]);
951 return 4;
952 }
953 }
954 else
955 {
956 if (length == 8)
957 {
958 *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]);
959 return 8;
960 }
961 else
962 {
963 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->fgr[rn - FGR_BASE]));
964 return 4;
965 }
966 }
967 }
968
969 if (cpu->register_widths[rn] == 32)
970 {
971 if (length == 8)
972 {
973 *(unsigned64*)memory =
974 H2T_8 ((unsigned32) (cpu->registers[rn]));
975 return 8;
976 }
977 else
978 {
979 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
980 return 4;
981 }
982 }
983 else
984 {
985 if (length == 8)
986 {
987 *(unsigned64*)memory =
988 H2T_8 ((unsigned64) (cpu->registers[rn]));
989 return 8;
990 }
991 else
992 {
993 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
994 return 4;
995 }
996 }
997
998 return 0;
999 }
1000
1001 SIM_RC
1002 sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
1003 {
1004
1005 #ifdef DEBUG
1006 #if 0 /* FIXME: doesn't compile */
1007 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1008 pr_addr(PC));
1009 #endif
1010 #endif /* DEBUG */
1011
1012 ColdReset(sd);
1013
1014 if (abfd != NULL)
1015 {
1016 /* override PC value set by ColdReset () */
1017 int cpu_nr;
1018 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1019 {
1020 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1021 CPU_PC_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
1022 }
1023 }
1024
1025 #if 0 /* def DEBUG */
1026 if (argv || env)
1027 {
1028 /* We should really place the argv slot values into the argument
1029 registers, and onto the stack as required. However, this
1030 assumes that we have a stack defined, which is not
1031 necessarily true at the moment. */
1032 char **cptr;
1033 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
1034 for (cptr = argv; (cptr && *cptr); cptr++)
1035 printf("DBG: arg \"%s\"\n",*cptr);
1036 }
1037 #endif /* DEBUG */
1038
1039 return SIM_RC_OK;
1040 }
1041
1042 /*---------------------------------------------------------------------------*/
1043 /*-- Private simulator support interface ------------------------------------*/
1044 /*---------------------------------------------------------------------------*/
1045
1046 /* Read a null terminated string from memory, return in a buffer */
1047 static char *
1048 fetch_str (SIM_DESC sd,
1049 address_word addr)
1050 {
1051 char *buf;
1052 int nr = 0;
1053 unsigned char null;
1054 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
1055 nr++;
1056 buf = NZALLOC (char, nr + 1);
1057 sim_read (sd, addr, (unsigned char *)buf, nr);
1058 return buf;
1059 }
1060
1061
1062 /* Implements the "sim firmware" command:
1063 sim firmware NAME[@ADDRESS] --- emulate ROM monitor named NAME.
1064 NAME can be idt, pmon, or lsipmon. If omitted, ADDRESS
1065 defaults to the normal address for that monitor.
1066 sim firmware none --- don't emulate any ROM monitor. Useful
1067 if you need a clean address space. */
1068 static SIM_RC
1069 sim_firmware_command (SIM_DESC sd, char *arg)
1070 {
1071 int address_present = 0;
1072 SIM_ADDR address;
1073
1074 /* Signal occurrence of this option. */
1075 firmware_option_p = 1;
1076
1077 /* Parse out the address, if present. */
1078 {
1079 char *p = strchr (arg, '@');
1080 if (p)
1081 {
1082 char *q;
1083 address_present = 1;
1084 p ++; /* skip over @ */
1085
1086 address = strtoul (p, &q, 0);
1087 if (*q != '\0')
1088 {
1089 sim_io_printf (sd, "Invalid address given to the"
1090 "`sim firmware NAME@ADDRESS' command: %s\n",
1091 p);
1092 return SIM_RC_FAIL;
1093 }
1094 }
1095 else
1096 {
1097 address_present = 0;
1098 address = -1; /* Dummy value. */
1099 }
1100 }
1101
1102 if (! strncmp (arg, "idt", 3))
1103 {
1104 idt_monitor_base = address_present ? address : 0xBFC00000;
1105 pmon_monitor_base = 0;
1106 lsipmon_monitor_base = 0;
1107 }
1108 else if (! strncmp (arg, "pmon", 4))
1109 {
1110 /* pmon uses indirect calls. Hook into implied idt. */
1111 pmon_monitor_base = address_present ? address : 0xBFC00500;
1112 idt_monitor_base = pmon_monitor_base - 0x500;
1113 lsipmon_monitor_base = 0;
1114 }
1115 else if (! strncmp (arg, "lsipmon", 7))
1116 {
1117 /* lsipmon uses indirect calls. Hook into implied idt. */
1118 pmon_monitor_base = 0;
1119 lsipmon_monitor_base = address_present ? address : 0xBFC00200;
1120 idt_monitor_base = lsipmon_monitor_base - 0x200;
1121 }
1122 else if (! strncmp (arg, "none", 4))
1123 {
1124 if (address_present)
1125 {
1126 sim_io_printf (sd,
1127 "The `sim firmware none' command does "
1128 "not take an `ADDRESS' argument.\n");
1129 return SIM_RC_FAIL;
1130 }
1131 idt_monitor_base = 0;
1132 pmon_monitor_base = 0;
1133 lsipmon_monitor_base = 0;
1134 }
1135 else
1136 {
1137 sim_io_printf (sd, "\
1138 Unrecognized name given to the `sim firmware NAME' command: %s\n\
1139 Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.\n",
1140 arg);
1141 return SIM_RC_FAIL;
1142 }
1143
1144 return SIM_RC_OK;
1145 }
1146
1147
1148
1149 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1150 int
1151 sim_monitor (SIM_DESC sd,
1152 sim_cpu *cpu,
1153 address_word cia,
1154 unsigned int reason)
1155 {
1156 #ifdef DEBUG
1157 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
1158 #endif /* DEBUG */
1159
1160 /* The IDT monitor actually allows two instructions per vector
1161 slot. However, the simulator currently causes a trap on each
1162 individual instruction. We cheat, and lose the bottom bit. */
1163 reason >>= 1;
1164
1165 /* The following callback functions are available, however the
1166 monitor we are simulating does not make use of them: get_errno,
1167 isatty, lseek, rename, system, time and unlink */
1168 switch (reason)
1169 {
1170
1171 case 6: /* int open(char *path,int flags) */
1172 {
1173 char *path = fetch_str (sd, A0);
1174 V0 = sim_io_open (sd, path, (int)A1);
1175 free (path);
1176 break;
1177 }
1178
1179 case 7: /* int read(int file,char *ptr,int len) */
1180 {
1181 int fd = A0;
1182 int nr = A2;
1183 char *buf = zalloc (nr);
1184 V0 = sim_io_read (sd, fd, buf, nr);
1185 sim_write (sd, A1, (unsigned char *)buf, nr);
1186 free (buf);
1187 }
1188 break;
1189
1190 case 8: /* int write(int file,char *ptr,int len) */
1191 {
1192 int fd = A0;
1193 int nr = A2;
1194 char *buf = zalloc (nr);
1195 sim_read (sd, A1, (unsigned char *)buf, nr);
1196 V0 = sim_io_write (sd, fd, buf, nr);
1197 if (fd == 1)
1198 sim_io_flush_stdout (sd);
1199 else if (fd == 2)
1200 sim_io_flush_stderr (sd);
1201 free (buf);
1202 break;
1203 }
1204
1205 case 10: /* int close(int file) */
1206 {
1207 V0 = sim_io_close (sd, (int)A0);
1208 break;
1209 }
1210
1211 case 2: /* Densan monitor: char inbyte(int waitflag) */
1212 {
1213 if (A0 == 0) /* waitflag == NOWAIT */
1214 V0 = (unsigned_word)-1;
1215 }
1216 /* Drop through to case 11 */
1217
1218 case 11: /* char inbyte(void) */
1219 {
1220 char tmp;
1221 /* ensure that all output has gone... */
1222 sim_io_flush_stdout (sd);
1223 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
1224 {
1225 sim_io_error(sd,"Invalid return from character read");
1226 V0 = (unsigned_word)-1;
1227 }
1228 else
1229 V0 = (unsigned_word)tmp;
1230 break;
1231 }
1232
1233 case 3: /* Densan monitor: void co(char chr) */
1234 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1235 {
1236 char tmp = (char)(A0 & 0xFF);
1237 sim_io_write_stdout (sd, &tmp, sizeof(char));
1238 break;
1239 }
1240
1241 case 17: /* void _exit() */
1242 {
1243 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
1244 sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
1245 (unsigned int)(A0 & 0xFFFFFFFF));
1246 break;
1247 }
1248
1249 case 28: /* PMON flush_cache */
1250 break;
1251
1252 case 55: /* void get_mem_info(unsigned int *ptr) */
1253 /* in: A0 = pointer to three word memory location */
1254 /* out: [A0 + 0] = size */
1255 /* [A0 + 4] = instruction cache size */
1256 /* [A0 + 8] = data cache size */
1257 {
1258 unsigned_4 value;
1259 unsigned_4 zero = 0;
1260 address_word mem_size;
1261 sim_memopt *entry, *match = NULL;
1262
1263 /* Search for memory region mapped to KSEG0 or KSEG1. */
1264 for (entry = STATE_MEMOPT (sd);
1265 entry != NULL;
1266 entry = entry->next)
1267 {
1268 if ((entry->addr == K0BASE || entry->addr == K1BASE)
1269 && (!match || entry->level < match->level))
1270 match = entry;
1271 else
1272 {
1273 sim_memopt *alias;
1274 for (alias = entry->alias;
1275 alias != NULL;
1276 alias = alias->next)
1277 if ((alias->addr == K0BASE || alias->addr == K1BASE)
1278 && (!match || entry->level < match->level))
1279 match = entry;
1280 }
1281 }
1282
1283 /* Get region size, limit to KSEG1 size (512MB). */
1284 SIM_ASSERT (match != NULL);
1285 mem_size = (match->modulo != 0
1286 ? match->modulo : match->nr_bytes);
1287 if (mem_size > K1SIZE)
1288 mem_size = K1SIZE;
1289
1290 value = mem_size;
1291 H2T (value);
1292 sim_write (sd, A0 + 0, (unsigned char *)&value, 4);
1293 sim_write (sd, A0 + 4, (unsigned char *)&zero, 4);
1294 sim_write (sd, A0 + 8, (unsigned char *)&zero, 4);
1295 /* sim_io_eprintf (sd, "sim: get_mem_info() deprecated\n"); */
1296 break;
1297 }
1298
1299 case 158: /* PMON printf */
1300 /* in: A0 = pointer to format string */
1301 /* A1 = optional argument 1 */
1302 /* A2 = optional argument 2 */
1303 /* A3 = optional argument 3 */
1304 /* out: void */
1305 /* The following is based on the PMON printf source */
1306 {
1307 address_word s = A0;
1308 unsigned char c;
1309 signed_word *ap = &A1; /* 1st argument */
1310 /* This isn't the quickest way, since we call the host print
1311 routine for every character almost. But it does avoid
1312 having to allocate and manage a temporary string buffer. */
1313 /* TODO: Include check that we only use three arguments (A1,
1314 A2 and A3) */
1315 while (sim_read (sd, s++, &c, 1) && c != '\0')
1316 {
1317 if (c == '%')
1318 {
1319 char tmp[40];
1320 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
1321 int width = 0, trunc = 0, haddot = 0, longlong = 0;
1322 while (sim_read (sd, s++, &c, 1) && c != '\0')
1323 {
1324 if (strchr ("dobxXulscefg%", c))
1325 break;
1326 else if (c == '-')
1327 fmt = FMT_LJUST;
1328 else if (c == '0')
1329 fmt = FMT_RJUST0;
1330 else if (c == '~')
1331 fmt = FMT_CENTER;
1332 else if (c == '*')
1333 {
1334 if (haddot)
1335 trunc = (int)*ap++;
1336 else
1337 width = (int)*ap++;
1338 }
1339 else if (c >= '1' && c <= '9')
1340 {
1341 address_word t = s;
1342 unsigned int n;
1343 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
1344 tmp[s - t] = c;
1345 tmp[s - t] = '\0';
1346 n = (unsigned int)strtol(tmp,NULL,10);
1347 if (haddot)
1348 trunc = n;
1349 else
1350 width = n;
1351 s--;
1352 }
1353 else if (c == '.')
1354 haddot = 1;
1355 }
1356 switch (c)
1357 {
1358 case '%':
1359 sim_io_printf (sd, "%%");
1360 break;
1361 case 's':
1362 if ((int)*ap != 0)
1363 {
1364 address_word p = *ap++;
1365 unsigned char ch;
1366 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
1367 sim_io_printf(sd, "%c", ch);
1368 }
1369 else
1370 sim_io_printf(sd,"(null)");
1371 break;
1372 case 'c':
1373 sim_io_printf (sd, "%c", (int)*ap++);
1374 break;
1375 default:
1376 if (c == 'l')
1377 {
1378 sim_read (sd, s++, &c, 1);
1379 if (c == 'l')
1380 {
1381 longlong = 1;
1382 sim_read (sd, s++, &c, 1);
1383 }
1384 }
1385 if (strchr ("dobxXu", c))
1386 {
1387 word64 lv = (word64) *ap++;
1388 if (c == 'b')
1389 sim_io_printf(sd,"<binary not supported>");
1390 else
1391 {
1392 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
1393 if (longlong)
1394 sim_io_printf(sd, tmp, lv);
1395 else
1396 sim_io_printf(sd, tmp, (int)lv);
1397 }
1398 }
1399 else if (strchr ("eEfgG", c))
1400 {
1401 double dbl = *(double*)(ap++);
1402 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
1403 sim_io_printf (sd, tmp, dbl);
1404 trunc = 0;
1405 }
1406 }
1407 }
1408 else
1409 sim_io_printf(sd, "%c", c);
1410 }
1411 break;
1412 }
1413
1414 default:
1415 /* Unknown reason. */
1416 return 0;
1417 }
1418 return 1;
1419 }
1420
1421 /* Store a word into memory. */
1422
1423 static void
1424 store_word (SIM_DESC sd,
1425 sim_cpu *cpu,
1426 address_word cia,
1427 uword64 vaddr,
1428 signed_word val)
1429 {
1430 address_word paddr = vaddr;
1431
1432 if ((vaddr & 3) != 0)
1433 SignalExceptionAddressStore ();
1434 else
1435 {
1436 const uword64 mask = 7;
1437 uword64 memval;
1438 unsigned int byte;
1439
1440 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
1441 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
1442 memval = ((uword64) val) << (8 * byte);
1443 StoreMemory (AccessLength_WORD, memval, 0, paddr, vaddr,
1444 isREAL);
1445 }
1446 }
1447
1448 /* Load a word from memory. */
1449
1450 static signed_word
1451 load_word (SIM_DESC sd,
1452 sim_cpu *cpu,
1453 address_word cia,
1454 uword64 vaddr)
1455 {
1456 if ((vaddr & 3) != 0)
1457 {
1458 SIM_CORE_SIGNAL (SD, cpu, cia, read_map, AccessLength_WORD+1, vaddr, read_transfer, sim_core_unaligned_signal);
1459 }
1460 else
1461 {
1462 address_word paddr = vaddr;
1463 const uword64 mask = 0x7;
1464 const unsigned int reverse = ReverseEndian ? 1 : 0;
1465 const unsigned int bigend = BigEndianCPU ? 1 : 0;
1466 uword64 memval;
1467 unsigned int byte;
1468
1469 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
1470 LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA,
1471 isREAL);
1472 byte = (vaddr & mask) ^ (bigend << 2);
1473 return EXTEND32 (memval >> (8 * byte));
1474 }
1475
1476 return 0;
1477 }
1478
1479 /* Simulate the mips16 entry and exit pseudo-instructions. These
1480 would normally be handled by the reserved instruction exception
1481 code, but for ease of simulation we just handle them directly. */
1482
1483 static void
1484 mips16_entry (SIM_DESC sd,
1485 sim_cpu *cpu,
1486 address_word cia,
1487 unsigned int insn)
1488 {
1489 int aregs, sregs, rreg;
1490
1491 #ifdef DEBUG
1492 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1493 #endif /* DEBUG */
1494
1495 aregs = (insn & 0x700) >> 8;
1496 sregs = (insn & 0x0c0) >> 6;
1497 rreg = (insn & 0x020) >> 5;
1498
1499 /* This should be checked by the caller. */
1500 if (sregs == 3)
1501 abort ();
1502
1503 if (aregs < 5)
1504 {
1505 int i;
1506 signed_word tsp;
1507
1508 /* This is the entry pseudo-instruction. */
1509
1510 for (i = 0; i < aregs; i++)
1511 store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
1512
1513 tsp = SP;
1514 SP -= 32;
1515
1516 if (rreg)
1517 {
1518 tsp -= 4;
1519 store_word (SD, CPU, cia, (uword64) tsp, RA);
1520 }
1521
1522 for (i = 0; i < sregs; i++)
1523 {
1524 tsp -= 4;
1525 store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
1526 }
1527 }
1528 else
1529 {
1530 int i;
1531 signed_word tsp;
1532
1533 /* This is the exit pseudo-instruction. */
1534
1535 tsp = SP + 32;
1536
1537 if (rreg)
1538 {
1539 tsp -= 4;
1540 RA = load_word (SD, CPU, cia, (uword64) tsp);
1541 }
1542
1543 for (i = 0; i < sregs; i++)
1544 {
1545 tsp -= 4;
1546 GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
1547 }
1548
1549 SP += 32;
1550
1551 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1552 {
1553 if (aregs == 5)
1554 {
1555 FGR[0] = WORD64LO (GPR[4]);
1556 FPR_STATE[0] = fmt_uninterpreted;
1557 }
1558 else if (aregs == 6)
1559 {
1560 FGR[0] = WORD64LO (GPR[5]);
1561 FGR[1] = WORD64LO (GPR[4]);
1562 FPR_STATE[0] = fmt_uninterpreted;
1563 FPR_STATE[1] = fmt_uninterpreted;
1564 }
1565 }
1566
1567 PC = RA;
1568 }
1569
1570 }
1571
1572 /*-- trace support ----------------------------------------------------------*/
1573
1574 /* The trace support is provided (if required) in the memory accessing
1575 routines. Since we are also providing the architecture specific
1576 features, the architecture simulation code can also deal with
1577 notifying the trace world of cache flushes, etc. Similarly we do
1578 not need to provide profiling support in the simulator engine,
1579 since we can sample in the instruction fetch control loop. By
1580 defining the trace manifest, we add tracing as a run-time
1581 option. */
1582
1583 #if WITH_TRACE_ANY_P
1584 /* Tracing by default produces "din" format (as required by
1585 dineroIII). Each line of such a trace file *MUST* have a din label
1586 and address field. The rest of the line is ignored, so comments can
1587 be included if desired. The first field is the label which must be
1588 one of the following values:
1589
1590 0 read data
1591 1 write data
1592 2 instruction fetch
1593 3 escape record (treated as unknown access type)
1594 4 escape record (causes cache flush)
1595
1596 The address field is a 32bit (lower-case) hexadecimal address
1597 value. The address should *NOT* be preceded by "0x".
1598
1599 The size of the memory transfer is not important when dealing with
1600 cache lines (as long as no more than a cache line can be
1601 transferred in a single operation :-), however more information
1602 could be given following the dineroIII requirement to allow more
1603 complete memory and cache simulators to provide better
1604 results. i.e. the University of Pisa has a cache simulator that can
1605 also take bus size and speed as (variable) inputs to calculate
1606 complete system performance (a much more useful ability when trying
1607 to construct an end product, rather than a processor). They
1608 currently have an ARM version of their tool called ChARM. */
1609
1610
1611 void
1612 dotrace (SIM_DESC sd,
1613 sim_cpu *cpu,
1614 FILE *tracefh,
1615 int type,
1616 SIM_ADDR address,
1617 int width,
1618 char *comment,...)
1619 {
1620 if (STATE & simTRACE) {
1621 va_list ap;
1622 fprintf(tracefh,"%d %s ; width %d ; ",
1623 type,
1624 pr_addr(address),
1625 width);
1626 va_start(ap,comment);
1627 vfprintf(tracefh,comment,ap);
1628 va_end(ap);
1629 fprintf(tracefh,"\n");
1630 }
1631 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1632 we may be generating 64bit ones, we should put the hi-32bits of the
1633 address into the comment field. */
1634
1635 /* TODO: Provide a buffer for the trace lines. We can then avoid
1636 performing writes until the buffer is filled, or the file is
1637 being closed. */
1638
1639 /* NOTE: We could consider adding a comment field to the "din" file
1640 produced using type 3 markers (unknown access). This would then
1641 allow information about the program that the "din" is for, and
1642 the MIPs world that was being simulated, to be placed into the
1643 trace file. */
1644
1645 return;
1646 }
1647 #endif /* WITH_TRACE_ANY_P */
1648
1649 /*---------------------------------------------------------------------------*/
1650 /*-- simulator engine -------------------------------------------------------*/
1651 /*---------------------------------------------------------------------------*/
1652
1653 static void
1654 ColdReset (SIM_DESC sd)
1655 {
1656 int cpu_nr;
1657 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1658 {
1659 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1660 /* RESET: Fixed PC address: */
1661 PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000);
1662 /* The reset vector address is in the unmapped, uncached memory space. */
1663
1664 SR &= ~(status_SR | status_TS | status_RP);
1665 SR |= (status_ERL | status_BEV);
1666
1667 /* Cheat and allow access to the complete register set immediately */
1668 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1669 && WITH_TARGET_WORD_BITSIZE == 64)
1670 SR |= status_FR; /* 64bit registers */
1671
1672 /* Ensure that any instructions with pending register updates are
1673 cleared: */
1674 PENDING_INVALIDATE();
1675
1676 /* Initialise the FPU registers to the unknown state */
1677 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1678 {
1679 int rn;
1680 for (rn = 0; (rn < 32); rn++)
1681 FPR_STATE[rn] = fmt_uninterpreted;
1682 }
1683
1684 /* Initialise the Config0 register. */
1685 C0_CONFIG = 0x80000000 /* Config1 present */
1686 | 2; /* KSEG0 uncached */
1687 if (WITH_TARGET_WORD_BITSIZE == 64)
1688 {
1689 /* FIXME Currently mips/sim-main.c:address_translation()
1690 truncates all addresses to 32-bits. */
1691 if (0 && WITH_TARGET_ADDRESS_BITSIZE == 64)
1692 C0_CONFIG |= (2 << 13); /* MIPS64, 64-bit addresses */
1693 else
1694 C0_CONFIG |= (1 << 13); /* MIPS64, 32-bit addresses */
1695 }
1696 if (BigEndianMem)
1697 C0_CONFIG |= 0x00008000; /* Big Endian */
1698 }
1699 }
1700
1701
1702
1703
1704 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1705 /* Signal an exception condition. This will result in an exception
1706 that aborts the instruction. The instruction operation pseudocode
1707 will never see a return from this function call. */
1708
1709 void
1710 signal_exception (SIM_DESC sd,
1711 sim_cpu *cpu,
1712 address_word cia,
1713 int exception,...)
1714 {
1715 /* int vector; */
1716
1717 #ifdef DEBUG
1718 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1719 #endif /* DEBUG */
1720
1721 /* Ensure that any active atomic read/modify/write operation will fail: */
1722 LLBIT = 0;
1723
1724 /* Save registers before interrupt dispatching */
1725 #ifdef SIM_CPU_EXCEPTION_TRIGGER
1726 SIM_CPU_EXCEPTION_TRIGGER(sd, cpu, cia);
1727 #endif
1728
1729 switch (exception) {
1730
1731 case DebugBreakPoint:
1732 if (! (Debug & Debug_DM))
1733 {
1734 if (INDELAYSLOT())
1735 {
1736 CANCELDELAYSLOT();
1737
1738 Debug |= Debug_DBD; /* signaled from within in delay slot */
1739 DEPC = cia - 4; /* reference the branch instruction */
1740 }
1741 else
1742 {
1743 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
1744 DEPC = cia;
1745 }
1746
1747 Debug |= Debug_DM; /* in debugging mode */
1748 Debug |= Debug_DBp; /* raising a DBp exception */
1749 PC = 0xBFC00200;
1750 sim_engine_restart (SD, CPU, NULL, NULL_CIA);
1751 }
1752 break;
1753
1754 case ReservedInstruction:
1755 {
1756 va_list ap;
1757 unsigned int instruction;
1758 va_start(ap,exception);
1759 instruction = va_arg(ap,unsigned int);
1760 va_end(ap);
1761 /* Provide simple monitor support using ReservedInstruction
1762 exceptions. The following code simulates the fixed vector
1763 entry points into the IDT monitor by causing a simulator
1764 trap, performing the monitor operation, and returning to
1765 the address held in the $ra register (standard PCS return
1766 address). This means we only need to pre-load the vector
1767 space with suitable instruction values. For systems were
1768 actual trap instructions are used, we would not need to
1769 perform this magic. */
1770 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1771 {
1772 int reason = (instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK;
1773 if (!sim_monitor (SD, CPU, cia, reason))
1774 sim_io_error (sd, "sim_monitor: unhandled reason = %d, pc = 0x%s\n", reason, pr_addr (cia));
1775
1776 /* NOTE: This assumes that a branch-and-link style
1777 instruction was used to enter the vector (which is the
1778 case with the current IDT monitor). */
1779 sim_engine_restart (SD, CPU, NULL, RA);
1780 }
1781 /* Look for the mips16 entry and exit instructions, and
1782 simulate a handler for them. */
1783 else if ((cia & 1) != 0
1784 && (instruction & 0xf81f) == 0xe809
1785 && (instruction & 0x0c0) != 0x0c0)
1786 {
1787 mips16_entry (SD, CPU, cia, instruction);
1788 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1789 }
1790 /* else fall through to normal exception processing */
1791 sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
1792 }
1793
1794 default:
1795 /* Store exception code into current exception id variable (used
1796 by exit code): */
1797
1798 /* TODO: If not simulating exceptions then stop the simulator
1799 execution. At the moment we always stop the simulation. */
1800
1801 #ifdef SUBTARGET_R3900
1802 /* update interrupt-related registers */
1803
1804 /* insert exception code in bits 6:2 */
1805 CAUSE = LSMASKED32(CAUSE, 31, 7) | LSINSERTED32(exception, 6, 2);
1806 /* shift IE/KU history bits left */
1807 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 3, 0), 5, 2);
1808
1809 if (STATE & simDELAYSLOT)
1810 {
1811 STATE &= ~simDELAYSLOT;
1812 CAUSE |= cause_BD;
1813 EPC = (cia - 4); /* reference the branch instruction */
1814 }
1815 else
1816 EPC = cia;
1817
1818 if (SR & status_BEV)
1819 PC = (signed)0xBFC00000 + 0x180;
1820 else
1821 PC = (signed)0x80000000 + 0x080;
1822 #else
1823 /* See figure 5-17 for an outline of the code below */
1824 if (! (SR & status_EXL))
1825 {
1826 CAUSE = (exception << 2);
1827 if (STATE & simDELAYSLOT)
1828 {
1829 STATE &= ~simDELAYSLOT;
1830 CAUSE |= cause_BD;
1831 EPC = (cia - 4); /* reference the branch instruction */
1832 }
1833 else
1834 EPC = cia;
1835 /* FIXME: TLB et.al. */
1836 /* vector = 0x180; */
1837 }
1838 else
1839 {
1840 CAUSE = (exception << 2);
1841 /* vector = 0x180; */
1842 }
1843 SR |= status_EXL;
1844 /* Store exception code into current exception id variable (used
1845 by exit code): */
1846
1847 if (SR & status_BEV)
1848 PC = (signed)0xBFC00200 + 0x180;
1849 else
1850 PC = (signed)0x80000000 + 0x180;
1851 #endif
1852
1853 switch ((CAUSE >> 2) & 0x1F)
1854 {
1855 case Interrupt:
1856 /* Interrupts arrive during event processing, no need to
1857 restart */
1858 return;
1859
1860 case NMIReset:
1861 /* Ditto */
1862 #ifdef SUBTARGET_3900
1863 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
1864 PC = (signed)0xBFC00000;
1865 #endif /* SUBTARGET_3900 */
1866 return;
1867
1868 case TLBModification:
1869 case TLBLoad:
1870 case TLBStore:
1871 case AddressLoad:
1872 case AddressStore:
1873 case InstructionFetch:
1874 case DataReference:
1875 /* The following is so that the simulator will continue from the
1876 exception handler address. */
1877 sim_engine_halt (SD, CPU, NULL, PC,
1878 sim_stopped, SIM_SIGBUS);
1879
1880 case ReservedInstruction:
1881 case CoProcessorUnusable:
1882 PC = EPC;
1883 sim_engine_halt (SD, CPU, NULL, PC,
1884 sim_stopped, SIM_SIGILL);
1885
1886 case IntegerOverflow:
1887 case FPE:
1888 sim_engine_halt (SD, CPU, NULL, PC,
1889 sim_stopped, SIM_SIGFPE);
1890
1891 case BreakPoint:
1892 sim_engine_halt (SD, CPU, NULL, PC, sim_stopped, SIM_SIGTRAP);
1893 break;
1894
1895 case SystemCall:
1896 case Trap:
1897 sim_engine_restart (SD, CPU, NULL, PC);
1898 break;
1899
1900 case Watch:
1901 PC = EPC;
1902 sim_engine_halt (SD, CPU, NULL, PC,
1903 sim_stopped, SIM_SIGTRAP);
1904
1905 default: /* Unknown internal exception */
1906 PC = EPC;
1907 sim_engine_halt (SD, CPU, NULL, PC,
1908 sim_stopped, SIM_SIGABRT);
1909
1910 }
1911
1912 case SimulatorFault:
1913 {
1914 va_list ap;
1915 char *msg;
1916 va_start(ap,exception);
1917 msg = va_arg(ap,char *);
1918 va_end(ap);
1919 sim_engine_abort (SD, CPU, NULL_CIA,
1920 "FATAL: Simulator error \"%s\"\n",msg);
1921 }
1922 }
1923
1924 return;
1925 }
1926
1927
1928
1929 /* This function implements what the MIPS32 and MIPS64 ISAs define as
1930 "UNPREDICTABLE" behaviour.
1931
1932 About UNPREDICTABLE behaviour they say: "UNPREDICTABLE results
1933 may vary from processor implementation to processor implementation,
1934 instruction to instruction, or as a function of time on the same
1935 implementation or instruction. Software can never depend on results
1936 that are UNPREDICTABLE. ..." (MIPS64 Architecture for Programmers
1937 Volume II, The MIPS64 Instruction Set. MIPS Document MD00087 revision
1938 0.95, page 2.)
1939
1940 For UNPREDICTABLE behaviour, we print a message, if possible print
1941 the offending instructions mips.igen instruction name (provided by
1942 the caller), and stop the simulator.
1943
1944 XXX FIXME: eventually, stopping the simulator should be made conditional
1945 on a command-line option. */
1946 void
1947 unpredictable_action(sim_cpu *cpu, address_word cia)
1948 {
1949 SIM_DESC sd = CPU_STATE(cpu);
1950
1951 sim_io_eprintf(sd, "UNPREDICTABLE: PC = 0x%s\n", pr_addr (cia));
1952 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGABRT);
1953 }
1954
1955
1956 /*-- co-processor support routines ------------------------------------------*/
1957
1958 static int UNUSED
1959 CoProcPresent(unsigned int coproc_number)
1960 {
1961 /* Return TRUE if simulator provides a model for the given co-processor number */
1962 return(0);
1963 }
1964
1965 void
1966 cop_lw (SIM_DESC sd,
1967 sim_cpu *cpu,
1968 address_word cia,
1969 int coproc_num,
1970 int coproc_reg,
1971 unsigned int memword)
1972 {
1973 switch (coproc_num)
1974 {
1975 case 1:
1976 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1977 {
1978 #ifdef DEBUG
1979 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
1980 #endif
1981 StoreFPR(coproc_reg,fmt_uninterpreted_32,(uword64)memword);
1982 break;
1983 }
1984
1985 default:
1986 #if 0 /* this should be controlled by a configuration option */
1987 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
1988 #endif
1989 break;
1990 }
1991
1992 return;
1993 }
1994
1995 void
1996 cop_ld (SIM_DESC sd,
1997 sim_cpu *cpu,
1998 address_word cia,
1999 int coproc_num,
2000 int coproc_reg,
2001 uword64 memword)
2002 {
2003
2004 #ifdef DEBUG
2005 printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num, coproc_reg, pr_uword64(memword), pr_addr(cia) );
2006 #endif
2007
2008 switch (coproc_num) {
2009 case 1:
2010 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2011 {
2012 StoreFPR(coproc_reg,fmt_uninterpreted_64,memword);
2013 break;
2014 }
2015
2016 default:
2017 #if 0 /* this message should be controlled by a configuration option */
2018 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
2019 #endif
2020 break;
2021 }
2022
2023 return;
2024 }
2025
2026
2027
2028
2029 unsigned int
2030 cop_sw (SIM_DESC sd,
2031 sim_cpu *cpu,
2032 address_word cia,
2033 int coproc_num,
2034 int coproc_reg)
2035 {
2036 unsigned int value = 0;
2037
2038 switch (coproc_num)
2039 {
2040 case 1:
2041 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2042 {
2043 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted_32);
2044 break;
2045 }
2046
2047 default:
2048 #if 0 /* should be controlled by configuration option */
2049 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2050 #endif
2051 break;
2052 }
2053
2054 return(value);
2055 }
2056
2057 uword64
2058 cop_sd (SIM_DESC sd,
2059 sim_cpu *cpu,
2060 address_word cia,
2061 int coproc_num,
2062 int coproc_reg)
2063 {
2064 uword64 value = 0;
2065 switch (coproc_num)
2066 {
2067 case 1:
2068 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2069 {
2070 value = ValueFPR(coproc_reg,fmt_uninterpreted_64);
2071 break;
2072 }
2073
2074 default:
2075 #if 0 /* should be controlled by configuration option */
2076 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2077 #endif
2078 break;
2079 }
2080
2081 return(value);
2082 }
2083
2084
2085
2086
2087 void
2088 decode_coproc (SIM_DESC sd,
2089 sim_cpu *cpu,
2090 address_word cia,
2091 unsigned int instruction,
2092 int coprocnum,
2093 CP0_operation op,
2094 int rt,
2095 int rd,
2096 int sel)
2097 {
2098 switch (coprocnum)
2099 {
2100 case 0: /* standard CPU control and cache registers */
2101 {
2102 /* R4000 Users Manual (second edition) lists the following CP0
2103 instructions:
2104 CODE><-RT><RD-><--TAIL--->
2105 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2106 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2107 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2108 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2109 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2110 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2111 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2112 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2113 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2114 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2115 */
2116 if (((op == cp0_mfc0) || (op == cp0_mtc0) /* MFC0 / MTC0 */
2117 || (op == cp0_dmfc0) || (op == cp0_dmtc0)) /* DMFC0 / DMTC0 */
2118 && sel == 0)
2119 {
2120 switch (rd) /* NOTEs: Standard CP0 registers */
2121 {
2122 /* 0 = Index R4000 VR4100 VR4300 */
2123 /* 1 = Random R4000 VR4100 VR4300 */
2124 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2125 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2126 /* 4 = Context R4000 VR4100 VR4300 */
2127 /* 5 = PageMask R4000 VR4100 VR4300 */
2128 /* 6 = Wired R4000 VR4100 VR4300 */
2129 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2130 /* 9 = Count R4000 VR4100 VR4300 */
2131 /* 10 = EntryHi R4000 VR4100 VR4300 */
2132 /* 11 = Compare R4000 VR4100 VR4300 */
2133 /* 12 = SR R4000 VR4100 VR4300 */
2134 #ifdef SUBTARGET_R3900
2135 case 3:
2136 /* 3 = Config R3900 */
2137 case 7:
2138 /* 7 = Cache R3900 */
2139 case 15:
2140 /* 15 = PRID R3900 */
2141
2142 /* ignore */
2143 break;
2144
2145 case 8:
2146 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2147 if (op == cp0_mfc0 || op == cp0_dmfc0)
2148 GPR[rt] = (signed_word) (signed_address) COP0_BADVADDR;
2149 else
2150 COP0_BADVADDR = GPR[rt];
2151 break;
2152
2153 #endif /* SUBTARGET_R3900 */
2154 case 12:
2155 if (op == cp0_mfc0 || op == cp0_dmfc0)
2156 GPR[rt] = SR;
2157 else
2158 SR = GPR[rt];
2159 break;
2160 /* 13 = Cause R4000 VR4100 VR4300 */
2161 case 13:
2162 if (op == cp0_mfc0 || op == cp0_dmfc0)
2163 GPR[rt] = CAUSE;
2164 else
2165 CAUSE = GPR[rt];
2166 break;
2167 /* 14 = EPC R4000 VR4100 VR4300 */
2168 case 14:
2169 if (op == cp0_mfc0 || op == cp0_dmfc0)
2170 GPR[rt] = (signed_word) (signed_address) EPC;
2171 else
2172 EPC = GPR[rt];
2173 break;
2174 /* 15 = PRId R4000 VR4100 VR4300 */
2175 #ifdef SUBTARGET_R3900
2176 /* 16 = Debug */
2177 case 16:
2178 if (op == cp0_mfc0 || op == cp0_dmfc0)
2179 GPR[rt] = Debug;
2180 else
2181 Debug = GPR[rt];
2182 break;
2183 #else
2184 /* 16 = Config R4000 VR4100 VR4300 */
2185 case 16:
2186 if (op == cp0_mfc0 || op == cp0_dmfc0)
2187 GPR[rt] = C0_CONFIG;
2188 else
2189 /* only bottom three bits are writable */
2190 C0_CONFIG = (C0_CONFIG & ~0x7) | (GPR[rt] & 0x7);
2191 break;
2192 #endif
2193 #ifdef SUBTARGET_R3900
2194 /* 17 = Debug */
2195 case 17:
2196 if (op == cp0_mfc0 || op == cp0_dmfc0)
2197 GPR[rt] = DEPC;
2198 else
2199 DEPC = GPR[rt];
2200 break;
2201 #else
2202 /* 17 = LLAddr R4000 VR4100 VR4300 */
2203 #endif
2204 /* 18 = WatchLo R4000 VR4100 VR4300 */
2205 /* 19 = WatchHi R4000 VR4100 VR4300 */
2206 /* 20 = XContext R4000 VR4100 VR4300 */
2207 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
2208 /* 27 = CacheErr R4000 VR4100 */
2209 /* 28 = TagLo R4000 VR4100 VR4300 */
2210 /* 29 = TagHi R4000 VR4100 VR4300 */
2211 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
2212 if (STATE_VERBOSE_P(SD))
2213 sim_io_eprintf (SD,
2214 "Warning: PC 0x%lx:interp.c decode_coproc DEADC0DE\n",
2215 (unsigned long)cia);
2216 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
2217 /* CPR[0,rd] = GPR[rt]; */
2218 default:
2219 if (op == cp0_mfc0 || op == cp0_dmfc0)
2220 GPR[rt] = (signed_word) (signed32) COP0_GPR[rd];
2221 else
2222 COP0_GPR[rd] = GPR[rt];
2223 #if 0
2224 if (code == 0x00)
2225 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
2226 else
2227 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
2228 #endif
2229 }
2230 }
2231 else if ((op == cp0_mfc0 || op == cp0_dmfc0)
2232 && rd == 16)
2233 {
2234 /* [D]MFC0 RT,C0_CONFIG,SEL */
2235 signed32 cfg = 0;
2236 switch (sel)
2237 {
2238 case 0:
2239 cfg = C0_CONFIG;
2240 break;
2241 case 1:
2242 /* MIPS32 r/o Config1:
2243 Config2 present */
2244 cfg = 0x80000000;
2245 /* MIPS16 implemented.
2246 XXX How to check configuration? */
2247 cfg |= 0x0000004;
2248 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2249 /* MDMX & FPU implemented */
2250 cfg |= 0x00000021;
2251 break;
2252 case 2:
2253 /* MIPS32 r/o Config2:
2254 Config3 present. */
2255 cfg = 0x80000000;
2256 break;
2257 case 3:
2258 /* MIPS32 r/o Config3:
2259 SmartMIPS implemented. */
2260 cfg = 0x00000002;
2261 break;
2262 }
2263 GPR[rt] = cfg;
2264 }
2265 else if (op == cp0_eret && sel == 0x18)
2266 {
2267 /* ERET */
2268 if (SR & status_ERL)
2269 {
2270 /* Oops, not yet available */
2271 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
2272 PC = EPC;
2273 SR &= ~status_ERL;
2274 }
2275 else
2276 {
2277 PC = EPC;
2278 SR &= ~status_EXL;
2279 }
2280 }
2281 else if (op == cp0_rfe && sel == 0x10)
2282 {
2283 /* RFE */
2284 #ifdef SUBTARGET_R3900
2285 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
2286
2287 /* shift IE/KU history bits right */
2288 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2), 3, 0);
2289
2290 /* TODO: CACHE register */
2291 #endif /* SUBTARGET_R3900 */
2292 }
2293 else if (op == cp0_deret && sel == 0x1F)
2294 {
2295 /* DERET */
2296 Debug &= ~Debug_DM;
2297 DELAYSLOT();
2298 DSPC = DEPC;
2299 }
2300 else
2301 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
2302 /* TODO: When executing an ERET or RFE instruction we should
2303 clear LLBIT, to ensure that any out-standing atomic
2304 read/modify/write sequence fails. */
2305 }
2306 break;
2307
2308 case 2: /* co-processor 2 */
2309 {
2310 int handle = 0;
2311
2312
2313 if(! handle)
2314 {
2315 sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
2316 instruction,pr_addr(cia));
2317 }
2318 }
2319 break;
2320
2321 case 1: /* should not occur (FPU co-processor) */
2322 case 3: /* should not occur (FPU co-processor) */
2323 SignalException(ReservedInstruction,instruction);
2324 break;
2325 }
2326
2327 return;
2328 }
2329
2330
2331 /* This code copied from gdb's utils.c. Would like to share this code,
2332 but don't know of a common place where both could get to it. */
2333
2334 /* Temporary storage using circular buffer */
2335 #define NUMCELLS 16
2336 #define CELLSIZE 32
2337 static char*
2338 get_cell (void)
2339 {
2340 static char buf[NUMCELLS][CELLSIZE];
2341 static int cell=0;
2342 if (++cell>=NUMCELLS) cell=0;
2343 return buf[cell];
2344 }
2345
2346 /* Print routines to handle variable size regs, etc */
2347
2348 /* Eliminate warning from compiler on 32-bit systems */
2349 static int thirty_two = 32;
2350
2351 char*
2352 pr_addr (SIM_ADDR addr)
2353 {
2354 char *paddr_str=get_cell();
2355 switch (sizeof(addr))
2356 {
2357 case 8:
2358 sprintf(paddr_str,"%08lx%08lx",
2359 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
2360 break;
2361 case 4:
2362 sprintf(paddr_str,"%08lx",(unsigned long)addr);
2363 break;
2364 case 2:
2365 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
2366 break;
2367 default:
2368 sprintf(paddr_str,"%x",addr);
2369 }
2370 return paddr_str;
2371 }
2372
2373 char*
2374 pr_uword64 (uword64 addr)
2375 {
2376 char *paddr_str=get_cell();
2377 sprintf(paddr_str,"%08lx%08lx",
2378 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
2379 return paddr_str;
2380 }
2381
2382
2383 void
2384 mips_core_signal (SIM_DESC sd,
2385 sim_cpu *cpu,
2386 sim_cia cia,
2387 unsigned map,
2388 int nr_bytes,
2389 address_word addr,
2390 transfer_type transfer,
2391 sim_core_signals sig)
2392 {
2393 const char *copy = (transfer == read_transfer ? "read" : "write");
2394 address_word ip = CIA_ADDR (cia);
2395
2396 switch (sig)
2397 {
2398 case sim_core_unmapped_signal:
2399 sim_io_eprintf (sd, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
2400 nr_bytes, copy,
2401 (unsigned long) addr, (unsigned long) ip);
2402 COP0_BADVADDR = addr;
2403 SignalExceptionDataReference();
2404 break;
2405
2406 case sim_core_unaligned_signal:
2407 sim_io_eprintf (sd, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
2408 nr_bytes, copy,
2409 (unsigned long) addr, (unsigned long) ip);
2410 COP0_BADVADDR = addr;
2411 if(transfer == read_transfer)
2412 SignalExceptionAddressLoad();
2413 else
2414 SignalExceptionAddressStore();
2415 break;
2416
2417 default:
2418 sim_engine_abort (sd, cpu, cia,
2419 "mips_core_signal - internal error - bad switch");
2420 }
2421 }
2422
2423
2424 void
2425 mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia)
2426 {
2427 ASSERT(cpu != NULL);
2428
2429 if(cpu->exc_suspended > 0)
2430 sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", cpu->exc_suspended);
2431
2432 PC = cia;
2433 memcpy(cpu->exc_trigger_registers, cpu->registers, sizeof(cpu->exc_trigger_registers));
2434 cpu->exc_suspended = 0;
2435 }
2436
2437 void
2438 mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception)
2439 {
2440 ASSERT(cpu != NULL);
2441
2442 if(cpu->exc_suspended > 0)
2443 sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n",
2444 cpu->exc_suspended, exception);
2445
2446 memcpy(cpu->exc_suspend_registers, cpu->registers, sizeof(cpu->exc_suspend_registers));
2447 memcpy(cpu->registers, cpu->exc_trigger_registers, sizeof(cpu->registers));
2448 cpu->exc_suspended = exception;
2449 }
2450
2451 void
2452 mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception)
2453 {
2454 ASSERT(cpu != NULL);
2455
2456 if(exception == 0 && cpu->exc_suspended > 0)
2457 {
2458 /* warn not for breakpoints */
2459 if(cpu->exc_suspended != sim_signal_to_host(sd, SIM_SIGTRAP))
2460 sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n",
2461 cpu->exc_suspended);
2462 }
2463 else if(exception != 0 && cpu->exc_suspended > 0)
2464 {
2465 if(exception != cpu->exc_suspended)
2466 sim_io_eprintf(sd, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
2467 cpu->exc_suspended, exception);
2468
2469 memcpy(cpu->registers, cpu->exc_suspend_registers, sizeof(cpu->registers));
2470 }
2471 else if(exception != 0 && cpu->exc_suspended == 0)
2472 {
2473 sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
2474 }
2475 cpu->exc_suspended = 0;
2476 }
2477
2478
2479 /*---------------------------------------------------------------------------*/
2480 /*> EOF interp.c <*/
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