4 // <insn-word> { "+" <insn-word> }
11 // { <insn-mnemonic> }
16 // IGEN config - mips16
17 // :option:16::insn-bit-size:16
18 // :option:16::hi-bit-nr:15
19 :option:16::insn-specifying-widths:true
20 :option:16::gen-delayed-branch:false
22 // IGEN config - mips32/64..
23 // :option:32::insn-bit-size:32
24 // :option:32::hi-bit-nr:31
25 :option:32::insn-specifying-widths:true
26 :option:32::gen-delayed-branch:false
29 // Generate separate simulators for each target
30 // :option:::multi-sim:true
33 // Models known by this simulator
34 :model:::mipsI:mips3000:
35 :model:::mipsII:mips6000:
36 :model:::mipsIII:mips4000:
37 :model:::mipsIV:mips8000:
38 :model:::mips16:mips16:
39 // start-sanitize-r5900
40 :model:::r5900:mips5900:
42 :model:::r3900:mips3900:
43 // start-sanitize-tx19
46 :model:::vr4100:mips4100:
47 // start-sanitize-vr4320
48 :model:::vr4320:mips4320:
49 // end-sanitize-vr4320
50 // start-sanitize-cygnus
51 :model:::vr5400:mips5400:
53 // end-sanitize-cygnus
54 :model:::vr5000:mips5000:
58 // Pseudo instructions known by IGEN
61 SignalException (ReservedInstruction, 0);
65 // Pseudo instructions known by interp.c
66 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
67 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
70 SignalException (ReservedInstruction, instruction_0);
77 // Simulate a 32 bit delayslot instruction
80 :function:::address_word:delayslot32:address_word target
82 instruction_word delay_insn;
83 sim_events_slip (SD, 1);
85 CIA = CIA + 4; /* NOTE not mips16 */
86 STATE |= simDELAYSLOT;
87 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
88 idecode_issue (CPU_, delay_insn, (CIA));
89 STATE &= ~simDELAYSLOT;
93 :function:::address_word:nullify_next_insn32:
95 sim_events_slip (SD, 1);
96 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
100 // start-sanitize-branchbug4011
101 :function:::void:check_4011_branch_bug:
103 if (BRANCHBUG4011_OPTION == 2 && BRANCHBUG4011_LAST_TARGET == CIA)
104 sim_engine_abort (SD, CPU, CIA, "4011 BRANCH BUG: %s at 0x%08lx was target of branch at 0x%08lx\n",
105 itable[MY_INDEX].name,
107 (long) BRANCHBUG4011_LAST_CIA);
110 :function:::void:mark_4011_branch_bug:address_word target
112 if (BRANCHBUG4011_OPTION)
114 BRANCHBUG4011_OPTION = 2;
115 BRANCHBUG4011_LAST_TARGET = target;
116 BRANCHBUG4011_LAST_CIA = CIA;
120 // end-sanitize-branchbug4011
123 // Check that an access to a HI/LO register meets timing requirements
125 // The following requirements exist:
127 // - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
128 // - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
129 // - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
130 // corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
133 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
135 if (history->mf.timestamp + 3 > time)
137 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
138 itable[MY_INDEX].name,
140 (long) history->mf.cia);
146 :function:::int:check_mt_hilo:hilo_history *history
147 *mipsI,mipsII,mipsIII,mipsIV:
149 // start-sanitize-vr4320
151 // end-sanitize-vr4320
152 // start-sanitize-cygnus
154 // end-sanitize-cygnus
156 signed64 time = sim_events_time (SD);
157 int ok = check_mf_cycles (SD_, history, time, "MT");
158 history->mt.timestamp = time;
159 history->mt.cia = CIA;
163 :function:::int:check_mt_hilo:hilo_history *history
165 // start-sanitize-tx19
168 // start-sanitize-r5900
170 // end-sanitize-r5900
172 signed64 time = sim_events_time (SD);
173 history->mt.timestamp = time;
174 history->mt.cia = CIA;
179 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
180 *mipsI,mipsII,mipsIII,mipsIV:
182 // start-sanitize-vr4320
184 // end-sanitize-vr4320
185 // start-sanitize-cygnus
187 // end-sanitize-cygnus
189 // start-sanitize-tx19
193 signed64 time = sim_events_time (SD);
196 && peer->mt.timestamp > history->op.timestamp
197 && history->mt.timestamp < history->op.timestamp
198 && ! (history->mf.timestamp > history->op.timestamp
199 && history->mf.timestamp < peer->mt.timestamp)
200 && ! (peer->mf.timestamp > history->op.timestamp
201 && peer->mf.timestamp < peer->mt.timestamp))
203 /* The peer has been written to since the last OP yet we have
205 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
206 itable[MY_INDEX].name,
208 (long) history->op.cia,
209 (long) peer->mt.cia);
212 history->mf.timestamp = time;
213 history->mf.cia = CIA;
217 // start-sanitize-r5900
218 // The r5900 mfhi et.al insns _can_ be exectuted immediatly after a div
219 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
220 // end-sanitize-r5900
221 // start-sanitize-r5900
223 // end-sanitize-r5900
224 // start-sanitize-r5900
226 /* FIXME: could record the fact that a stall occured if we want */
227 signed64 time = sim_events_time (SD);
228 history->mf.timestamp = time;
229 history->mf.cia = CIA;
232 // end-sanitize-r5900
235 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
236 *mipsI,mipsII,mipsIII,mipsIV:
238 // start-sanitize-vr4320
240 // end-sanitize-vr4320
241 // start-sanitize-cygnus
243 // end-sanitize-cygnus
245 signed64 time = sim_events_time (SD);
246 int ok = (check_mf_cycles (SD_, hi, time, "OP")
247 && check_mf_cycles (SD_, lo, time, "OP"));
248 hi->op.timestamp = time;
249 lo->op.timestamp = time;
255 // The r3900 mult and multu insns _can_ be exectuted immediatly after
257 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
259 // start-sanitize-tx19
262 // start-sanitize-r5900
264 // end-sanitize-r5900
266 /* FIXME: could record the fact that a stall occured if we want */
267 signed64 time = sim_events_time (SD);
268 hi->op.timestamp = time;
269 lo->op.timestamp = time;
276 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
277 *mipsI,mipsII,mipsIII,mipsIV:
279 // start-sanitize-vr4320
281 // end-sanitize-vr4320
282 // start-sanitize-cygnus
284 // end-sanitize-cygnus
286 // start-sanitize-tx19
290 signed64 time = sim_events_time (SD);
291 int ok = (check_mf_cycles (SD_, hi, time, "OP")
292 && check_mf_cycles (SD_, lo, time, "OP"));
293 hi->op.timestamp = time;
294 lo->op.timestamp = time;
301 // start-sanitize-r5900
302 // The r5900 div et.al insns _can_ be exectuted immediatly after
304 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
305 // end-sanitize-r5900
306 // start-sanitize-r5900
308 // end-sanitize-r5900
309 // start-sanitize-r5900
311 /* FIXME: could record the fact that a stall occured if we want */
312 signed64 time = sim_events_time (SD);
313 hi->op.timestamp = time;
314 lo->op.timestamp = time;
319 // end-sanitize-r5900
324 // Mips Architecture:
326 // CPU Instruction Set (mipsI - mipsIV)
331 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
332 "add r<RD>, r<RS>, r<RT>"
333 *mipsI,mipsII,mipsIII,mipsIV:
335 // start-sanitize-vr4320
337 // end-sanitize-vr4320
338 // start-sanitize-cygnus
340 // end-sanitize-cygnus
341 // start-sanitize-r5900
343 // end-sanitize-r5900
345 // start-sanitize-tx19
349 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
351 ALU32_BEGIN (GPR[RS]);
355 TRACE_ALU_RESULT (GPR[RD]);
360 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
361 "addi r<RT>, r<RS>, IMMEDIATE"
362 *mipsI,mipsII,mipsIII,mipsIV:
364 // start-sanitize-vr4320
366 // end-sanitize-vr4320
367 // start-sanitize-cygnus
369 // end-sanitize-cygnus
370 // start-sanitize-r5900
372 // end-sanitize-r5900
374 // start-sanitize-tx19
378 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
380 ALU32_BEGIN (GPR[RS]);
381 ALU32_ADD (EXTEND16 (IMMEDIATE));
384 TRACE_ALU_RESULT (GPR[RT]);
389 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
391 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
392 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
393 TRACE_ALU_RESULT (GPR[rt]);
396 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
397 "addiu r<RT>, r<RS>, <IMMEDIATE>"
398 *mipsI,mipsII,mipsIII,mipsIV:
400 // start-sanitize-vr4320
402 // end-sanitize-vr4320
403 // start-sanitize-cygnus
405 // end-sanitize-cygnus
406 // start-sanitize-r5900
408 // end-sanitize-r5900
410 // start-sanitize-tx19
414 do_addiu (SD_, RS, RT, IMMEDIATE);
419 :function:::void:do_addu:int rs, int rt, int rd
421 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
422 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
423 TRACE_ALU_RESULT (GPR[rd]);
426 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
427 "addu r<RD>, r<RS>, r<RT>"
428 *mipsI,mipsII,mipsIII,mipsIV:
430 // start-sanitize-vr4320
432 // end-sanitize-vr4320
433 // start-sanitize-cygnus
435 // end-sanitize-cygnus
436 // start-sanitize-r5900
438 // end-sanitize-r5900
440 // start-sanitize-tx19
444 do_addu (SD_, RS, RT, RD);
449 :function:::void:do_and:int rs, int rt, int rd
451 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
452 GPR[rd] = GPR[rs] & GPR[rt];
453 TRACE_ALU_RESULT (GPR[rd]);
456 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
457 "and r<RD>, r<RS>, r<RT>"
458 *mipsI,mipsII,mipsIII,mipsIV:
460 // start-sanitize-vr4320
462 // end-sanitize-vr4320
463 // start-sanitize-cygnus
465 // end-sanitize-cygnus
466 // start-sanitize-r5900
468 // end-sanitize-r5900
470 // start-sanitize-tx19
474 do_and (SD_, RS, RT, RD);
479 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
480 "and r<RT>, r<RS>, <IMMEDIATE>"
481 *mipsI,mipsII,mipsIII,mipsIV:
483 // start-sanitize-vr4320
485 // end-sanitize-vr4320
486 // start-sanitize-cygnus
488 // end-sanitize-cygnus
489 // start-sanitize-r5900
491 // end-sanitize-r5900
493 // start-sanitize-tx19
497 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
498 GPR[RT] = GPR[RS] & IMMEDIATE;
499 TRACE_ALU_RESULT (GPR[RT]);
504 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
505 "beq r<RS>, r<RT>, <OFFSET>"
506 *mipsI,mipsII,mipsIII,mipsIV:
508 // start-sanitize-vr4320
510 // end-sanitize-vr4320
511 // start-sanitize-cygnus
513 // end-sanitize-cygnus
514 // start-sanitize-r5900
516 // end-sanitize-r5900
518 // start-sanitize-tx19
522 address_word offset = EXTEND16 (OFFSET) << 2;
524 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
526 mark_branch_bug (NIA+offset);
527 DELAY_SLOT (NIA + offset);
533 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
534 "beql r<RS>, r<RT>, <OFFSET>"
539 // start-sanitize-vr4320
541 // end-sanitize-vr4320
542 // start-sanitize-cygnus
544 // end-sanitize-cygnus
545 // start-sanitize-r5900
547 // end-sanitize-r5900
549 // start-sanitize-tx19
553 address_word offset = EXTEND16 (OFFSET) << 2;
555 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
557 mark_branch_bug (NIA+offset);
558 DELAY_SLOT (NIA + offset);
561 NULLIFY_NEXT_INSTRUCTION ();
566 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
567 "bgez r<RS>, <OFFSET>"
568 *mipsI,mipsII,mipsIII,mipsIV:
570 // start-sanitize-vr4320
572 // end-sanitize-vr4320
573 // start-sanitize-cygnus
575 // end-sanitize-cygnus
576 // start-sanitize-r5900
578 // end-sanitize-r5900
580 // start-sanitize-tx19
584 address_word offset = EXTEND16 (OFFSET) << 2;
586 if ((signed_word) GPR[RS] >= 0)
588 mark_branch_bug (NIA+offset);
589 DELAY_SLOT (NIA + offset);
595 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
596 "bgezal r<RS>, <OFFSET>"
597 *mipsI,mipsII,mipsIII,mipsIV:
599 // start-sanitize-vr4320
601 // end-sanitize-vr4320
602 // start-sanitize-cygnus
604 // end-sanitize-cygnus
605 // start-sanitize-r5900
607 // end-sanitize-r5900
609 // start-sanitize-tx19
613 address_word offset = EXTEND16 (OFFSET) << 2;
616 if ((signed_word) GPR[RS] >= 0)
618 mark_branch_bug (NIA+offset);
619 DELAY_SLOT (NIA + offset);
625 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
626 "bgezall r<RS>, <OFFSET>"
631 // start-sanitize-vr4320
633 // end-sanitize-vr4320
634 // start-sanitize-cygnus
636 // end-sanitize-cygnus
637 // start-sanitize-r5900
639 // end-sanitize-r5900
641 // start-sanitize-tx19
645 address_word offset = EXTEND16 (OFFSET) << 2;
648 /* NOTE: The branch occurs AFTER the next instruction has been
650 if ((signed_word) GPR[RS] >= 0)
652 mark_branch_bug (NIA+offset);
653 DELAY_SLOT (NIA + offset);
656 NULLIFY_NEXT_INSTRUCTION ();
661 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
662 "bgezl r<RS>, <OFFSET>"
667 // start-sanitize-vr4320
669 // end-sanitize-vr4320
670 // start-sanitize-cygnus
672 // end-sanitize-cygnus
673 // start-sanitize-r5900
675 // end-sanitize-r5900
677 // start-sanitize-tx19
681 address_word offset = EXTEND16 (OFFSET) << 2;
683 if ((signed_word) GPR[RS] >= 0)
685 mark_branch_bug (NIA+offset);
686 DELAY_SLOT (NIA + offset);
689 NULLIFY_NEXT_INSTRUCTION ();
694 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
695 "bgtz r<RS>, <OFFSET>"
696 *mipsI,mipsII,mipsIII,mipsIV:
698 // start-sanitize-vr4320
700 // end-sanitize-vr4320
701 // start-sanitize-cygnus
703 // end-sanitize-cygnus
704 // start-sanitize-r5900
706 // end-sanitize-r5900
708 // start-sanitize-tx19
712 address_word offset = EXTEND16 (OFFSET) << 2;
714 if ((signed_word) GPR[RS] > 0)
716 mark_branch_bug (NIA+offset);
717 DELAY_SLOT (NIA + offset);
723 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
724 "bgtzl r<RS>, <OFFSET>"
729 // start-sanitize-vr4320
731 // end-sanitize-vr4320
732 // start-sanitize-cygnus
734 // end-sanitize-cygnus
735 // start-sanitize-r5900
737 // end-sanitize-r5900
739 // start-sanitize-tx19
743 address_word offset = EXTEND16 (OFFSET) << 2;
745 /* NOTE: The branch occurs AFTER the next instruction has been
747 if ((signed_word) GPR[RS] > 0)
749 mark_branch_bug (NIA+offset);
750 DELAY_SLOT (NIA + offset);
753 NULLIFY_NEXT_INSTRUCTION ();
758 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
759 "blez r<RS>, <OFFSET>"
760 *mipsI,mipsII,mipsIII,mipsIV:
762 // start-sanitize-vr4320
764 // end-sanitize-vr4320
765 // start-sanitize-cygnus
767 // end-sanitize-cygnus
768 // start-sanitize-r5900
770 // end-sanitize-r5900
772 // start-sanitize-tx19
776 address_word offset = EXTEND16 (OFFSET) << 2;
778 /* NOTE: The branch occurs AFTER the next instruction has been
780 if ((signed_word) GPR[RS] <= 0)
782 mark_branch_bug (NIA+offset);
783 DELAY_SLOT (NIA + offset);
789 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
790 "bgezl r<RS>, <OFFSET>"
795 // start-sanitize-vr4320
797 // end-sanitize-vr4320
798 // start-sanitize-cygnus
800 // end-sanitize-cygnus
801 // start-sanitize-r5900
803 // end-sanitize-r5900
805 // start-sanitize-tx19
809 address_word offset = EXTEND16 (OFFSET) << 2;
811 if ((signed_word) GPR[RS] <= 0)
813 mark_branch_bug (NIA+offset);
814 DELAY_SLOT (NIA + offset);
817 NULLIFY_NEXT_INSTRUCTION ();
822 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
823 "bltz r<RS>, <OFFSET>"
824 *mipsI,mipsII,mipsIII,mipsIV:
826 // start-sanitize-vr4320
828 // end-sanitize-vr4320
829 // start-sanitize-cygnus
831 // end-sanitize-cygnus
832 // start-sanitize-r5900
834 // end-sanitize-r5900
836 // start-sanitize-tx19
840 address_word offset = EXTEND16 (OFFSET) << 2;
842 if ((signed_word) GPR[RS] < 0)
844 mark_branch_bug (NIA+offset);
845 DELAY_SLOT (NIA + offset);
851 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
852 "bltzal r<RS>, <OFFSET>"
853 *mipsI,mipsII,mipsIII,mipsIV:
855 // start-sanitize-vr4320
857 // end-sanitize-vr4320
858 // start-sanitize-cygnus
860 // end-sanitize-cygnus
861 // start-sanitize-r5900
863 // end-sanitize-r5900
865 // start-sanitize-tx19
869 address_word offset = EXTEND16 (OFFSET) << 2;
872 /* NOTE: The branch occurs AFTER the next instruction has been
874 if ((signed_word) GPR[RS] < 0)
876 mark_branch_bug (NIA+offset);
877 DELAY_SLOT (NIA + offset);
883 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
884 "bltzall r<RS>, <OFFSET>"
889 // start-sanitize-vr4320
891 // end-sanitize-vr4320
892 // start-sanitize-cygnus
894 // end-sanitize-cygnus
895 // start-sanitize-r5900
897 // end-sanitize-r5900
899 // start-sanitize-tx19
903 address_word offset = EXTEND16 (OFFSET) << 2;
906 if ((signed_word) GPR[RS] < 0)
908 mark_branch_bug (NIA+offset);
909 DELAY_SLOT (NIA + offset);
912 NULLIFY_NEXT_INSTRUCTION ();
917 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
918 "bltzl r<RS>, <OFFSET>"
923 // start-sanitize-vr4320
925 // end-sanitize-vr4320
926 // start-sanitize-cygnus
928 // end-sanitize-cygnus
929 // start-sanitize-r5900
931 // end-sanitize-r5900
933 // start-sanitize-tx19
937 address_word offset = EXTEND16 (OFFSET) << 2;
939 /* NOTE: The branch occurs AFTER the next instruction has been
941 if ((signed_word) GPR[RS] < 0)
943 mark_branch_bug (NIA+offset);
944 DELAY_SLOT (NIA + offset);
947 NULLIFY_NEXT_INSTRUCTION ();
952 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
953 "bne r<RS>, r<RT>, <OFFSET>"
954 *mipsI,mipsII,mipsIII,mipsIV:
956 // start-sanitize-vr4320
958 // end-sanitize-vr4320
959 // start-sanitize-cygnus
961 // end-sanitize-cygnus
962 // start-sanitize-r5900
964 // end-sanitize-r5900
966 // start-sanitize-tx19
970 address_word offset = EXTEND16 (OFFSET) << 2;
972 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
974 mark_branch_bug (NIA+offset);
975 DELAY_SLOT (NIA + offset);
981 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
982 "bnel r<RS>, r<RT>, <OFFSET>"
987 // start-sanitize-vr4320
989 // end-sanitize-vr4320
990 // start-sanitize-cygnus
992 // end-sanitize-cygnus
993 // start-sanitize-r5900
995 // end-sanitize-r5900
997 // start-sanitize-tx19
1001 address_word offset = EXTEND16 (OFFSET) << 2;
1002 check_branch_bug ();
1003 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1005 mark_branch_bug (NIA+offset);
1006 DELAY_SLOT (NIA + offset);
1009 NULLIFY_NEXT_INSTRUCTION ();
1014 000000,20.CODE,001101:SPECIAL:32::BREAK
1016 *mipsI,mipsII,mipsIII,mipsIV:
1018 // start-sanitize-vr4320
1020 // end-sanitize-vr4320
1021 // start-sanitize-cygnus
1023 // end-sanitize-cygnus
1024 // start-sanitize-r5900
1026 // end-sanitize-r5900
1028 // start-sanitize-tx19
1030 // end-sanitize-tx19
1032 /* Check for some break instruction which are reserved for use by the simulator. */
1033 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1034 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
1035 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1037 sim_engine_halt (SD, CPU, NULL, cia,
1038 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1040 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
1041 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1043 if (STATE & simDELAYSLOT)
1044 PC = cia - 4; /* reference the branch instruction */
1047 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1049 // start-sanitize-sky
1050 else if (break_code == (HALT_INSTRUCTION_PASS & HALT_INSTRUCTION_MASK))
1052 sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 0);
1054 else if (break_code == (HALT_INSTRUCTION_FAIL & HALT_INSTRUCTION_MASK))
1056 sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 15);
1060 /* If we get this far, we're not an instruction reserved by the sim. Raise
1062 SignalException(BreakPoint, instruction_0);
1070 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1071 "dadd r<RD>, r<RS>, r<RT>"
1075 // start-sanitize-vr4320
1077 // end-sanitize-vr4320
1078 // start-sanitize-cygnus
1080 // end-sanitize-cygnus
1081 // start-sanitize-r5900
1083 // end-sanitize-r5900
1084 // start-sanitize-tx19
1086 // end-sanitize-tx19
1088 /* this check's for overflow */
1089 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1091 ALU64_BEGIN (GPR[RS]);
1092 ALU64_ADD (GPR[RT]);
1093 ALU64_END (GPR[RD]);
1095 TRACE_ALU_RESULT (GPR[RD]);
1100 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1101 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1105 // start-sanitize-vr4320
1107 // end-sanitize-vr4320
1108 // start-sanitize-cygnus
1110 // end-sanitize-cygnus
1111 // start-sanitize-r5900
1113 // end-sanitize-r5900
1114 // start-sanitize-tx19
1116 // end-sanitize-tx19
1118 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1120 ALU64_BEGIN (GPR[RS]);
1121 ALU64_ADD (EXTEND16 (IMMEDIATE));
1122 ALU64_END (GPR[RT]);
1124 TRACE_ALU_RESULT (GPR[RT]);
1129 :function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
1131 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1132 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1133 TRACE_ALU_RESULT (GPR[rt]);
1136 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1137 "daddu r<RT>, r<RS>, <IMMEDIATE>"
1141 // start-sanitize-vr4320
1143 // end-sanitize-vr4320
1144 // start-sanitize-cygnus
1146 // end-sanitize-cygnus
1147 // start-sanitize-r5900
1149 // end-sanitize-r5900
1150 // start-sanitize-tx19
1152 // end-sanitize-tx19
1154 do_daddiu (SD_, RS, RT, IMMEDIATE);
1159 :function:::void:do_daddu:int rs, int rt, int rd
1161 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1162 GPR[rd] = GPR[rs] + GPR[rt];
1163 TRACE_ALU_RESULT (GPR[rd]);
1166 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1167 "daddu r<RD>, r<RS>, r<RT>"
1171 // start-sanitize-vr4320
1173 // end-sanitize-vr4320
1174 // start-sanitize-cygnus
1176 // end-sanitize-cygnus
1177 // start-sanitize-r5900
1179 // end-sanitize-r5900
1180 // start-sanitize-tx19
1182 // end-sanitize-tx19
1184 do_daddu (SD_, RS, RT, RD);
1189 :function:64::void:do_ddiv:int rs, int rt
1191 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1192 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1194 signed64 n = GPR[rs];
1195 signed64 d = GPR[rt];
1198 LO = SIGNED64 (0x8000000000000000);
1201 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1203 LO = SIGNED64 (0x8000000000000000);
1212 TRACE_ALU_RESULT2 (HI, LO);
1215 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
1220 // start-sanitize-vr4320
1222 // end-sanitize-vr4320
1223 // start-sanitize-cygnus
1225 // end-sanitize-cygnus
1226 // start-sanitize-r5900
1228 // end-sanitize-r5900
1229 // start-sanitize-tx19
1231 // end-sanitize-tx19
1233 do_ddiv (SD_, RS, RT);
1238 :function:64::void:do_ddivu:int rs, int rt
1240 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1241 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1243 unsigned64 n = GPR[rs];
1244 unsigned64 d = GPR[rt];
1247 LO = SIGNED64 (0x8000000000000000);
1256 TRACE_ALU_RESULT2 (HI, LO);
1259 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1260 "ddivu r<RS>, r<RT>"
1264 // start-sanitize-vr4320
1266 // end-sanitize-vr4320
1267 // start-sanitize-cygnus
1269 // end-sanitize-cygnus
1270 // start-sanitize-tx19
1272 // end-sanitize-tx19
1274 do_ddivu (SD_, RS, RT);
1279 :function:::void:do_div:int rs, int rt
1281 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1282 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1284 signed32 n = GPR[rs];
1285 signed32 d = GPR[rt];
1288 LO = EXTEND32 (0x80000000);
1291 else if (n == SIGNED32 (0x80000000) && d == -1)
1293 LO = EXTEND32 (0x80000000);
1298 LO = EXTEND32 (n / d);
1299 HI = EXTEND32 (n % d);
1302 TRACE_ALU_RESULT2 (HI, LO);
1305 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
1307 *mipsI,mipsII,mipsIII,mipsIV:
1309 // start-sanitize-vr4320
1311 // end-sanitize-vr4320
1312 // start-sanitize-cygnus
1314 // end-sanitize-cygnus
1315 // start-sanitize-r5900
1317 // end-sanitize-r5900
1319 // start-sanitize-tx19
1321 // end-sanitize-tx19
1323 do_div (SD_, RS, RT);
1328 :function:::void:do_divu:int rs, int rt
1330 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1331 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1333 unsigned32 n = GPR[rs];
1334 unsigned32 d = GPR[rt];
1337 LO = EXTEND32 (0x80000000);
1342 LO = EXTEND32 (n / d);
1343 HI = EXTEND32 (n % d);
1346 TRACE_ALU_RESULT2 (HI, LO);
1349 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1351 *mipsI,mipsII,mipsIII,mipsIV:
1353 // start-sanitize-vr4320
1355 // end-sanitize-vr4320
1356 // start-sanitize-cygnus
1358 // end-sanitize-cygnus
1359 // start-sanitize-r5900
1361 // end-sanitize-r5900
1363 // start-sanitize-tx19
1365 // end-sanitize-tx19
1367 do_divu (SD_, RS, RT);
1372 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1382 unsigned64 op1 = GPR[rs];
1383 unsigned64 op2 = GPR[rt];
1384 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1385 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1386 /* make signed multiply unsigned */
1401 /* multuply out the 4 sub products */
1402 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1403 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1404 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1405 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1406 /* add the products */
1407 mid = ((unsigned64) VH4_8 (m00)
1408 + (unsigned64) VL4_8 (m10)
1409 + (unsigned64) VL4_8 (m01));
1410 lo = U8_4 (mid, m00);
1412 + (unsigned64) VH4_8 (mid)
1413 + (unsigned64) VH4_8 (m01)
1414 + (unsigned64) VH4_8 (m10));
1424 /* save the result HI/LO (and a gpr) */
1429 TRACE_ALU_RESULT2 (HI, LO);
1432 :function:::void:do_dmult:int rs, int rt, int rd
1434 do_dmultx (SD_, rs, rt, rd, 1);
1437 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1438 "dmult r<RS>, r<RT>"
1440 // start-sanitize-tx19
1442 // end-sanitize-tx19
1443 // start-sanitize-vr4320
1445 // end-sanitize-vr4320
1447 do_dmult (SD_, RS, RT, 0);
1450 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1451 "dmult r<RS>, r<RT>":RD == 0
1452 "dmult r<RD>, r<RS>, r<RT>"
1454 // start-sanitize-cygnus
1456 // end-sanitize-cygnus
1458 do_dmult (SD_, RS, RT, RD);
1463 :function:::void:do_dmultu:int rs, int rt, int rd
1465 do_dmultx (SD_, rs, rt, rd, 0);
1468 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1469 "dmultu r<RS>, r<RT>"
1471 // start-sanitize-tx19
1473 // end-sanitize-tx19
1474 // start-sanitize-vr4320
1476 // end-sanitize-vr4320
1478 do_dmultu (SD_, RS, RT, 0);
1481 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1482 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1483 "dmultu r<RS>, r<RT>"
1485 // start-sanitize-cygnus
1487 // end-sanitize-cygnus
1489 do_dmultu (SD_, RS, RT, RD);
1494 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1495 "dsll r<RD>, r<RT>, <SHIFT>"
1499 // start-sanitize-vr4320
1501 // end-sanitize-vr4320
1502 // start-sanitize-cygnus
1504 // end-sanitize-cygnus
1505 // start-sanitize-r5900
1507 // end-sanitize-r5900
1508 // start-sanitize-tx19
1510 // end-sanitize-tx19
1513 GPR[RD] = GPR[RT] << s;
1517 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1518 "dsll32 r<RD>, r<RT>, <SHIFT>"
1522 // start-sanitize-vr4320
1524 // end-sanitize-vr4320
1525 // start-sanitize-cygnus
1527 // end-sanitize-cygnus
1528 // start-sanitize-r5900
1530 // end-sanitize-r5900
1531 // start-sanitize-tx19
1533 // end-sanitize-tx19
1536 GPR[RD] = GPR[RT] << s;
1541 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1542 "dsllv r<RD>, r<RT>, r<RS>"
1546 // start-sanitize-vr4320
1548 // end-sanitize-vr4320
1549 // start-sanitize-cygnus
1551 // end-sanitize-cygnus
1552 // start-sanitize-r5900
1554 // end-sanitize-r5900
1555 // start-sanitize-tx19
1557 // end-sanitize-tx19
1559 int s = MASKED64 (GPR[RS], 5, 0);
1560 GPR[RD] = GPR[RT] << s;
1565 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1566 "dsra r<RD>, r<RT>, <SHIFT>"
1570 // start-sanitize-vr4320
1572 // end-sanitize-vr4320
1573 // start-sanitize-cygnus
1575 // end-sanitize-cygnus
1576 // start-sanitize-r5900
1578 // end-sanitize-r5900
1579 // start-sanitize-tx19
1581 // end-sanitize-tx19
1584 GPR[RD] = ((signed64) GPR[RT]) >> s;
1588 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1589 "dsra32 r<RT>, r<RD>, <SHIFT>"
1593 // start-sanitize-vr4320
1595 // end-sanitize-vr4320
1596 // start-sanitize-cygnus
1598 // end-sanitize-cygnus
1599 // start-sanitize-r5900
1601 // end-sanitize-r5900
1602 // start-sanitize-tx19
1604 // end-sanitize-tx19
1607 GPR[RD] = ((signed64) GPR[RT]) >> s;
1611 :function:::void:do_dsrav:int rs, int rt, int rd
1613 int s = MASKED64 (GPR[rs], 5, 0);
1614 TRACE_ALU_INPUT2 (GPR[rt], s);
1615 GPR[rd] = ((signed64) GPR[rt]) >> s;
1616 TRACE_ALU_RESULT (GPR[rd]);
1619 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1620 "dsra32 r<RT>, r<RD>, r<RS>"
1624 // start-sanitize-vr4320
1626 // end-sanitize-vr4320
1627 // start-sanitize-cygnus
1629 // end-sanitize-cygnus
1630 // start-sanitize-r5900
1632 // end-sanitize-r5900
1633 // start-sanitize-tx19
1635 // end-sanitize-tx19
1637 do_dsrav (SD_, RS, RT, RD);
1641 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1642 "dsrl r<RD>, r<RT>, <SHIFT>"
1646 // start-sanitize-vr4320
1648 // end-sanitize-vr4320
1649 // start-sanitize-cygnus
1651 // end-sanitize-cygnus
1652 // start-sanitize-r5900
1654 // end-sanitize-r5900
1655 // start-sanitize-tx19
1657 // end-sanitize-tx19
1660 GPR[RD] = (unsigned64) GPR[RT] >> s;
1664 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1665 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1669 // start-sanitize-vr4320
1671 // end-sanitize-vr4320
1672 // start-sanitize-cygnus
1674 // end-sanitize-cygnus
1675 // start-sanitize-r5900
1677 // end-sanitize-r5900
1678 // start-sanitize-tx19
1680 // end-sanitize-tx19
1683 GPR[RD] = (unsigned64) GPR[RT] >> s;
1687 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1688 "dsrl32 r<RD>, r<RT>, r<RS>"
1692 // start-sanitize-vr4320
1694 // end-sanitize-vr4320
1695 // start-sanitize-cygnus
1697 // end-sanitize-cygnus
1698 // start-sanitize-r5900
1700 // end-sanitize-r5900
1701 // start-sanitize-tx19
1703 // end-sanitize-tx19
1705 int s = MASKED64 (GPR[RS], 5, 0);
1706 GPR[RD] = (unsigned64) GPR[RT] >> s;
1710 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1711 "dsub r<RD>, r<RS>, r<RT>"
1715 // start-sanitize-vr4320
1717 // end-sanitize-vr4320
1718 // start-sanitize-cygnus
1720 // end-sanitize-cygnus
1721 // start-sanitize-r5900
1723 // end-sanitize-r5900
1724 // start-sanitize-tx19
1726 // end-sanitize-tx19
1728 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1730 ALU64_BEGIN (GPR[RS]);
1731 ALU64_SUB (GPR[RT]);
1732 ALU64_END (GPR[RD]);
1734 TRACE_ALU_RESULT (GPR[RD]);
1738 :function:::void:do_dsubu:int rs, int rt, int rd
1740 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1741 GPR[rd] = GPR[rs] - GPR[rt];
1742 TRACE_ALU_RESULT (GPR[rd]);
1745 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1746 "dsubu r<RD>, r<RS>, r<RT>"
1750 // start-sanitize-vr4320
1752 // end-sanitize-vr4320
1753 // start-sanitize-cygnus
1755 // end-sanitize-cygnus
1756 // start-sanitize-r5900
1758 // end-sanitize-r5900
1759 // start-sanitize-tx19
1761 // end-sanitize-tx19
1763 do_dsubu (SD_, RS, RT, RD);
1767 000010,26.INSTR_INDEX:NORMAL:32::J
1769 *mipsI,mipsII,mipsIII,mipsIV:
1771 // start-sanitize-vr4320
1773 // end-sanitize-vr4320
1774 // start-sanitize-cygnus
1776 // end-sanitize-cygnus
1777 // start-sanitize-r5900
1779 // end-sanitize-r5900
1781 // start-sanitize-tx19
1783 // end-sanitize-tx19
1785 /* NOTE: The region used is that of the delay slot NIA and NOT the
1786 current instruction */
1787 address_word region = (NIA & MASK (63, 28));
1788 DELAY_SLOT (region | (INSTR_INDEX << 2));
1792 000011,26.INSTR_INDEX:NORMAL:32::JAL
1794 *mipsI,mipsII,mipsIII,mipsIV:
1796 // start-sanitize-vr4320
1798 // end-sanitize-vr4320
1799 // start-sanitize-cygnus
1801 // end-sanitize-cygnus
1802 // start-sanitize-r5900
1804 // end-sanitize-r5900
1806 // start-sanitize-tx19
1808 // end-sanitize-tx19
1810 /* NOTE: The region used is that of the delay slot and NOT the
1811 current instruction */
1812 address_word region = (NIA & MASK (63, 28));
1814 DELAY_SLOT (region | (INSTR_INDEX << 2));
1818 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1819 "jalr r<RS>":RD == 31
1821 *mipsI,mipsII,mipsIII,mipsIV:
1823 // start-sanitize-vr4320
1825 // end-sanitize-vr4320
1826 // start-sanitize-cygnus
1828 // end-sanitize-cygnus
1829 // start-sanitize-r5900
1831 // end-sanitize-r5900
1833 // start-sanitize-tx19
1835 // end-sanitize-tx19
1837 address_word temp = GPR[RS];
1843 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1845 *mipsI,mipsII,mipsIII,mipsIV:
1847 // start-sanitize-vr4320
1849 // end-sanitize-vr4320
1850 // start-sanitize-cygnus
1852 // end-sanitize-cygnus
1853 // start-sanitize-r5900
1855 // end-sanitize-r5900
1857 // start-sanitize-tx19
1859 // end-sanitize-tx19
1861 DELAY_SLOT (GPR[RS]);
1865 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1867 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1868 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1869 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1876 vaddr = base + offset;
1877 if ((vaddr & access) != 0)
1878 SignalExceptionAddressLoad ();
1879 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1880 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1881 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1882 byte = ((vaddr & mask) ^ bigendiancpu);
1883 return (memval >> (8 * byte));
1887 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1888 "lb r<RT>, <OFFSET>(r<BASE>)"
1889 *mipsI,mipsII,mipsIII,mipsIV:
1891 // start-sanitize-vr4320
1893 // end-sanitize-vr4320
1894 // start-sanitize-cygnus
1896 // end-sanitize-cygnus
1897 // start-sanitize-r5900
1899 // end-sanitize-r5900
1901 // start-sanitize-tx19
1903 // end-sanitize-tx19
1905 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1909 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1910 "lbu r<RT>, <OFFSET>(r<BASE>)"
1911 *mipsI,mipsII,mipsIII,mipsIV:
1913 // start-sanitize-vr4320
1915 // end-sanitize-vr4320
1916 // start-sanitize-cygnus
1918 // end-sanitize-cygnus
1919 // start-sanitize-r5900
1921 // end-sanitize-r5900
1923 // start-sanitize-tx19
1925 // end-sanitize-tx19
1927 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1931 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1932 "ld r<RT>, <OFFSET>(r<BASE>)"
1936 // start-sanitize-vr4320
1938 // end-sanitize-vr4320
1939 // start-sanitize-cygnus
1941 // end-sanitize-cygnus
1942 // start-sanitize-r5900
1944 // end-sanitize-r5900
1945 // start-sanitize-tx19
1947 // end-sanitize-tx19
1949 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1953 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1954 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1959 // start-sanitize-vr4320
1961 // end-sanitize-vr4320
1962 // start-sanitize-cygnus
1964 // end-sanitize-cygnus
1966 // start-sanitize-tx19
1968 // end-sanitize-tx19
1970 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1976 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1977 "ldl r<RT>, <OFFSET>(r<BASE>)"
1981 // start-sanitize-vr4320
1983 // end-sanitize-vr4320
1984 // start-sanitize-cygnus
1986 // end-sanitize-cygnus
1987 // start-sanitize-r5900
1989 // end-sanitize-r5900
1990 // start-sanitize-tx19
1992 // end-sanitize-tx19
1994 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1998 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1999 "ldr r<RT>, <OFFSET>(r<BASE>)"
2003 // start-sanitize-vr4320
2005 // end-sanitize-vr4320
2006 // start-sanitize-cygnus
2008 // end-sanitize-cygnus
2009 // start-sanitize-r5900
2011 // end-sanitize-r5900
2012 // start-sanitize-tx19
2014 // end-sanitize-tx19
2016 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2020 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2021 "lh r<RT>, <OFFSET>(r<BASE>)"
2022 *mipsI,mipsII,mipsIII,mipsIV:
2024 // start-sanitize-vr4320
2026 // end-sanitize-vr4320
2027 // start-sanitize-cygnus
2029 // end-sanitize-cygnus
2030 // start-sanitize-r5900
2032 // end-sanitize-r5900
2034 // start-sanitize-tx19
2036 // end-sanitize-tx19
2038 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2042 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2043 "lhu r<RT>, <OFFSET>(r<BASE>)"
2044 *mipsI,mipsII,mipsIII,mipsIV:
2046 // start-sanitize-vr4320
2048 // end-sanitize-vr4320
2049 // start-sanitize-cygnus
2051 // end-sanitize-cygnus
2052 // start-sanitize-r5900
2054 // end-sanitize-r5900
2056 // start-sanitize-tx19
2058 // end-sanitize-tx19
2060 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2064 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2065 "ll r<RT>, <OFFSET>(r<BASE>)"
2070 // start-sanitize-vr4320
2072 // end-sanitize-vr4320
2073 // start-sanitize-cygnus
2075 // end-sanitize-cygnus
2076 // start-sanitize-r5900
2078 // end-sanitize-r5900
2079 // start-sanitize-tx19
2081 // end-sanitize-tx19
2083 unsigned32 instruction = instruction_0;
2084 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2085 int destreg = ((instruction >> 16) & 0x0000001F);
2086 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2088 address_word vaddr = ((unsigned64)op1 + offset);
2091 if ((vaddr & 3) != 0)
2092 SignalExceptionAddressLoad();
2095 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2097 unsigned64 memval = 0;
2098 unsigned64 memval1 = 0;
2099 unsigned64 mask = 0x7;
2100 unsigned int shift = 2;
2101 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2102 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2104 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2105 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2106 byte = ((vaddr & mask) ^ (bigend << shift));
2107 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
2115 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2116 "lld r<RT>, <OFFSET>(r<BASE>)"
2120 // start-sanitize-vr4320
2122 // end-sanitize-vr4320
2123 // start-sanitize-cygnus
2125 // end-sanitize-cygnus
2126 // start-sanitize-r5900
2128 // end-sanitize-r5900
2129 // start-sanitize-tx19
2131 // end-sanitize-tx19
2133 unsigned32 instruction = instruction_0;
2134 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2135 int destreg = ((instruction >> 16) & 0x0000001F);
2136 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2138 address_word vaddr = ((unsigned64)op1 + offset);
2141 if ((vaddr & 7) != 0)
2142 SignalExceptionAddressLoad();
2145 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2147 unsigned64 memval = 0;
2148 unsigned64 memval1 = 0;
2149 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2150 GPR[destreg] = memval;
2158 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2159 "lui r<RT>, <IMMEDIATE>"
2160 *mipsI,mipsII,mipsIII,mipsIV:
2162 // start-sanitize-vr4320
2164 // end-sanitize-vr4320
2165 // start-sanitize-cygnus
2167 // end-sanitize-cygnus
2168 // start-sanitize-r5900
2170 // end-sanitize-r5900
2172 // start-sanitize-tx19
2174 // end-sanitize-tx19
2176 TRACE_ALU_INPUT1 (IMMEDIATE);
2177 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2178 TRACE_ALU_RESULT (GPR[RT]);
2182 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2183 "lw r<RT>, <OFFSET>(r<BASE>)"
2184 *mipsI,mipsII,mipsIII,mipsIV:
2186 // start-sanitize-vr4320
2188 // end-sanitize-vr4320
2189 // start-sanitize-cygnus
2191 // end-sanitize-cygnus
2192 // start-sanitize-r5900
2194 // end-sanitize-r5900
2196 // start-sanitize-tx19
2198 // end-sanitize-tx19
2200 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2204 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2205 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2206 *mipsI,mipsII,mipsIII,mipsIV:
2208 // start-sanitize-vr4320
2210 // end-sanitize-vr4320
2211 // start-sanitize-cygnus
2213 // end-sanitize-cygnus
2214 // start-sanitize-r5900
2216 // end-sanitize-r5900
2218 // start-sanitize-tx19
2220 // end-sanitize-tx19
2222 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2226 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2228 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2229 address_word reverseendian = (ReverseEndian ? -1 : 0);
2230 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2239 unsigned_word lhs_mask;
2242 vaddr = base + offset;
2243 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2244 paddr = (paddr ^ (reverseendian & mask));
2245 if (BigEndianMem == 0)
2246 paddr = paddr & ~access;
2248 /* compute where within the word/mem we are */
2249 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2250 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2251 nr_lhs_bits = 8 * byte + 8;
2252 nr_rhs_bits = 8 * access - 8 * byte;
2253 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2255 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2256 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2257 (long) ((unsigned64) paddr >> 32), (long) paddr,
2258 word, byte, nr_lhs_bits, nr_rhs_bits); */
2260 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2263 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2264 temp = (memval << nr_rhs_bits);
2268 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2269 temp = (memval >> nr_lhs_bits);
2271 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2272 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2274 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2275 (long) ((unsigned64) memval >> 32), (long) memval,
2276 (long) ((unsigned64) temp >> 32), (long) temp,
2277 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2278 (long) (rt >> 32), (long) rt); */
2283 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2284 "lwl r<RT>, <OFFSET>(r<BASE>)"
2285 *mipsI,mipsII,mipsIII,mipsIV:
2287 // start-sanitize-vr4320
2289 // end-sanitize-vr4320
2290 // start-sanitize-cygnus
2292 // end-sanitize-cygnus
2293 // start-sanitize-r5900
2295 // end-sanitize-r5900
2297 // start-sanitize-tx19
2299 // end-sanitize-tx19
2301 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
2305 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2307 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2308 address_word reverseendian = (ReverseEndian ? -1 : 0);
2309 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2316 vaddr = base + offset;
2317 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2318 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2319 paddr = (paddr ^ (reverseendian & mask));
2320 if (BigEndianMem != 0)
2321 paddr = paddr & ~access;
2322 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2323 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
2324 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2325 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2326 (long) paddr, byte, (long) paddr, (long) memval); */
2328 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2330 rt |= (memval >> (8 * byte)) & screen;
2336 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2337 "lwr r<RT>, <OFFSET>(r<BASE>)"
2338 *mipsI,mipsII,mipsIII,mipsIV:
2340 // start-sanitize-vr4320
2342 // end-sanitize-vr4320
2343 // start-sanitize-cygnus
2345 // end-sanitize-cygnus
2346 // start-sanitize-r5900
2348 // end-sanitize-r5900
2350 // start-sanitize-tx19
2352 // end-sanitize-tx19
2354 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2358 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2359 "lwu r<RT>, <OFFSET>(r<BASE>)"
2363 // start-sanitize-vr4320
2365 // end-sanitize-vr4320
2366 // start-sanitize-cygnus
2368 // end-sanitize-cygnus
2369 // start-sanitize-r5900
2371 // end-sanitize-r5900
2372 // start-sanitize-tx19
2374 // end-sanitize-tx19
2376 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2380 :function:::void:do_mfhi:int rd
2382 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2383 TRACE_ALU_INPUT1 (HI);
2385 TRACE_ALU_RESULT (GPR[rd]);
2388 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2390 *mipsI,mipsII,mipsIII,mipsIV:
2392 // start-sanitize-vr4320
2394 // end-sanitize-vr4320
2395 // start-sanitize-cygnus
2397 // end-sanitize-cygnus
2398 // start-sanitize-r5900
2400 // end-sanitize-r5900
2402 // start-sanitize-tx19
2404 // end-sanitize-tx19
2411 :function:::void:do_mflo:int rd
2413 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2414 TRACE_ALU_INPUT1 (LO);
2416 TRACE_ALU_RESULT (GPR[rd]);
2419 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2421 *mipsI,mipsII,mipsIII,mipsIV:
2423 // start-sanitize-vr4320
2425 // end-sanitize-vr4320
2426 // start-sanitize-cygnus
2428 // end-sanitize-cygnus
2429 // start-sanitize-r5900
2431 // end-sanitize-r5900
2433 // start-sanitize-tx19
2435 // end-sanitize-tx19
2442 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2443 "movn r<RD>, r<RS>, r<RT>"
2446 // start-sanitize-vr4320
2448 // end-sanitize-vr4320
2449 // start-sanitize-cygnus
2451 // end-sanitize-cygnus
2452 // start-sanitize-r5900
2454 // end-sanitize-r5900
2462 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2463 "movz r<RD>, r<RS>, r<RT>"
2466 // start-sanitize-vr4320
2468 // end-sanitize-vr4320
2469 // start-sanitize-cygnus
2471 // end-sanitize-cygnus
2472 // start-sanitize-r5900
2474 // end-sanitize-r5900
2482 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2484 *mipsI,mipsII,mipsIII,mipsIV:
2486 // start-sanitize-vr4320
2488 // end-sanitize-vr4320
2489 // start-sanitize-cygnus
2491 // end-sanitize-cygnus
2492 // start-sanitize-r5900
2494 // end-sanitize-r5900
2496 // start-sanitize-tx19
2498 // end-sanitize-tx19
2500 check_mt_hilo (SD_, HIHISTORY);
2506 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2508 *mipsI,mipsII,mipsIII,mipsIV:
2510 // start-sanitize-vr4320
2512 // end-sanitize-vr4320
2513 // start-sanitize-cygnus
2515 // end-sanitize-cygnus
2516 // start-sanitize-r5900
2518 // end-sanitize-r5900
2520 // start-sanitize-tx19
2522 // end-sanitize-tx19
2524 check_mt_hilo (SD_, LOHISTORY);
2530 :function:::void:do_mult:int rs, int rt, int rd
2533 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2534 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2535 prod = (((signed64)(signed32) GPR[rs])
2536 * ((signed64)(signed32) GPR[rt]));
2537 LO = EXTEND32 (VL4_8 (prod));
2538 HI = EXTEND32 (VH4_8 (prod));
2541 TRACE_ALU_RESULT2 (HI, LO);
2544 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2546 *mipsI,mipsII,mipsIII,mipsIV:
2547 // start-sanitize-vr4320
2549 // end-sanitize-vr4320
2551 do_mult (SD_, RS, RT, 0);
2555 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2556 "mult r<RD>, r<RS>, r<RT>"
2558 // start-sanitize-cygnus
2560 // end-sanitize-cygnus
2561 // start-sanitize-r5900
2563 // end-sanitize-r5900
2565 // start-sanitize-tx19
2567 // end-sanitize-tx19
2569 do_mult (SD_, RS, RT, RD);
2573 :function:::void:do_multu:int rs, int rt, int rd
2576 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2577 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2578 prod = (((unsigned64)(unsigned32) GPR[rs])
2579 * ((unsigned64)(unsigned32) GPR[rt]));
2580 LO = EXTEND32 (VL4_8 (prod));
2581 HI = EXTEND32 (VH4_8 (prod));
2584 TRACE_ALU_RESULT2 (HI, LO);
2587 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2588 "multu r<RS>, r<RT>"
2589 *mipsI,mipsII,mipsIII,mipsIV:
2590 // start-sanitize-vr4320
2592 // end-sanitize-vr4320
2594 do_multu (SD_, RS, RT, 0);
2597 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2598 "multu r<RD>, r<RS>, r<RT>"
2600 // start-sanitize-cygnus
2602 // end-sanitize-cygnus
2603 // start-sanitize-r5900
2605 // end-sanitize-r5900
2607 // start-sanitize-tx19
2609 // end-sanitize-tx19
2611 do_multu (SD_, RS, RT, 0);
2615 :function:::void:do_nor:int rs, int rt, int rd
2617 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2618 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2619 TRACE_ALU_RESULT (GPR[rd]);
2622 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2623 "nor r<RD>, r<RS>, r<RT>"
2624 *mipsI,mipsII,mipsIII,mipsIV:
2626 // start-sanitize-vr4320
2628 // end-sanitize-vr4320
2629 // start-sanitize-cygnus
2631 // end-sanitize-cygnus
2632 // start-sanitize-r5900
2634 // end-sanitize-r5900
2636 // start-sanitize-tx19
2638 // end-sanitize-tx19
2640 do_nor (SD_, RS, RT, RD);
2644 :function:::void:do_or:int rs, int rt, int rd
2646 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2647 GPR[rd] = (GPR[rs] | GPR[rt]);
2648 TRACE_ALU_RESULT (GPR[rd]);
2651 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2652 "or r<RD>, r<RS>, r<RT>"
2653 *mipsI,mipsII,mipsIII,mipsIV:
2655 // start-sanitize-vr4320
2657 // end-sanitize-vr4320
2658 // start-sanitize-cygnus
2660 // end-sanitize-cygnus
2661 // start-sanitize-r5900
2663 // end-sanitize-r5900
2665 // start-sanitize-tx19
2667 // end-sanitize-tx19
2669 do_or (SD_, RS, RT, RD);
2674 :function:::void:do_ori:int rs, int rt, unsigned immediate
2676 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2677 GPR[rt] = (GPR[rs] | immediate);
2678 TRACE_ALU_RESULT (GPR[rt]);
2681 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2682 "ori r<RT>, r<RS>, <IMMEDIATE>"
2683 *mipsI,mipsII,mipsIII,mipsIV:
2685 // start-sanitize-vr4320
2687 // end-sanitize-vr4320
2688 // start-sanitize-cygnus
2690 // end-sanitize-cygnus
2691 // start-sanitize-r5900
2693 // end-sanitize-r5900
2695 // start-sanitize-tx19
2697 // end-sanitize-tx19
2699 do_ori (SD_, RS, RT, IMMEDIATE);
2703 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2706 // start-sanitize-vr4320
2708 // end-sanitize-vr4320
2709 // start-sanitize-cygnus
2711 // end-sanitize-cygnus
2712 // start-sanitize-r5900
2714 // end-sanitize-r5900
2716 unsigned32 instruction = instruction_0;
2717 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2718 int hint = ((instruction >> 16) & 0x0000001F);
2719 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2721 address_word vaddr = ((unsigned64)op1 + offset);
2725 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2726 Prefetch(uncached,paddr,vaddr,isDATA,hint);
2731 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2733 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2734 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2735 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2742 vaddr = base + offset;
2743 if ((vaddr & access) != 0)
2744 SignalExceptionAddressStore ();
2745 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2746 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2747 byte = ((vaddr & mask) ^ bigendiancpu);
2748 memval = (word << (8 * byte));
2749 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2753 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2754 "sb r<RT>, <OFFSET>(r<BASE>)"
2755 *mipsI,mipsII,mipsIII,mipsIV:
2757 // start-sanitize-vr4320
2759 // end-sanitize-vr4320
2760 // start-sanitize-cygnus
2762 // end-sanitize-cygnus
2763 // start-sanitize-r5900
2765 // end-sanitize-r5900
2767 // start-sanitize-tx19
2769 // end-sanitize-tx19
2771 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2775 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2776 "sc r<RT>, <OFFSET>(r<BASE>)"
2781 // start-sanitize-vr4320
2783 // end-sanitize-vr4320
2784 // start-sanitize-cygnus
2786 // end-sanitize-cygnus
2787 // start-sanitize-r5900
2789 // end-sanitize-r5900
2790 // start-sanitize-tx19
2792 // end-sanitize-tx19
2794 unsigned32 instruction = instruction_0;
2795 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2796 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2797 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2799 address_word vaddr = ((unsigned64)op1 + offset);
2802 if ((vaddr & 3) != 0)
2803 SignalExceptionAddressStore();
2806 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2808 unsigned64 memval = 0;
2809 unsigned64 memval1 = 0;
2810 unsigned64 mask = 0x7;
2812 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2813 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2814 memval = ((unsigned64) op2 << (8 * byte));
2817 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2819 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2826 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2827 "scd r<RT>, <OFFSET>(r<BASE>)"
2831 // start-sanitize-vr4320
2833 // end-sanitize-vr4320
2834 // start-sanitize-cygnus
2836 // end-sanitize-cygnus
2837 // start-sanitize-r5900
2839 // end-sanitize-r5900
2840 // start-sanitize-tx19
2842 // end-sanitize-tx19
2844 unsigned32 instruction = instruction_0;
2845 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2846 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2847 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2849 address_word vaddr = ((unsigned64)op1 + offset);
2852 if ((vaddr & 7) != 0)
2853 SignalExceptionAddressStore();
2856 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2858 unsigned64 memval = 0;
2859 unsigned64 memval1 = 0;
2863 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2865 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2872 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2873 "sd r<RT>, <OFFSET>(r<BASE>)"
2877 // start-sanitize-vr4320
2879 // end-sanitize-vr4320
2880 // start-sanitize-cygnus
2882 // end-sanitize-cygnus
2883 // start-sanitize-r5900
2885 // end-sanitize-r5900
2886 // start-sanitize-tx19
2888 // end-sanitize-tx19
2890 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2894 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2895 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2900 // start-sanitize-vr4320
2902 // end-sanitize-vr4320
2903 // start-sanitize-cygnus
2905 // end-sanitize-cygnus
2906 // start-sanitize-tx19
2908 // end-sanitize-tx19
2910 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2914 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2915 "sdl r<RT>, <OFFSET>(r<BASE>)"
2919 // start-sanitize-vr4320
2921 // end-sanitize-vr4320
2922 // start-sanitize-cygnus
2924 // end-sanitize-cygnus
2925 // start-sanitize-r5900
2927 // end-sanitize-r5900
2928 // start-sanitize-tx19
2930 // end-sanitize-tx19
2932 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2936 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2937 "sdr r<RT>, <OFFSET>(r<BASE>)"
2941 // start-sanitize-vr4320
2943 // end-sanitize-vr4320
2944 // start-sanitize-cygnus
2946 // end-sanitize-cygnus
2947 // start-sanitize-r5900
2949 // end-sanitize-r5900
2950 // start-sanitize-tx19
2952 // end-sanitize-tx19
2954 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2958 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2959 "sh r<RT>, <OFFSET>(r<BASE>)"
2960 *mipsI,mipsII,mipsIII,mipsIV:
2962 // start-sanitize-vr4320
2964 // end-sanitize-vr4320
2965 // start-sanitize-cygnus
2967 // end-sanitize-cygnus
2968 // start-sanitize-r5900
2970 // end-sanitize-r5900
2972 // start-sanitize-tx19
2974 // end-sanitize-tx19
2976 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2980 :function:::void:do_sll:int rt, int rd, int shift
2982 unsigned32 temp = (GPR[rt] << shift);
2983 TRACE_ALU_INPUT2 (GPR[rt], shift);
2984 GPR[rd] = EXTEND32 (temp);
2985 TRACE_ALU_RESULT (GPR[rd]);
2988 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2989 "sll r<RD>, r<RT>, <SHIFT>"
2990 *mipsI,mipsII,mipsIII,mipsIV:
2992 // start-sanitize-vr4320
2994 // end-sanitize-vr4320
2995 // start-sanitize-cygnus
2997 // end-sanitize-cygnus
2998 // start-sanitize-r5900
3000 // end-sanitize-r5900
3002 // start-sanitize-tx19
3004 // end-sanitize-tx19
3006 do_sll (SD_, RT, RD, SHIFT);
3010 :function:::void:do_sllv:int rs, int rt, int rd
3012 int s = MASKED (GPR[rs], 4, 0);
3013 unsigned32 temp = (GPR[rt] << s);
3014 TRACE_ALU_INPUT2 (GPR[rt], s);
3015 GPR[rd] = EXTEND32 (temp);
3016 TRACE_ALU_RESULT (GPR[rd]);
3019 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
3020 "sllv r<RD>, r<RT>, r<RS>"
3021 *mipsI,mipsII,mipsIII,mipsIV:
3023 // start-sanitize-vr4320
3025 // end-sanitize-vr4320
3026 // start-sanitize-cygnus
3028 // end-sanitize-cygnus
3029 // start-sanitize-r5900
3031 // end-sanitize-r5900
3033 // start-sanitize-tx19
3035 // end-sanitize-tx19
3037 do_sllv (SD_, RS, RT, RD);
3041 :function:::void:do_slt:int rs, int rt, int rd
3043 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3044 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
3045 TRACE_ALU_RESULT (GPR[rd]);
3048 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
3049 "slt r<RD>, r<RS>, r<RT>"
3050 *mipsI,mipsII,mipsIII,mipsIV:
3052 // start-sanitize-vr4320
3054 // end-sanitize-vr4320
3055 // start-sanitize-cygnus
3057 // end-sanitize-cygnus
3058 // start-sanitize-r5900
3060 // end-sanitize-r5900
3062 // start-sanitize-tx19
3064 // end-sanitize-tx19
3066 do_slt (SD_, RS, RT, RD);
3070 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
3072 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3073 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3074 TRACE_ALU_RESULT (GPR[rt]);
3077 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3078 "slti r<RT>, r<RS>, <IMMEDIATE>"
3079 *mipsI,mipsII,mipsIII,mipsIV:
3081 // start-sanitize-vr4320
3083 // end-sanitize-vr4320
3084 // start-sanitize-cygnus
3086 // end-sanitize-cygnus
3087 // start-sanitize-r5900
3089 // end-sanitize-r5900
3091 // start-sanitize-tx19
3093 // end-sanitize-tx19
3095 do_slti (SD_, RS, RT, IMMEDIATE);
3099 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3101 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3102 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3103 TRACE_ALU_RESULT (GPR[rt]);
3106 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3107 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3108 *mipsI,mipsII,mipsIII,mipsIV:
3110 // start-sanitize-vr4320
3112 // end-sanitize-vr4320
3113 // start-sanitize-cygnus
3115 // end-sanitize-cygnus
3116 // start-sanitize-r5900
3118 // end-sanitize-r5900
3120 // start-sanitize-tx19
3122 // end-sanitize-tx19
3124 do_sltiu (SD_, RS, RT, IMMEDIATE);
3129 :function:::void:do_sltu:int rs, int rt, int rd
3131 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3132 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3133 TRACE_ALU_RESULT (GPR[rd]);
3136 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
3137 "sltu r<RD>, r<RS>, r<RT>"
3138 *mipsI,mipsII,mipsIII,mipsIV:
3140 // start-sanitize-vr4320
3142 // end-sanitize-vr4320
3143 // start-sanitize-cygnus
3145 // end-sanitize-cygnus
3146 // start-sanitize-r5900
3148 // end-sanitize-r5900
3150 // start-sanitize-tx19
3152 // end-sanitize-tx19
3154 do_sltu (SD_, RS, RT, RD);
3158 :function:::void:do_sra:int rt, int rd, int shift
3160 signed32 temp = (signed32) GPR[rt] >> shift;
3161 TRACE_ALU_INPUT2 (GPR[rt], shift);
3162 GPR[rd] = EXTEND32 (temp);
3163 TRACE_ALU_RESULT (GPR[rd]);
3166 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3167 "sra r<RD>, r<RT>, <SHIFT>"
3168 *mipsI,mipsII,mipsIII,mipsIV:
3170 // start-sanitize-vr4320
3172 // end-sanitize-vr4320
3173 // start-sanitize-cygnus
3175 // end-sanitize-cygnus
3176 // start-sanitize-r5900
3178 // end-sanitize-r5900
3180 // start-sanitize-tx19
3182 // end-sanitize-tx19
3184 do_sra (SD_, RT, RD, SHIFT);
3189 :function:::void:do_srav:int rs, int rt, int rd
3191 int s = MASKED (GPR[rs], 4, 0);
3192 signed32 temp = (signed32) GPR[rt] >> s;
3193 TRACE_ALU_INPUT2 (GPR[rt], s);
3194 GPR[rd] = EXTEND32 (temp);
3195 TRACE_ALU_RESULT (GPR[rd]);
3198 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3199 "srav r<RD>, r<RT>, r<RS>"
3200 *mipsI,mipsII,mipsIII,mipsIV:
3202 // start-sanitize-vr4320
3204 // end-sanitize-vr4320
3205 // start-sanitize-cygnus
3207 // end-sanitize-cygnus
3208 // start-sanitize-r5900
3210 // end-sanitize-r5900
3212 // start-sanitize-tx19
3214 // end-sanitize-tx19
3216 do_srav (SD_, RS, RT, RD);
3221 :function:::void:do_srl:int rt, int rd, int shift
3223 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3224 TRACE_ALU_INPUT2 (GPR[rt], shift);
3225 GPR[rd] = EXTEND32 (temp);
3226 TRACE_ALU_RESULT (GPR[rd]);
3229 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3230 "srl r<RD>, r<RT>, <SHIFT>"
3231 *mipsI,mipsII,mipsIII,mipsIV:
3233 // start-sanitize-vr4320
3235 // end-sanitize-vr4320
3236 // start-sanitize-cygnus
3238 // end-sanitize-cygnus
3239 // start-sanitize-r5900
3241 // end-sanitize-r5900
3243 // start-sanitize-tx19
3245 // end-sanitize-tx19
3247 do_srl (SD_, RT, RD, SHIFT);
3251 :function:::void:do_srlv:int rs, int rt, int rd
3253 int s = MASKED (GPR[rs], 4, 0);
3254 unsigned32 temp = (unsigned32) GPR[rt] >> s;
3255 TRACE_ALU_INPUT2 (GPR[rt], s);
3256 GPR[rd] = EXTEND32 (temp);
3257 TRACE_ALU_RESULT (GPR[rd]);
3260 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3261 "srlv r<RD>, r<RT>, r<RS>"
3262 *mipsI,mipsII,mipsIII,mipsIV:
3264 // start-sanitize-vr4320
3266 // end-sanitize-vr4320
3267 // start-sanitize-cygnus
3269 // end-sanitize-cygnus
3270 // start-sanitize-r5900
3272 // end-sanitize-r5900
3274 // start-sanitize-tx19
3276 // end-sanitize-tx19
3278 do_srlv (SD_, RS, RT, RD);
3282 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3283 "sub r<RD>, r<RS>, r<RT>"
3284 *mipsI,mipsII,mipsIII,mipsIV:
3286 // start-sanitize-vr4320
3288 // end-sanitize-vr4320
3289 // start-sanitize-cygnus
3291 // end-sanitize-cygnus
3292 // start-sanitize-r5900
3294 // end-sanitize-r5900
3296 // start-sanitize-tx19
3298 // end-sanitize-tx19
3300 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3302 ALU32_BEGIN (GPR[RS]);
3303 ALU32_SUB (GPR[RT]);
3304 ALU32_END (GPR[RD]);
3306 TRACE_ALU_RESULT (GPR[RD]);
3310 :function:::void:do_subu:int rs, int rt, int rd
3312 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3313 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3314 TRACE_ALU_RESULT (GPR[rd]);
3317 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3318 "subu r<RD>, r<RS>, r<RT>"
3319 *mipsI,mipsII,mipsIII,mipsIV:
3321 // start-sanitize-vr4320
3323 // end-sanitize-vr4320
3324 // start-sanitize-cygnus
3326 // end-sanitize-cygnus
3327 // start-sanitize-r5900
3329 // end-sanitize-r5900
3331 // start-sanitize-tx19
3333 // end-sanitize-tx19
3335 do_subu (SD_, RS, RT, RD);
3339 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3340 "sw r<RT>, <OFFSET>(r<BASE>)"
3341 *mipsI,mipsII,mipsIII,mipsIV:
3342 // start-sanitize-tx19
3344 // end-sanitize-tx19
3346 // start-sanitize-vr4320
3348 // end-sanitize-vr4320
3350 // start-sanitize-cygnus
3352 // end-sanitize-cygnus
3353 // start-sanitize-r5900
3355 // end-sanitize-r5900
3357 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3361 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3362 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3363 *mipsI,mipsII,mipsIII,mipsIV:
3365 // start-sanitize-vr4320
3367 // end-sanitize-vr4320
3368 // start-sanitize-cygnus
3370 // end-sanitize-cygnus
3372 // start-sanitize-tx19
3374 // end-sanitize-tx19
3376 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3381 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3383 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3384 address_word reverseendian = (ReverseEndian ? -1 : 0);
3385 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3395 vaddr = base + offset;
3396 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3397 paddr = (paddr ^ (reverseendian & mask));
3398 if (BigEndianMem == 0)
3399 paddr = paddr & ~access;
3401 /* compute where within the word/mem we are */
3402 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3403 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3404 nr_lhs_bits = 8 * byte + 8;
3405 nr_rhs_bits = 8 * access - 8 * byte;
3406 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3407 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3408 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3409 (long) ((unsigned64) paddr >> 32), (long) paddr,
3410 word, byte, nr_lhs_bits, nr_rhs_bits); */
3414 memval = (rt >> nr_rhs_bits);
3418 memval = (rt << nr_lhs_bits);
3420 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
3421 (long) ((unsigned64) rt >> 32), (long) rt,
3422 (long) ((unsigned64) memval >> 32), (long) memval); */
3423 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
3427 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3428 "swl r<RT>, <OFFSET>(r<BASE>)"
3429 *mipsI,mipsII,mipsIII,mipsIV:
3431 // start-sanitize-vr4320
3433 // end-sanitize-vr4320
3434 // start-sanitize-cygnus
3436 // end-sanitize-cygnus
3437 // start-sanitize-r5900
3439 // end-sanitize-r5900
3441 // start-sanitize-tx19
3443 // end-sanitize-tx19
3445 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3449 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3451 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3452 address_word reverseendian = (ReverseEndian ? -1 : 0);
3453 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3460 vaddr = base + offset;
3461 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3462 paddr = (paddr ^ (reverseendian & mask));
3463 if (BigEndianMem != 0)
3465 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3466 memval = (rt << (byte * 8));
3467 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3470 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3471 "swr r<RT>, <OFFSET>(r<BASE>)"
3472 *mipsI,mipsII,mipsIII,mipsIV:
3474 // start-sanitize-vr4320
3476 // end-sanitize-vr4320
3477 // start-sanitize-cygnus
3479 // end-sanitize-cygnus
3480 // start-sanitize-r5900
3482 // end-sanitize-r5900
3484 // start-sanitize-tx19
3486 // end-sanitize-tx19
3488 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3492 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3499 // start-sanitize-vr4320
3501 // end-sanitize-vr4320
3502 // start-sanitize-cygnus
3504 // end-sanitize-cygnus
3505 // start-sanitize-r5900
3507 // end-sanitize-r5900
3509 // start-sanitize-tx19
3511 // end-sanitize-tx19
3513 SyncOperation (STYPE);
3517 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3519 *mipsI,mipsII,mipsIII,mipsIV:
3521 // start-sanitize-vr4320
3523 // end-sanitize-vr4320
3524 // start-sanitize-cygnus
3526 // end-sanitize-cygnus
3527 // start-sanitize-r5900
3529 // end-sanitize-r5900
3531 // start-sanitize-tx19
3533 // end-sanitize-tx19
3535 SignalException(SystemCall, instruction_0);
3539 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3545 // start-sanitize-vr4320
3547 // end-sanitize-vr4320
3548 // start-sanitize-cygnus
3550 // end-sanitize-cygnus
3551 // start-sanitize-r5900
3553 // end-sanitize-r5900
3554 // start-sanitize-tx19
3556 // end-sanitize-tx19
3558 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3559 SignalException(Trap, instruction_0);
3563 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3564 "teqi r<RS>, <IMMEDIATE>"
3569 // start-sanitize-vr4320
3571 // end-sanitize-vr4320
3572 // start-sanitize-cygnus
3574 // end-sanitize-cygnus
3575 // start-sanitize-r5900
3577 // end-sanitize-r5900
3578 // start-sanitize-tx19
3580 // end-sanitize-tx19
3582 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3583 SignalException(Trap, instruction_0);
3587 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3593 // start-sanitize-vr4320
3595 // end-sanitize-vr4320
3596 // start-sanitize-cygnus
3598 // end-sanitize-cygnus
3599 // start-sanitize-r5900
3601 // end-sanitize-r5900
3602 // start-sanitize-tx19
3604 // end-sanitize-tx19
3606 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3607 SignalException(Trap, instruction_0);
3611 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3612 "tgei r<RS>, <IMMEDIATE>"
3617 // start-sanitize-vr4320
3619 // end-sanitize-vr4320
3620 // start-sanitize-cygnus
3622 // end-sanitize-cygnus
3623 // start-sanitize-r5900
3625 // end-sanitize-r5900
3626 // start-sanitize-tx19
3628 // end-sanitize-tx19
3630 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3631 SignalException(Trap, instruction_0);
3635 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3636 "tgeiu r<RS>, <IMMEDIATE>"
3641 // start-sanitize-vr4320
3643 // end-sanitize-vr4320
3644 // start-sanitize-cygnus
3646 // end-sanitize-cygnus
3647 // start-sanitize-r5900
3649 // end-sanitize-r5900
3650 // start-sanitize-tx19
3652 // end-sanitize-tx19
3654 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3655 SignalException(Trap, instruction_0);
3659 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3665 // start-sanitize-vr4320
3667 // end-sanitize-vr4320
3668 // start-sanitize-cygnus
3670 // end-sanitize-cygnus
3671 // start-sanitize-r5900
3673 // end-sanitize-r5900
3674 // start-sanitize-tx19
3676 // end-sanitize-tx19
3678 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3679 SignalException(Trap, instruction_0);
3683 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3689 // start-sanitize-vr4320
3691 // end-sanitize-vr4320
3692 // start-sanitize-cygnus
3694 // end-sanitize-cygnus
3695 // start-sanitize-r5900
3697 // end-sanitize-r5900
3698 // start-sanitize-tx19
3700 // end-sanitize-tx19
3702 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3703 SignalException(Trap, instruction_0);
3707 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3708 "tlti r<RS>, <IMMEDIATE>"
3713 // start-sanitize-vr4320
3715 // end-sanitize-vr4320
3716 // start-sanitize-cygnus
3718 // end-sanitize-cygnus
3719 // start-sanitize-r5900
3721 // end-sanitize-r5900
3722 // start-sanitize-tx19
3724 // end-sanitize-tx19
3726 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3727 SignalException(Trap, instruction_0);
3731 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3732 "tltiu r<RS>, <IMMEDIATE>"
3737 // start-sanitize-vr4320
3739 // end-sanitize-vr4320
3740 // start-sanitize-cygnus
3742 // end-sanitize-cygnus
3743 // start-sanitize-r5900
3745 // end-sanitize-r5900
3746 // start-sanitize-tx19
3748 // end-sanitize-tx19
3750 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3751 SignalException(Trap, instruction_0);
3755 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3761 // start-sanitize-vr4320
3763 // end-sanitize-vr4320
3764 // start-sanitize-cygnus
3766 // end-sanitize-cygnus
3767 // start-sanitize-r5900
3769 // end-sanitize-r5900
3770 // start-sanitize-tx19
3772 // end-sanitize-tx19
3774 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3775 SignalException(Trap, instruction_0);
3779 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3785 // start-sanitize-vr4320
3787 // end-sanitize-vr4320
3788 // start-sanitize-cygnus
3790 // end-sanitize-cygnus
3791 // start-sanitize-r5900
3793 // end-sanitize-r5900
3794 // start-sanitize-tx19
3796 // end-sanitize-tx19
3798 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3799 SignalException(Trap, instruction_0);
3803 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3804 "tne r<RS>, <IMMEDIATE>"
3809 // start-sanitize-vr4320
3811 // end-sanitize-vr4320
3812 // start-sanitize-cygnus
3814 // end-sanitize-cygnus
3815 // start-sanitize-r5900
3817 // end-sanitize-r5900
3818 // start-sanitize-tx19
3820 // end-sanitize-tx19
3822 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3823 SignalException(Trap, instruction_0);
3827 :function:::void:do_xor:int rs, int rt, int rd
3829 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3830 GPR[rd] = GPR[rs] ^ GPR[rt];
3831 TRACE_ALU_RESULT (GPR[rd]);
3834 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3835 "xor r<RD>, r<RS>, r<RT>"
3836 *mipsI,mipsII,mipsIII,mipsIV:
3838 // start-sanitize-vr4320
3840 // end-sanitize-vr4320
3841 // start-sanitize-cygnus
3843 // end-sanitize-cygnus
3844 // start-sanitize-r5900
3846 // end-sanitize-r5900
3848 // start-sanitize-tx19
3850 // end-sanitize-tx19
3852 do_xor (SD_, RS, RT, RD);
3856 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3858 TRACE_ALU_INPUT2 (GPR[rs], immediate);
3859 GPR[rt] = GPR[rs] ^ immediate;
3860 TRACE_ALU_RESULT (GPR[rt]);
3863 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3864 "xori r<RT>, r<RS>, <IMMEDIATE>"
3865 *mipsI,mipsII,mipsIII,mipsIV:
3867 // start-sanitize-vr4320
3869 // end-sanitize-vr4320
3870 // start-sanitize-cygnus
3872 // end-sanitize-cygnus
3873 // start-sanitize-r5900
3875 // end-sanitize-r5900
3877 // start-sanitize-tx19
3879 // end-sanitize-tx19
3881 do_xori (SD_, RS, RT, IMMEDIATE);
3886 // MIPS Architecture:
3888 // FPU Instruction Set (COP1 & COP1X)
3896 case fmt_single: return "s";
3897 case fmt_double: return "d";
3898 case fmt_word: return "w";
3899 case fmt_long: return "l";
3900 default: return "?";
3910 default: return "?";
3930 :%s::::COND:int cond
3934 case 00: return "f";
3935 case 01: return "un";
3936 case 02: return "eq";
3937 case 03: return "ueq";
3938 case 04: return "olt";
3939 case 05: return "ult";
3940 case 06: return "ole";
3941 case 07: return "ule";
3942 case 010: return "sf";
3943 case 011: return "ngle";
3944 case 012: return "seq";
3945 case 013: return "ngl";
3946 case 014: return "lt";
3947 case 015: return "nge";
3948 case 016: return "le";
3949 case 017: return "ngt";
3950 default: return "?";
3955 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3956 "abs.%s<FMT> f<FD>, f<FS>"
3957 *mipsI,mipsII,mipsIII,mipsIV:
3959 // start-sanitize-vr4320
3961 // end-sanitize-vr4320
3962 // start-sanitize-cygnus
3964 // end-sanitize-cygnus
3966 // start-sanitize-tx19
3968 // end-sanitize-tx19
3970 unsigned32 instruction = instruction_0;
3971 int destreg = ((instruction >> 6) & 0x0000001F);
3972 int fs = ((instruction >> 11) & 0x0000001F);
3973 int format = ((instruction >> 21) & 0x00000007);
3975 if ((format != fmt_single) && (format != fmt_double))
3976 SignalException(ReservedInstruction,instruction);
3978 StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3984 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3985 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3986 *mipsI,mipsII,mipsIII,mipsIV:
3988 // start-sanitize-vr4320
3990 // end-sanitize-vr4320
3991 // start-sanitize-cygnus
3993 // end-sanitize-cygnus
3995 // start-sanitize-tx19
3997 // end-sanitize-tx19
3999 unsigned32 instruction = instruction_0;
4000 int destreg = ((instruction >> 6) & 0x0000001F);
4001 int fs = ((instruction >> 11) & 0x0000001F);
4002 int ft = ((instruction >> 16) & 0x0000001F);
4003 int format = ((instruction >> 21) & 0x00000007);
4005 if ((format != fmt_single) && (format != fmt_double))
4006 SignalException(ReservedInstruction, instruction);
4008 StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
4019 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
4020 "bc1%s<TF>%s<ND> <OFFSET>"
4021 *mipsI,mipsII,mipsIII:
4022 // start-sanitize-r5900
4024 // end-sanitize-r5900
4026 check_branch_bug ();
4027 TRACE_BRANCH_INPUT (PREVCOC1());
4028 if (PREVCOC1() == TF)
4030 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4031 TRACE_BRANCH_RESULT (dest);
4032 mark_branch_bug (dest);
4037 TRACE_BRANCH_RESULT (0);
4038 NULLIFY_NEXT_INSTRUCTION ();
4042 TRACE_BRANCH_RESULT (NIA);
4046 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
4047 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
4048 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
4051 // start-sanitize-vr4320
4053 // end-sanitize-vr4320
4054 // start-sanitize-cygnus
4056 // end-sanitize-cygnus
4058 // start-sanitize-tx19
4060 // end-sanitize-tx19
4062 check_branch_bug ();
4063 if (GETFCC(CC) == TF)
4065 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4066 mark_branch_bug (dest);
4071 NULLIFY_NEXT_INSTRUCTION ();
4084 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
4086 if ((fmt != fmt_single) && (fmt != fmt_double))
4087 SignalException (ReservedInstruction, insn);
4094 unsigned64 ofs = ValueFPR (fs, fmt);
4095 unsigned64 oft = ValueFPR (ft, fmt);
4096 if (NaN (ofs, fmt) || NaN (oft, fmt))
4098 if (FCSR & FP_ENABLE (IO))
4100 FCSR |= FP_CAUSE (IO);
4101 SignalExceptionFPE ();
4109 less = Less (ofs, oft, fmt);
4110 equal = Equal (ofs, oft, fmt);
4113 condition = (((cond & (1 << 2)) && less)
4114 || ((cond & (1 << 1)) && equal)
4115 || ((cond & (1 << 0)) && unordered));
4116 SETFCC (cc, condition);
4120 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
4121 *mipsI,mipsII,mipsIII:
4122 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
4124 do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
4127 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
4128 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4129 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4132 // start-sanitize-vr4320
4134 // end-sanitize-vr4320
4135 // start-sanitize-cygnus
4137 // end-sanitize-cygnus
4139 // start-sanitize-tx19
4141 // end-sanitize-tx19
4143 do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
4147 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
4148 "ceil.l.%s<FMT> f<FD>, f<FS>"
4152 // start-sanitize-vr4320
4154 // end-sanitize-vr4320
4155 // start-sanitize-cygnus
4157 // end-sanitize-cygnus
4158 // start-sanitize-r5900
4160 // end-sanitize-r5900
4162 // start-sanitize-tx19
4164 // end-sanitize-tx19
4166 unsigned32 instruction = instruction_0;
4167 int destreg = ((instruction >> 6) & 0x0000001F);
4168 int fs = ((instruction >> 11) & 0x0000001F);
4169 int format = ((instruction >> 21) & 0x00000007);
4171 if ((format != fmt_single) && (format != fmt_double))
4172 SignalException(ReservedInstruction,instruction);
4174 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
4179 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
4184 // start-sanitize-vr4320
4186 // end-sanitize-vr4320
4187 // start-sanitize-cygnus
4189 // end-sanitize-cygnus
4190 // start-sanitize-r5900
4192 // end-sanitize-r5900
4194 // start-sanitize-tx19
4196 // end-sanitize-tx19
4198 unsigned32 instruction = instruction_0;
4199 int destreg = ((instruction >> 6) & 0x0000001F);
4200 int fs = ((instruction >> 11) & 0x0000001F);
4201 int format = ((instruction >> 21) & 0x00000007);
4203 if ((format != fmt_single) && (format != fmt_double))
4204 SignalException(ReservedInstruction,instruction);
4206 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
4213 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4214 "c%s<X>c1 r<RT>, f<FS>"
4222 PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
4224 PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4226 PENDING_FILL(COCIDX,0); /* special case */
4229 { /* control from */
4231 PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4233 PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4237 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4238 "c%s<X>c1 r<RT>, f<FS>"
4241 // start-sanitize-vr4320
4243 // end-sanitize-vr4320
4244 // start-sanitize-cygnus
4246 // end-sanitize-cygnus
4248 // start-sanitize-tx19
4250 // end-sanitize-tx19
4255 TRACE_ALU_INPUT1 (GPR[RT]);
4258 FCR0 = VL4_8(GPR[RT]);
4259 TRACE_ALU_RESULT (FCR0);
4263 FCR31 = VL4_8(GPR[RT]);
4264 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4265 TRACE_ALU_RESULT (FCR31);
4269 TRACE_ALU_RESULT0 ();
4274 { /* control from */
4277 TRACE_ALU_INPUT1 (FCR0);
4278 GPR[RT] = SIGNEXTEND (FCR0, 32);
4282 TRACE_ALU_INPUT1 (FCR31);
4283 GPR[RT] = SIGNEXTEND (FCR31, 32);
4285 TRACE_ALU_RESULT (GPR[RT]);
4292 // FIXME: Does not correctly differentiate between mips*
4294 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4295 "cvt.d.%s<FMT> f<FD>, f<FS>"
4296 *mipsI,mipsII,mipsIII,mipsIV:
4298 // start-sanitize-vr4320
4300 // end-sanitize-vr4320
4301 // start-sanitize-cygnus
4303 // end-sanitize-cygnus
4305 // start-sanitize-tx19
4307 // end-sanitize-tx19
4309 unsigned32 instruction = instruction_0;
4310 int destreg = ((instruction >> 6) & 0x0000001F);
4311 int fs = ((instruction >> 11) & 0x0000001F);
4312 int format = ((instruction >> 21) & 0x00000007);
4314 if ((format == fmt_double) | 0)
4315 SignalException(ReservedInstruction,instruction);
4317 StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4322 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4323 "cvt.l.%s<FMT> f<FD>, f<FS>"
4327 // start-sanitize-vr4320
4329 // end-sanitize-vr4320
4330 // start-sanitize-cygnus
4332 // end-sanitize-cygnus
4334 // start-sanitize-tx19
4336 // end-sanitize-tx19
4338 unsigned32 instruction = instruction_0;
4339 int destreg = ((instruction >> 6) & 0x0000001F);
4340 int fs = ((instruction >> 11) & 0x0000001F);
4341 int format = ((instruction >> 21) & 0x00000007);
4343 if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4344 SignalException(ReservedInstruction,instruction);
4346 StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4352 // FIXME: Does not correctly differentiate between mips*
4354 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4355 "cvt.s.%s<FMT> f<FD>, f<FS>"
4356 *mipsI,mipsII,mipsIII,mipsIV:
4358 // start-sanitize-vr4320
4360 // end-sanitize-vr4320
4361 // start-sanitize-cygnus
4363 // end-sanitize-cygnus
4365 // start-sanitize-tx19
4367 // end-sanitize-tx19
4369 unsigned32 instruction = instruction_0;
4370 int destreg = ((instruction >> 6) & 0x0000001F);
4371 int fs = ((instruction >> 11) & 0x0000001F);
4372 int format = ((instruction >> 21) & 0x00000007);
4374 if ((format == fmt_single) | 0)
4375 SignalException(ReservedInstruction,instruction);
4377 StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4382 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4383 "cvt.w.%s<FMT> f<FD>, f<FS>"
4384 *mipsI,mipsII,mipsIII,mipsIV:
4386 // start-sanitize-vr4320
4388 // end-sanitize-vr4320
4389 // start-sanitize-cygnus
4391 // end-sanitize-cygnus
4393 // start-sanitize-tx19
4395 // end-sanitize-tx19
4397 unsigned32 instruction = instruction_0;
4398 int destreg = ((instruction >> 6) & 0x0000001F);
4399 int fs = ((instruction >> 11) & 0x0000001F);
4400 int format = ((instruction >> 21) & 0x00000007);
4402 if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4403 SignalException(ReservedInstruction,instruction);
4405 StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4410 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4411 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4412 *mipsI,mipsII,mipsIII,mipsIV:
4414 // start-sanitize-vr4320
4416 // end-sanitize-vr4320
4417 // start-sanitize-cygnus
4419 // end-sanitize-cygnus
4421 // start-sanitize-tx19
4423 // end-sanitize-tx19
4425 unsigned32 instruction = instruction_0;
4426 int destreg = ((instruction >> 6) & 0x0000001F);
4427 int fs = ((instruction >> 11) & 0x0000001F);
4428 int ft = ((instruction >> 16) & 0x0000001F);
4429 int format = ((instruction >> 21) & 0x00000007);
4431 if ((format != fmt_single) && (format != fmt_double))
4432 SignalException(ReservedInstruction,instruction);
4434 StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4441 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4442 "dm%s<X>c1 r<RT>, f<FS>"
4447 if (SizeFGR() == 64)
4448 PENDING_FILL((FS + FGRIDX),GPR[RT]);
4449 else if ((FS & 0x1) == 0)
4451 PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4452 PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4457 if (SizeFGR() == 64)
4458 PENDING_FILL(RT,FGR[FS]);
4459 else if ((FS & 0x1) == 0)
4460 PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4462 PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4465 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4466 "dm%s<X>c1 r<RT>, f<FS>"
4469 // start-sanitize-vr4320
4471 // end-sanitize-vr4320
4472 // start-sanitize-cygnus
4474 // end-sanitize-cygnus
4475 // start-sanitize-r5900
4477 // end-sanitize-r5900
4479 // start-sanitize-tx19
4481 // end-sanitize-tx19
4485 if (SizeFGR() == 64)
4486 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4487 else if ((FS & 0x1) == 0)
4488 StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4492 if (SizeFGR() == 64)
4494 else if ((FS & 0x1) == 0)
4495 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4497 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4502 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4503 "floor.l.%s<FMT> f<FD>, f<FS>"
4507 // start-sanitize-vr4320
4509 // end-sanitize-vr4320
4510 // start-sanitize-cygnus
4512 // end-sanitize-cygnus
4513 // start-sanitize-r5900
4515 // end-sanitize-r5900
4517 // start-sanitize-tx19
4519 // end-sanitize-tx19
4521 unsigned32 instruction = instruction_0;
4522 int destreg = ((instruction >> 6) & 0x0000001F);
4523 int fs = ((instruction >> 11) & 0x0000001F);
4524 int format = ((instruction >> 21) & 0x00000007);
4526 if ((format != fmt_single) && (format != fmt_double))
4527 SignalException(ReservedInstruction,instruction);
4529 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4534 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4535 "floor.w.%s<FMT> f<FD>, f<FS>"
4540 // start-sanitize-vr4320
4542 // end-sanitize-vr4320
4543 // start-sanitize-cygnus
4545 // end-sanitize-cygnus
4546 // start-sanitize-r5900
4548 // end-sanitize-r5900
4550 // start-sanitize-tx19
4552 // end-sanitize-tx19
4554 unsigned32 instruction = instruction_0;
4555 int destreg = ((instruction >> 6) & 0x0000001F);
4556 int fs = ((instruction >> 11) & 0x0000001F);
4557 int format = ((instruction >> 21) & 0x00000007);
4559 if ((format != fmt_single) && (format != fmt_double))
4560 SignalException(ReservedInstruction,instruction);
4562 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4567 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4568 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4573 // start-sanitize-vr4320
4575 // end-sanitize-vr4320
4576 // start-sanitize-cygnus
4578 // end-sanitize-cygnus
4580 // start-sanitize-tx19
4582 // end-sanitize-tx19
4584 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4588 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4589 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4592 // start-sanitize-vr4320
4594 // end-sanitize-vr4320
4595 // start-sanitize-cygnus
4597 // end-sanitize-cygnus
4599 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4604 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4605 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4606 *mipsI,mipsII,mipsIII,mipsIV:
4608 // start-sanitize-vr4320
4610 // end-sanitize-vr4320
4611 // start-sanitize-cygnus
4613 // end-sanitize-cygnus
4614 // start-sanitize-r5900
4616 // end-sanitize-r5900
4618 // start-sanitize-tx19
4620 // end-sanitize-tx19
4622 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4626 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4627 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4630 // start-sanitize-vr4320
4632 // end-sanitize-vr4320
4633 // start-sanitize-cygnus
4635 // end-sanitize-cygnus
4637 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4643 // FIXME: Not correct for mips*
4645 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4646 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4649 // start-sanitize-vr4320
4651 // end-sanitize-vr4320
4652 // start-sanitize-cygnus
4654 // end-sanitize-cygnus
4656 unsigned32 instruction = instruction_0;
4657 int destreg = ((instruction >> 6) & 0x0000001F);
4658 int fs = ((instruction >> 11) & 0x0000001F);
4659 int ft = ((instruction >> 16) & 0x0000001F);
4660 int fr = ((instruction >> 21) & 0x0000001F);
4662 StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4667 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4668 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4671 // start-sanitize-vr4320
4673 // end-sanitize-vr4320
4674 // start-sanitize-cygnus
4676 // end-sanitize-cygnus
4678 unsigned32 instruction = instruction_0;
4679 int destreg = ((instruction >> 6) & 0x0000001F);
4680 int fs = ((instruction >> 11) & 0x0000001F);
4681 int ft = ((instruction >> 16) & 0x0000001F);
4682 int fr = ((instruction >> 21) & 0x0000001F);
4684 StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4691 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4692 "m%s<X>c1 r<RT>, f<FS>"
4699 if (SizeFGR() == 64)
4700 PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4702 PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4705 PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4707 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4708 "m%s<X>c1 r<RT>, f<FS>"
4711 // start-sanitize-vr4320
4713 // end-sanitize-vr4320
4714 // start-sanitize-cygnus
4716 // end-sanitize-cygnus
4718 // start-sanitize-tx19
4720 // end-sanitize-tx19
4724 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4726 GPR[RT] = SIGNEXTEND(FGR[FS],32);
4730 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4731 "mov.%s<FMT> f<FD>, f<FS>"
4732 *mipsI,mipsII,mipsIII,mipsIV:
4734 // start-sanitize-vr4320
4736 // end-sanitize-vr4320
4737 // start-sanitize-cygnus
4739 // end-sanitize-cygnus
4741 // start-sanitize-tx19
4743 // end-sanitize-tx19
4745 unsigned32 instruction = instruction_0;
4746 int destreg = ((instruction >> 6) & 0x0000001F);
4747 int fs = ((instruction >> 11) & 0x0000001F);
4748 int format = ((instruction >> 21) & 0x00000007);
4750 StoreFPR(destreg,format,ValueFPR(fs,format));
4756 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4757 "mov%s<TF> r<RD>, r<RS>, <CC>"
4760 // start-sanitize-vr4320
4762 // end-sanitize-vr4320
4763 // start-sanitize-cygnus
4765 // end-sanitize-cygnus
4766 // start-sanitize-r5900
4768 // end-sanitize-r5900
4770 if (GETFCC(CC) == TF)
4776 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4777 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4780 // start-sanitize-vr4320
4782 // end-sanitize-vr4320
4783 // start-sanitize-cygnus
4785 // end-sanitize-cygnus
4786 // start-sanitize-r5900
4788 // end-sanitize-r5900
4790 unsigned32 instruction = instruction_0;
4791 int format = ((instruction >> 21) & 0x00000007);
4793 if (GETFCC(CC) == TF)
4794 StoreFPR (FD, format, ValueFPR (FS, format));
4796 StoreFPR (FD, format, ValueFPR (FD, format));
4801 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4804 // start-sanitize-vr4320
4806 // end-sanitize-vr4320
4807 // start-sanitize-cygnus
4809 // end-sanitize-cygnus
4810 // start-sanitize-r5900
4812 // end-sanitize-r5900
4814 unsigned32 instruction = instruction_0;
4815 int destreg = ((instruction >> 6) & 0x0000001F);
4816 int fs = ((instruction >> 11) & 0x0000001F);
4817 int format = ((instruction >> 21) & 0x00000007);
4819 StoreFPR(destreg,format,ValueFPR(fs,format));
4827 // MOVT.fmt see MOVtf.fmt
4831 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4832 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4835 // start-sanitize-vr4320
4837 // end-sanitize-vr4320
4838 // start-sanitize-cygnus
4840 // end-sanitize-cygnus
4841 // start-sanitize-r5900
4843 // end-sanitize-r5900
4845 unsigned32 instruction = instruction_0;
4846 int destreg = ((instruction >> 6) & 0x0000001F);
4847 int fs = ((instruction >> 11) & 0x0000001F);
4848 int format = ((instruction >> 21) & 0x00000007);
4850 StoreFPR(destreg,format,ValueFPR(fs,format));
4856 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4857 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4860 // start-sanitize-vr4320
4862 // end-sanitize-vr4320
4863 // start-sanitize-cygnus
4865 // end-sanitize-cygnus
4866 // start-sanitize-r5900
4868 // end-sanitize-r5900
4870 unsigned32 instruction = instruction_0;
4871 int destreg = ((instruction >> 6) & 0x0000001F);
4872 int fs = ((instruction >> 11) & 0x0000001F);
4873 int ft = ((instruction >> 16) & 0x0000001F);
4874 int fr = ((instruction >> 21) & 0x0000001F);
4876 StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4882 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4883 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4886 // start-sanitize-vr4320
4888 // end-sanitize-vr4320
4889 // start-sanitize-cygnus
4891 // end-sanitize-cygnus
4892 // start-sanitize-r5900
4894 // end-sanitize-r5900
4896 unsigned32 instruction = instruction_0;
4897 int destreg = ((instruction >> 6) & 0x0000001F);
4898 int fs = ((instruction >> 11) & 0x0000001F);
4899 int ft = ((instruction >> 16) & 0x0000001F);
4900 int fr = ((instruction >> 21) & 0x0000001F);
4902 StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4910 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4911 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4912 *mipsI,mipsII,mipsIII,mipsIV:
4914 // start-sanitize-vr4320
4916 // end-sanitize-vr4320
4917 // start-sanitize-cygnus
4919 // end-sanitize-cygnus
4921 // start-sanitize-tx19
4923 // end-sanitize-tx19
4925 unsigned32 instruction = instruction_0;
4926 int destreg = ((instruction >> 6) & 0x0000001F);
4927 int fs = ((instruction >> 11) & 0x0000001F);
4928 int ft = ((instruction >> 16) & 0x0000001F);
4929 int format = ((instruction >> 21) & 0x00000007);
4931 if ((format != fmt_single) && (format != fmt_double))
4932 SignalException(ReservedInstruction,instruction);
4934 StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4939 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4940 "neg.%s<FMT> f<FD>, f<FS>"
4941 *mipsI,mipsII,mipsIII,mipsIV:
4943 // start-sanitize-vr4320
4945 // end-sanitize-vr4320
4946 // start-sanitize-cygnus
4948 // end-sanitize-cygnus
4950 // start-sanitize-tx19
4952 // end-sanitize-tx19
4954 unsigned32 instruction = instruction_0;
4955 int destreg = ((instruction >> 6) & 0x0000001F);
4956 int fs = ((instruction >> 11) & 0x0000001F);
4957 int format = ((instruction >> 21) & 0x00000007);
4959 if ((format != fmt_single) && (format != fmt_double))
4960 SignalException(ReservedInstruction,instruction);
4962 StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4968 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4969 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4972 // start-sanitize-vr4320
4974 // end-sanitize-vr4320
4975 // start-sanitize-cygnus
4977 // end-sanitize-cygnus
4979 unsigned32 instruction = instruction_0;
4980 int destreg = ((instruction >> 6) & 0x0000001F);
4981 int fs = ((instruction >> 11) & 0x0000001F);
4982 int ft = ((instruction >> 16) & 0x0000001F);
4983 int fr = ((instruction >> 21) & 0x0000001F);
4985 StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4991 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4992 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4995 // start-sanitize-vr4320
4997 // end-sanitize-vr4320
4998 // start-sanitize-cygnus
5000 // end-sanitize-cygnus
5002 unsigned32 instruction = instruction_0;
5003 int destreg = ((instruction >> 6) & 0x0000001F);
5004 int fs = ((instruction >> 11) & 0x0000001F);
5005 int ft = ((instruction >> 16) & 0x0000001F);
5006 int fr = ((instruction >> 21) & 0x0000001F);
5008 StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5014 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
5015 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
5018 // start-sanitize-vr4320
5020 // end-sanitize-vr4320
5021 // start-sanitize-cygnus
5023 // end-sanitize-cygnus
5025 unsigned32 instruction = instruction_0;
5026 int destreg = ((instruction >> 6) & 0x0000001F);
5027 int fs = ((instruction >> 11) & 0x0000001F);
5028 int ft = ((instruction >> 16) & 0x0000001F);
5029 int fr = ((instruction >> 21) & 0x0000001F);
5031 StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
5037 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
5038 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
5041 // start-sanitize-vr4320
5043 // end-sanitize-vr4320
5044 // start-sanitize-cygnus
5046 // end-sanitize-cygnus
5048 unsigned32 instruction = instruction_0;
5049 int destreg = ((instruction >> 6) & 0x0000001F);
5050 int fs = ((instruction >> 11) & 0x0000001F);
5051 int ft = ((instruction >> 16) & 0x0000001F);
5052 int fr = ((instruction >> 21) & 0x0000001F);
5054 StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5059 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
5060 "prefx <HINT>, r<INDEX>(r<BASE>)"
5063 // start-sanitize-vr4320
5065 // end-sanitize-vr4320
5066 // start-sanitize-cygnus
5068 // end-sanitize-cygnus
5070 unsigned32 instruction = instruction_0;
5071 int fs = ((instruction >> 11) & 0x0000001F);
5072 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5073 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5075 address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
5078 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5079 Prefetch(uncached,paddr,vaddr,isDATA,fs);
5083 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
5085 "recip.%s<FMT> f<FD>, f<FS>"
5087 // start-sanitize-vr4320
5089 // end-sanitize-vr4320
5090 // start-sanitize-cygnus
5092 // end-sanitize-cygnus
5094 unsigned32 instruction = instruction_0;
5095 int destreg = ((instruction >> 6) & 0x0000001F);
5096 int fs = ((instruction >> 11) & 0x0000001F);
5097 int format = ((instruction >> 21) & 0x00000007);
5099 if ((format != fmt_single) && (format != fmt_double))
5100 SignalException(ReservedInstruction,instruction);
5102 StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
5107 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
5108 "round.l.%s<FMT> f<FD>, f<FS>"
5112 // start-sanitize-vr4320
5114 // end-sanitize-vr4320
5115 // start-sanitize-cygnus
5117 // end-sanitize-cygnus
5118 // start-sanitize-r5900
5120 // end-sanitize-r5900
5122 // start-sanitize-tx19
5124 // end-sanitize-tx19
5126 unsigned32 instruction = instruction_0;
5127 int destreg = ((instruction >> 6) & 0x0000001F);
5128 int fs = ((instruction >> 11) & 0x0000001F);
5129 int format = ((instruction >> 21) & 0x00000007);
5131 if ((format != fmt_single) && (format != fmt_double))
5132 SignalException(ReservedInstruction,instruction);
5134 StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
5139 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
5140 "round.w.%s<FMT> f<FD>, f<FS>"
5145 // start-sanitize-vr4320
5147 // end-sanitize-vr4320
5148 // start-sanitize-cygnus
5150 // end-sanitize-cygnus
5151 // start-sanitize-r5900
5153 // end-sanitize-r5900
5155 // start-sanitize-tx19
5157 // end-sanitize-tx19
5159 unsigned32 instruction = instruction_0;
5160 int destreg = ((instruction >> 6) & 0x0000001F);
5161 int fs = ((instruction >> 11) & 0x0000001F);
5162 int format = ((instruction >> 21) & 0x00000007);
5164 if ((format != fmt_single) && (format != fmt_double))
5165 SignalException(ReservedInstruction,instruction);
5167 StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
5172 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
5174 "rsqrt.%s<FMT> f<FD>, f<FS>"
5176 // start-sanitize-vr4320
5178 // end-sanitize-vr4320
5179 // start-sanitize-cygnus
5181 // end-sanitize-cygnus
5183 unsigned32 instruction = instruction_0;
5184 int destreg = ((instruction >> 6) & 0x0000001F);
5185 int fs = ((instruction >> 11) & 0x0000001F);
5186 int format = ((instruction >> 21) & 0x00000007);
5188 if ((format != fmt_single) && (format != fmt_double))
5189 SignalException(ReservedInstruction,instruction);
5191 StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
5196 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
5197 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5202 // start-sanitize-vr4320
5204 // end-sanitize-vr4320
5205 // start-sanitize-cygnus
5207 // end-sanitize-cygnus
5209 // start-sanitize-tx19
5211 // end-sanitize-tx19
5213 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5217 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
5218 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
5221 // start-sanitize-vr4320
5223 // end-sanitize-vr4320
5224 // start-sanitize-cygnus
5226 // end-sanitize-cygnus
5228 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5232 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5233 "sqrt.%s<FMT> f<FD>, f<FS>"
5238 // start-sanitize-vr4320
5240 // end-sanitize-vr4320
5241 // start-sanitize-cygnus
5243 // end-sanitize-cygnus
5245 // start-sanitize-tx19
5247 // end-sanitize-tx19
5249 unsigned32 instruction = instruction_0;
5250 int destreg = ((instruction >> 6) & 0x0000001F);
5251 int fs = ((instruction >> 11) & 0x0000001F);
5252 int format = ((instruction >> 21) & 0x00000007);
5254 if ((format != fmt_single) && (format != fmt_double))
5255 SignalException(ReservedInstruction,instruction);
5257 StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5262 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5263 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5264 *mipsI,mipsII,mipsIII,mipsIV:
5266 // start-sanitize-vr4320
5268 // end-sanitize-vr4320
5269 // start-sanitize-cygnus
5271 // end-sanitize-cygnus
5273 // start-sanitize-tx19
5275 // end-sanitize-tx19
5277 unsigned32 instruction = instruction_0;
5278 int destreg = ((instruction >> 6) & 0x0000001F);
5279 int fs = ((instruction >> 11) & 0x0000001F);
5280 int ft = ((instruction >> 16) & 0x0000001F);
5281 int format = ((instruction >> 21) & 0x00000007);
5283 if ((format != fmt_single) && (format != fmt_double))
5284 SignalException(ReservedInstruction,instruction);
5286 StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5292 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5293 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5294 *mipsI,mipsII,mipsIII,mipsIV:
5296 // start-sanitize-vr4320
5298 // end-sanitize-vr4320
5299 // start-sanitize-cygnus
5301 // end-sanitize-cygnus
5302 // start-sanitize-r5900
5304 // end-sanitize-r5900
5306 // start-sanitize-tx19
5308 // end-sanitize-tx19
5310 unsigned32 instruction = instruction_0;
5311 signed_word offset = EXTEND16 (OFFSET);
5312 int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5313 signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5315 address_word vaddr = ((uword64)op1 + offset);
5318 if ((vaddr & 3) != 0)
5319 SignalExceptionAddressStore();
5322 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5325 uword64 memval1 = 0;
5326 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5327 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5328 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5330 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5331 byte = ((vaddr & mask) ^ bigendiancpu);
5332 memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
5333 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5340 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5341 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5344 // start-sanitize-vr4320
5346 // end-sanitize-vr4320
5347 // start-sanitize-cygnus
5349 // end-sanitize-cygnus
5351 unsigned32 instruction = instruction_0;
5352 int fs = ((instruction >> 11) & 0x0000001F);
5353 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5354 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5356 address_word vaddr = ((unsigned64)op1 + op2);
5359 if ((vaddr & 3) != 0)
5360 SignalExceptionAddressStore();
5363 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5365 unsigned64 memval = 0;
5366 unsigned64 memval1 = 0;
5367 unsigned64 mask = 0x7;
5369 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5370 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5371 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5373 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5381 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5382 "trunc.l.%s<FMT> f<FD>, f<FS>"
5386 // start-sanitize-vr4320
5388 // end-sanitize-vr4320
5389 // start-sanitize-cygnus
5391 // end-sanitize-cygnus
5392 // start-sanitize-r5900
5394 // end-sanitize-r5900
5396 // start-sanitize-tx19
5398 // end-sanitize-tx19
5400 unsigned32 instruction = instruction_0;
5401 int destreg = ((instruction >> 6) & 0x0000001F);
5402 int fs = ((instruction >> 11) & 0x0000001F);
5403 int format = ((instruction >> 21) & 0x00000007);
5405 if ((format != fmt_single) && (format != fmt_double))
5406 SignalException(ReservedInstruction,instruction);
5408 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5413 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5414 "trunc.w.%s<FMT> f<FD>, f<FS>"
5419 // start-sanitize-vr4320
5421 // end-sanitize-vr4320
5422 // start-sanitize-cygnus
5424 // end-sanitize-cygnus
5425 // start-sanitize-r5900
5427 // end-sanitize-r5900
5429 // start-sanitize-tx19
5431 // end-sanitize-tx19
5433 unsigned32 instruction = instruction_0;
5434 int destreg = ((instruction >> 6) & 0x0000001F);
5435 int fs = ((instruction >> 11) & 0x0000001F);
5436 int format = ((instruction >> 21) & 0x00000007);
5438 if ((format != fmt_single) && (format != fmt_double))
5439 SignalException(ReservedInstruction,instruction);
5441 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5447 // MIPS Architecture:
5449 // System Control Instruction Set (COP0)
5453 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5455 *mipsI,mipsII,mipsIII,mipsIV:
5457 // start-sanitize-vr4320
5459 // end-sanitize-vr4320
5460 // start-sanitize-cygnus
5462 // end-sanitize-cygnus
5465 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5467 *mipsI,mipsII,mipsIII,mipsIV:
5469 // start-sanitize-vr4320
5471 // end-sanitize-vr4320
5472 // start-sanitize-cygnus
5474 // end-sanitize-cygnus
5477 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5479 *mipsI,mipsII,mipsIII,mipsIV:
5483 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5485 *mipsI,mipsII,mipsIII,mipsIV:
5487 // start-sanitize-vr4320
5489 // end-sanitize-vr4320
5490 // start-sanitize-cygnus
5492 // end-sanitize-cygnus
5495 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5499 // start-sanitize-vr4320
5501 // end-sanitize-vr4320
5502 // start-sanitize-cygnus
5504 // end-sanitize-cygnus
5506 // start-sanitize-tx19
5508 // end-sanitize-tx19
5510 unsigned32 instruction = instruction_0;
5511 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5512 int hint = ((instruction >> 16) & 0x0000001F);
5513 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5515 address_word vaddr = (op1 + offset);
5518 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5519 CacheOp(hint,vaddr,paddr,instruction);
5524 010000,10000,000000000000000,111001:COP0:32::DI
5526 *mipsI,mipsII,mipsIII,mipsIV:
5528 // start-sanitize-vr4320
5530 // end-sanitize-vr4320
5531 // start-sanitize-cygnus
5533 // end-sanitize-cygnus
5536 010000,10000,000000000000000,111000:COP0:32::EI
5538 *mipsI,mipsII,mipsIII,mipsIV:
5540 // start-sanitize-vr4320
5542 // end-sanitize-vr4320
5543 // start-sanitize-cygnus
5545 // end-sanitize-cygnus
5548 010000,10000,000000000000000,011000:COP0:32::ERET
5553 // start-sanitize-vr4320
5555 // end-sanitize-vr4320
5556 // start-sanitize-cygnus
5558 // end-sanitize-cygnus
5559 // start-sanitize-r5900
5561 // end-sanitize-r5900
5563 if (SR & status_ERL)
5565 /* Oops, not yet available */
5566 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5578 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5579 "mfc0 r<RT>, r<RD> # <REGX>"
5580 *mipsI,mipsII,mipsIII,mipsIV:
5583 // start-sanitize-vr4320
5585 // end-sanitize-vr4320
5586 // start-sanitize-cygnus
5588 // end-sanitize-cygnus
5589 // start-sanitize-r5900
5591 // end-sanitize-r5900
5593 TRACE_ALU_INPUT0 ();
5594 DecodeCoproc (instruction_0);
5595 TRACE_ALU_RESULT (GPR[RT]);
5598 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5599 "mtc0 r<RT>, r<RD> # <REGX>"
5600 *mipsI,mipsII,mipsIII,mipsIV:
5601 // start-sanitize-tx19
5603 // end-sanitize-tx19
5605 // start-sanitize-vr4320
5607 // end-sanitize-vr4320
5609 // start-sanitize-cygnus
5611 // end-sanitize-cygnus
5612 // start-sanitize-r5900
5614 // end-sanitize-r5900
5616 DecodeCoproc (instruction_0);
5620 010000,10000,000000000000000,010000:COP0:32::RFE
5622 *mipsI,mipsII,mipsIII,mipsIV:
5623 // start-sanitize-tx19
5625 // end-sanitize-tx19
5627 // start-sanitize-vr4320
5629 // end-sanitize-vr4320
5631 // start-sanitize-cygnus
5633 // end-sanitize-cygnus
5634 // start-sanitize-r5900
5636 // end-sanitize-r5900
5638 DecodeCoproc (instruction_0);
5642 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5643 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5644 *mipsI,mipsII,mipsIII,mipsIV:
5645 // start-sanitize-r5900
5647 // end-sanitize-r5900
5649 // start-sanitize-tx19
5651 // end-sanitize-tx19
5653 DecodeCoproc (instruction_0);
5658 010000,10000,000000000000000,001000:COP0:32::TLBP
5660 *mipsI,mipsII,mipsIII,mipsIV:
5662 // start-sanitize-vr4320
5664 // end-sanitize-vr4320
5665 // start-sanitize-cygnus
5667 // end-sanitize-cygnus
5670 010000,10000,000000000000000,000001:COP0:32::TLBR
5672 *mipsI,mipsII,mipsIII,mipsIV:
5674 // start-sanitize-vr4320
5676 // end-sanitize-vr4320
5677 // start-sanitize-cygnus
5679 // end-sanitize-cygnus
5682 010000,10000,000000000000000,000010:COP0:32::TLBWI
5684 *mipsI,mipsII,mipsIII,mipsIV:
5686 // start-sanitize-vr4320
5688 // end-sanitize-vr4320
5689 // start-sanitize-cygnus
5691 // end-sanitize-cygnus
5694 010000,10000,000000000000000,000110:COP0:32::TLBWR
5696 *mipsI,mipsII,mipsIII,mipsIV:
5698 // start-sanitize-vr4320
5700 // end-sanitize-vr4320
5701 // start-sanitize-cygnus
5703 // end-sanitize-cygnus
5707 // start-sanitize-cygnus
5708 :include:64,f::mdmx.igen
5709 // end-sanitize-cygnus
5710 // start-sanitize-r5900
5711 :include::r5900:r5900.igen
5712 // end-sanitize-r5900
5716 // start-sanitize-cygnus-never
5718 // // FIXME FIXME FIXME What is this instruction?
5719 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5724 // // start-sanitize-r5900
5726 // // end-sanitize-r5900
5728 // // start-sanitize-tx19
5730 // // end-sanitize-tx19
5732 // unsigned32 instruction = instruction_0;
5733 // signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5734 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5735 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5737 // if (CoProcPresent(3))
5738 // SignalException(CoProcessorUnusable);
5740 // SignalException(ReservedInstruction,instruction);
5744 // end-sanitize-cygnus-never
5745 // start-sanitize-cygnus-never
5747 // // FIXME FIXME FIXME What is this?
5748 // 11100,******,00001:RR:16::SDBBP
5751 // unsigned32 instruction = instruction_0;
5752 // if (have_extendval)
5753 // SignalException (ReservedInstruction, instruction);
5755 // SignalException(DebugBreakPoint,instruction);
5759 // end-sanitize-cygnus-never
5760 // start-sanitize-cygnus-never
5762 // // FIXME FIXME FIXME What is this?
5763 // 000000,********************,001110:SPECIAL:32::SDBBP
5766 // unsigned32 instruction = instruction_0;
5768 // SignalException(DebugBreakPoint,instruction);
5772 // end-sanitize-cygnus-never