1 //Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0/c_dsp32mac_dr_a1a0.dsp
2 // Spec Reference: dsp32mac dr_a1a0
5 .include "testutils.inc"
12 // The result accumulated in A , and stored to a reg half
17 imm32 r4, 0x12efbc5569;
22 R6.H = (A1 += R0.L * R0.L), R6.L = (A0 = R0.L * R0.L);
25 R1.H = (A1 += R2.L * R3.L), R1.L = (A0 -= R2.H * R3.L);
28 R2.H = (A1 -= R4.L * R5.L), R2.L = (A0 += R4.H * R5.H);
31 R3.H = (A1 += R0.L * R7.L), R3.L = (A0 += R0.L * R7.H);
34 CHECKREG r0, 0x13545ABD;
35 CHECKREG r1, 0x7FFF0964;
36 CHECKREG r2, 0x71380FD8;
37 CHECKREG r3, 0x21D909DC;
38 CHECKREG r4, 0x21D8C27A;
39 CHECKREG r5, 0x09DB89BE;
40 CHECKREG r6, 0x40534053;
41 CHECKREG r7, 0xF78E9008;
42 CHECKREG p1, 0x4052DF12;
43 CHECKREG p2, 0x4052DF12;
44 CHECKREG p3, 0xAAA259B0;
45 CHECKREG p4, 0x0963CE3A;
46 CHECKREG p5, 0x713876AA;
47 CHECKREG fp, 0x0FD82A12;
58 R0.H = (A1 += R1.L * R0.H), R0.L = (A0 = R1.L * R0.L);
61 R6.H = (A1 += R2.L * R2.H), R6.L = (A0 -= R2.H * R2.L);
64 R2.H = (A1 -= R4.L * R5.H), R2.L = (A0 += R4.H * R5.H);
67 R3.H = (A1 += R3.L * R7.H), R3.L = (A0 -= R3.L * R7.H);
70 CHECKREG r0, 0xFFD1FF22;
71 CHECKREG r1, 0x22BCFEC7;
72 CHECKREG r2, 0x80007FFF;
73 CHECKREG r3, 0x80007FFF;
74 CHECKREG r4, 0x721A320A;
75 CHECKREG r5, 0xA6989CC2;
76 CHECKREG r6, 0xC0033EF0;
77 CHECKREG r7, 0xF98E9008;
78 CHECKREG p1, 0xFFD0BC98;
79 CHECKREG p2, 0xFF221DD6;
80 CHECKREG p3, 0xC002B3C0;
81 CHECKREG p4, 0x3EF026AE;
82 CHECKREG p5, 0x6C76CC46;
83 CHECKREG fp, 0xAC3C0286;
94 R0.H = (A1 -= R1.H * R0.L), R0.L = (A0 = R1.L * R0.L);
97 R1.H = (A1 += R2.H * R3.L), R1.L = (A0 -= R2.H * R3.L);
100 R2.H = (A1 = R4.H * R5.L), R2.L = (A0 += R4.H * R5.H);
103 R3.H = (A1 -= R6.H * R7.L), R3.L = (A0 += R6.L * R7.H);
106 CHECKREG r0, 0xD0B1FF22;
107 CHECKREG r1, 0x89A8462B;
108 CHECKREG r2, 0x55DDD39D;
109 CHECKREG r3, 0xF3EF2BB9;
110 CHECKREG r4, 0xF3EEC968;
111 CHECKREG r5, 0x2BB8C982;
112 CHECKREG r6, 0x900C807D;
113 CHECKREG r7, 0xA78E9008;
114 CHECKREG p1, 0xD0B14668;
115 CHECKREG p2, 0xFF221DD6;
116 CHECKREG p3, 0x89A83740;
117 CHECKREG p4, 0x462B2CFE;
118 CHECKREG p5, 0x55DD4A28;
119 CHECKREG fp, 0xD39D28D6;
121 imm32 r0, 0x03545abd;
122 imm32 r1, 0xb3bcfec7;
123 imm32 r2, 0x24348679;
124 imm32 r3, 0x60049007;
125 imm32 r4, 0x7fbc5569;
126 imm32 r5, 0x9d35560b;
127 imm32 r6, 0xa00c807d;
128 imm32 r7, 0x078e9008;
130 R0.H = (A1 += R1.H * R0.H), R0.L = (A0 -= R1.L * R0.L);
133 R1.H = (A1 -= R2.H * R3.H), R1.L = (A0 = R2.H * R3.L);
136 R2.H = (A1 = R4.H * R5.H), R2.L = (A0 += R4.H * R5.H);
139 R3.H = (A1 += R6.H * R7.H), R3.L = (A0 -= R6.L * R7.H);
142 CHECKREG r0, 0xFE0400DE;
143 CHECKREG r1, 0xE2DCE054;
144 CHECKREG r2, 0x9D698000;
145 CHECKREG r3, 0x97C08545;
146 CHECKREG r4, 0x97BFB128;
147 CHECKREG r5, 0x85449604;
148 CHECKREG r6, 0xA00C807D;
149 CHECKREG r7, 0x078E9008;
150 CHECKREG p1, 0xFE045B60;
151 CHECKREG p2, 0x00DDE22A;
152 CHECKREG p3, 0xE2DC39C0;
153 CHECKREG p4, 0xE0547AD8;
154 CHECKREG p5, 0x9D697BD8;
155 CHECKREG fp, 0x7DBDF6B0;