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git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/v850/sim-main.h
a4c57af01050eae85878be748fca8e1b23ff59fa
2 #define WITH_MODULO_MEMORY 1
3 #define WITH_WATCHPOINTS 1
4 #define WITH_TARGET_WORD_MSB 31
6 #include "sim-basics.h"
9 typedef address_word sim_cia
;
12 /* This simulator doesn't cache state */
13 #define SIM_ENGINE_HALT_HOOK(sd,last_cpu,cia) while (0)
14 #define SIM_ENGINE_RESTART_HOOK(sd,last_cpu,cia) while (0)
16 /* Get the number of instructions. FIXME: must be a more elegant way
19 #define MAX_INSNS (nr_itable_entries)
20 #define INSN_NAME(i) itable[(i)].name
29 typedef unsigned8 uint8
;
30 typedef signed16 int16
;
31 typedef unsigned16 uint16
;
32 typedef signed32 int32
;
33 typedef unsigned32 uint32
;
34 typedef unsigned32 reg_t
;
37 /* The current state of the processor; registers, memory, etc. */
39 typedef struct _v850_regs
{
40 reg_t regs
[32]; /* general-purpose registers */
41 reg_t sregs
[32]; /* system registers, including psw */
43 int dummy_mem
; /* where invalid accesses go */
48 /* ... simulator specific members ... */
50 reg_t psw_mask
; /* only allow non-reserved bits to be set */
51 sim_event
*pending_nmi
;
52 /* ... base type ... */
56 #define CPU_CIA(CPU) ((CPU)->reg.pc)
59 sim_cpu cpu
[MAX_NR_PROCESSORS
];
61 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
63 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
75 /* For compatibility, until all functions converted to passing
76 SIM_DESC as an argument */
77 extern SIM_DESC simulator
;
80 #define V850_ROM_SIZE 0x8000
81 #define V850_LOW_END 0x200000
82 #define V850_HIGH_START 0xffe000
85 #define SIG_V850_EXIT -1 /* indication of a normal exit */
88 /* Because we are still using the old semantic table, provide compat
89 macro's that store the instruction where the old simops expects
94 OP
[0] = inst
& 0x1f; /* RRRRR -> reg1 */
95 OP
[1] = (inst
>> 11) & 0x1f; /* rrrrr -> reg2 */
96 OP
[2] = (inst
>> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
102 OP[0] = instruction_0 & 0x1f; \
103 OP[1] = (instruction_0 >> 11) & 0x1f; \
105 OP[3] = instruction_0
107 #define COMPAT_1(CALL) \
114 OP[0] = instruction_0 & 0x1f; \
115 OP[1] = (instruction_0 >> 11) & 0x1f; \
116 OP[2] = instruction_1; \
117 OP[3] = (instruction_1 << 16) | instruction_0
119 #define COMPAT_2(CALL) \
126 #define GR ((CPU)->reg.regs)
127 #define SR ((CPU)->reg.sregs)
130 #define State (STATE_CPU (simulator, 0)->reg)
131 #define PC (State.pc)
132 #define SP (State.regs[3])
133 #define EP (State.regs[30])
135 #define EIPC (State.sregs[0])
136 #define EIPSW (State.sregs[1])
137 #define FEPC (State.sregs[2])
138 #define FEPSW (State.sregs[3])
139 #define ECR (State.sregs[4])
140 #define PSW (State.sregs[5])
141 /* start-sanitize-v850e */
142 #define CTPC (SR[16])
143 #define CTPSW (SR[17])
144 /* end-sanitize-v850e */
145 #define DBPC (State.sregs[18])
146 #define DBPSW (State.sregs[19])
147 /* start-sanitize-v850e */
148 #define CTBP (State.sregs[20])
149 /* end-sanitize-v850e */
151 /* start-sanitize-v850eq */
152 #define PSW_US BIT32 (8)
153 /* end-sanitize-v850eq */
163 #define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
165 /* sign-extend a 4-bit number */
166 #define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
168 /* sign-extend a 5-bit number */
169 #define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
171 /* sign-extend a 9-bit number */
172 #define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
174 /* sign-extend a 22-bit number */
175 #define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
177 /* sign extend a 40 bit number */
178 #define SEXT40(x) ((((x) & UNSIGNED64 (0xffffffffff)) \
179 ^ (~UNSIGNED64 (0x7fffffffff))) \
180 + UNSIGNED64 (0x8000000000))
182 /* sign extend a 44 bit number */
183 #define SEXT44(x) ((((x) & UNSIGNED64 (0xfffffffffff)) \
184 ^ (~ UNSIGNED64 (0x7ffffffffff))) \
185 + UNSIGNED64 (0x80000000000))
187 /* sign extend a 60 bit number */
188 #define SEXT60(x) ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
189 ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
190 + UNSIGNED64 (0x800000000000000))
192 /* No sign extension */
195 #define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
197 #define RLW(x) load_mem (x, 4)
208 /* Function declarations. */
211 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
212 PC, sim_core_execute_map, (EA))
214 #define IMEM_IMMED(EA,N) \
215 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
216 PC, sim_core_execute_map, (EA) + (N) * 2)
218 #define load_mem(ADDR,LEN) \
219 sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
220 PC, sim_core_read_map, (ADDR))
222 #define store_mem(ADDR,LEN,DATA) \
223 sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
224 PC, sim_core_write_map, (ADDR), (DATA))
227 /* Debug/tracing calls */
256 /* start-sanitize-v850e */
260 /* end-sanitize-v850e */
261 /* start-sanitize-v850eq */
266 /* end-sanitize-v850eq */
270 void trace_input
PARAMS ((char *name
, enum op_types type
, int size
));
271 void trace_output
PARAMS ((enum op_types result
));
272 void trace_result
PARAMS ((int has_result
, unsigned32 result
));
274 extern int trace_num_values
;
275 extern unsigned32 trace_values
[];
276 extern unsigned32 trace_pc
;
277 extern const char *trace_name
;
278 extern const char *trace_module
;
280 #define TRACE_ALU_INPUT0() \
282 if (TRACE_ALU_P (CPU)) { \
283 trace_module = "alu"; \
285 trace_name = itable[MY_INDEX].name; \
286 trace_num_values = 0; \
290 #define TRACE_ALU_INPUT1(IN1) \
292 if (TRACE_ALU_P (CPU)) { \
293 trace_module = "alu"; \
295 trace_name = itable[MY_INDEX].name; \
296 trace_values[0] = (IN1); \
297 trace_num_values = 1; \
301 #define TRACE_ALU_INPUT2(IN1, IN2) \
303 if (TRACE_ALU_P (CPU)) { \
304 trace_module = "alu"; \
306 trace_name = itable[MY_INDEX].name; \
307 trace_values[0] = (IN1); \
308 trace_values[1] = (IN2); \
309 trace_num_values = 2; \
313 #define TRACE_ALU_RESULT(RESULT) \
315 if (TRACE_ALU_P (CPU)) { \
316 trace_result (1, (RESULT)); \
320 #define TRACE_BRANCH1(IN1) \
322 if (TRACE_BRANCH_P (CPU)) { \
323 trace_module = "branch"; \
325 trace_name = itable[MY_INDEX].name; \
326 trace_values[0] = (IN1); \
327 trace_num_values = 1; \
328 trace_result (1, (nia)); \
332 #define TRACE_BRANCH2(IN1, IN2) \
334 if (TRACE_BRANCH_P (CPU)) { \
335 trace_module = "branch"; \
337 trace_name = itable[MY_INDEX].name; \
338 trace_values[0] = (IN1); \
339 trace_values[1] = (IN2); \
340 trace_num_values = 2; \
341 trace_result (1, (nia)); \
345 #define TRACE_BRANCH3(IN1, IN2, IN3) \
347 if (TRACE_BRANCH_P (CPU)) { \
348 trace_module = "branch"; \
350 trace_name = itable[MY_INDEX].name; \
351 trace_values[0] = (IN1); \
352 trace_values[1] = (IN2); \
353 trace_values[2] = (IN3); \
354 trace_num_values = 3; \
355 trace_result (1, (nia)); \
361 #define trace_input(NAME, IN1, IN2)
362 #define trace_output(RESULT)
363 #define trace_result(HAS_RESULT, RESULT)
365 #define TRACE_ALU_INPUT0()
366 #define TRACE_ALU_INPUT1(IN1)
367 #define TRACE_ALU_INPUT2(IN1, IN2)
368 #define TRACE_ALU_RESULT(RESULT)
370 #define TRACE_BRANCH1(IN1)
371 #define TRACE_BRANCH2(IN1, IN2)
372 #define TRACE_BRANCH2(IN1, IN2, IN3)
376 /* start-sanitize-v850eq */
377 extern void divun ( unsigned int N
,
378 unsigned long int als
,
379 unsigned long int sfi
,
380 unsigned long int * quotient_ptr
,
381 unsigned long int * remainder_ptr
,
382 boolean
* overflow_ptr
384 extern void divn ( unsigned int N
,
385 unsigned long int als
,
386 unsigned long int sfi
,
387 signed long int * quotient_ptr
,
388 signed long int * remainder_ptr
,
389 boolean
* overflow_ptr
391 /* end-sanitize-v850eq */
392 /* start-sanitize-v850e */
393 extern int type1_regs
[];
394 extern int type2_regs
[];
395 /* end-sanitize-v850e */
396 /* start-sanitize-v850eq */
397 extern int type3_regs
[];
398 /* end-sanitize-v850eq */