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[thirdparty/linux.git] / sound / pci / hda / hda_intel.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 *
4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
6 *
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
21 */
22
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/mutex.h>
33 #include <linux/io.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clocksource.h>
36 #include <linux/time.h>
37 #include <linux/completion.h>
38 #include <linux/acpi.h>
39
40 #ifdef CONFIG_X86
41 /* for snoop control */
42 #include <asm/pgtable.h>
43 #include <asm/set_memory.h>
44 #include <asm/cpufeature.h>
45 #endif
46 #include <sound/core.h>
47 #include <sound/initval.h>
48 #include <sound/hdaudio.h>
49 #include <sound/hda_i915.h>
50 #include <sound/intel-dsp-config.h>
51 #include <linux/vgaarb.h>
52 #include <linux/vga_switcheroo.h>
53 #include <linux/firmware.h>
54 #include <sound/hda_codec.h>
55 #include "hda_controller.h"
56 #include "hda_intel.h"
57
58 #define CREATE_TRACE_POINTS
59 #include "hda_intel_trace.h"
60
61 /* position fix mode */
62 enum {
63 POS_FIX_AUTO,
64 POS_FIX_LPIB,
65 POS_FIX_POSBUF,
66 POS_FIX_VIACOMBO,
67 POS_FIX_COMBO,
68 POS_FIX_SKL,
69 POS_FIX_FIFO,
70 };
71
72 /* Defines for ATI HD Audio support in SB450 south bridge */
73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
75
76 /* Defines for Nvidia HDA support */
77 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
78 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
79 #define NVIDIA_HDA_ISTRM_COH 0x4d
80 #define NVIDIA_HDA_OSTRM_COH 0x4c
81 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
82
83 /* Defines for Intel SCH HDA snoop control */
84 #define INTEL_HDA_CGCTL 0x48
85 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
86 #define INTEL_SCH_HDA_DEVC 0x78
87 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
88
89 /* Define VIA HD Audio Device ID*/
90 #define VIA_HDAC_DEVICE_ID 0x3288
91
92 /* max number of SDs */
93 /* ICH, ATI and VIA have 4 playback and 4 capture */
94 #define ICH6_NUM_CAPTURE 4
95 #define ICH6_NUM_PLAYBACK 4
96
97 /* ULI has 6 playback and 5 capture */
98 #define ULI_NUM_CAPTURE 5
99 #define ULI_NUM_PLAYBACK 6
100
101 /* ATI HDMI may have up to 8 playbacks and 0 capture */
102 #define ATIHDMI_NUM_CAPTURE 0
103 #define ATIHDMI_NUM_PLAYBACK 8
104
105 /* TERA has 4 playback and 3 capture */
106 #define TERA_NUM_CAPTURE 3
107 #define TERA_NUM_PLAYBACK 4
108
109
110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
113 static char *model[SNDRV_CARDS];
114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
117 static int probe_only[SNDRV_CARDS];
118 static int jackpoll_ms[SNDRV_CARDS];
119 static int single_cmd = -1;
120 static int enable_msi = -1;
121 #ifdef CONFIG_SND_HDA_PATCH_LOADER
122 static char *patch[SNDRV_CARDS];
123 #endif
124 #ifdef CONFIG_SND_HDA_INPUT_BEEP
125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
126 CONFIG_SND_HDA_INPUT_BEEP_MODE};
127 #endif
128 static bool dmic_detect = 1;
129
130 module_param_array(index, int, NULL, 0444);
131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
132 module_param_array(id, charp, NULL, 0444);
133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
134 module_param_array(enable, bool, NULL, 0444);
135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
136 module_param_array(model, charp, NULL, 0444);
137 MODULE_PARM_DESC(model, "Use the given board model.");
138 module_param_array(position_fix, int, NULL, 0444);
139 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
141 module_param_array(bdl_pos_adj, int, NULL, 0644);
142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
143 module_param_array(probe_mask, int, NULL, 0444);
144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
145 module_param_array(probe_only, int, NULL, 0444);
146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
147 module_param_array(jackpoll_ms, int, NULL, 0444);
148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
149 module_param(single_cmd, bint, 0444);
150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
151 "(for debugging only).");
152 module_param(enable_msi, bint, 0444);
153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
154 #ifdef CONFIG_SND_HDA_PATCH_LOADER
155 module_param_array(patch, charp, NULL, 0444);
156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
157 #endif
158 #ifdef CONFIG_SND_HDA_INPUT_BEEP
159 module_param_array(beep_mode, bool, NULL, 0444);
160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
161 "(0=off, 1=on) (default=1).");
162 #endif
163 module_param(dmic_detect, bool, 0444);
164 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
165 "(0=off, 1=on) (default=1); "
166 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
167
168 #ifdef CONFIG_PM
169 static int param_set_xint(const char *val, const struct kernel_param *kp);
170 static const struct kernel_param_ops param_ops_xint = {
171 .set = param_set_xint,
172 .get = param_get_int,
173 };
174 #define param_check_xint param_check_int
175
176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
177 module_param(power_save, xint, 0644);
178 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
179 "(in second, 0 = disable).");
180
181 static bool pm_blacklist = true;
182 module_param(pm_blacklist, bool, 0644);
183 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
184
185 /* reset the HD-audio controller in power save mode.
186 * this may give more power-saving, but will take longer time to
187 * wake up.
188 */
189 static bool power_save_controller = 1;
190 module_param(power_save_controller, bool, 0644);
191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
192 #else
193 #define power_save 0
194 #endif /* CONFIG_PM */
195
196 static int align_buffer_size = -1;
197 module_param(align_buffer_size, bint, 0644);
198 MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
200
201 #ifdef CONFIG_X86
202 static int hda_snoop = -1;
203 module_param_named(snoop, hda_snoop, bint, 0444);
204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
205 #else
206 #define hda_snoop true
207 #endif
208
209
210 MODULE_LICENSE("GPL");
211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
212 "{Intel, ICH6M},"
213 "{Intel, ICH7},"
214 "{Intel, ESB2},"
215 "{Intel, ICH8},"
216 "{Intel, ICH9},"
217 "{Intel, ICH10},"
218 "{Intel, PCH},"
219 "{Intel, CPT},"
220 "{Intel, PPT},"
221 "{Intel, LPT},"
222 "{Intel, LPT_LP},"
223 "{Intel, WPT_LP},"
224 "{Intel, SPT},"
225 "{Intel, SPT_LP},"
226 "{Intel, HPT},"
227 "{Intel, PBG},"
228 "{Intel, SCH},"
229 "{ATI, SB450},"
230 "{ATI, SB600},"
231 "{ATI, RS600},"
232 "{ATI, RS690},"
233 "{ATI, RS780},"
234 "{ATI, R600},"
235 "{ATI, RV630},"
236 "{ATI, RV610},"
237 "{ATI, RV670},"
238 "{ATI, RV635},"
239 "{ATI, RV620},"
240 "{ATI, RV770},"
241 "{VIA, VT8251},"
242 "{VIA, VT8237A},"
243 "{SiS, SIS966},"
244 "{ULI, M5461}}");
245 MODULE_DESCRIPTION("Intel HDA driver");
246
247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
249 #define SUPPORT_VGA_SWITCHEROO
250 #endif
251 #endif
252
253
254 /*
255 */
256
257 /* driver types */
258 enum {
259 AZX_DRIVER_ICH,
260 AZX_DRIVER_PCH,
261 AZX_DRIVER_SCH,
262 AZX_DRIVER_SKL,
263 AZX_DRIVER_HDMI,
264 AZX_DRIVER_ATI,
265 AZX_DRIVER_ATIHDMI,
266 AZX_DRIVER_ATIHDMI_NS,
267 AZX_DRIVER_VIA,
268 AZX_DRIVER_SIS,
269 AZX_DRIVER_ULI,
270 AZX_DRIVER_NVIDIA,
271 AZX_DRIVER_TERA,
272 AZX_DRIVER_CTX,
273 AZX_DRIVER_CTHDA,
274 AZX_DRIVER_CMEDIA,
275 AZX_DRIVER_ZHAOXIN,
276 AZX_DRIVER_GENERIC,
277 AZX_NUM_DRIVERS, /* keep this as last entry */
278 };
279
280 #define azx_get_snoop_type(chip) \
281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
283
284 /* quirks for old Intel chipsets */
285 #define AZX_DCAPS_INTEL_ICH \
286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE |\
287 AZX_DCAPS_SYNC_WRITE)
288
289 /* quirks for Intel PCH */
290 #define AZX_DCAPS_INTEL_PCH_BASE \
291 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
292 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
293
294 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
295 #define AZX_DCAPS_INTEL_PCH_NOPM \
296 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
297
298 /* PCH for HSW/BDW; with runtime PM */
299 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
300 #define AZX_DCAPS_INTEL_PCH \
301 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
302
303 /* HSW HDMI */
304 #define AZX_DCAPS_INTEL_HASWELL \
305 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
306 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
307 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
308
309 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
310 #define AZX_DCAPS_INTEL_BROADWELL \
311 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
312 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
313 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
314
315 #define AZX_DCAPS_INTEL_BAYTRAIL \
316 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
317
318 #define AZX_DCAPS_INTEL_BRASWELL \
319 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
320 AZX_DCAPS_I915_COMPONENT)
321
322 #define AZX_DCAPS_INTEL_SKYLAKE \
323 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
324 AZX_DCAPS_SYNC_WRITE |\
325 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
326
327 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
328
329 /* quirks for ATI SB / AMD Hudson */
330 #define AZX_DCAPS_PRESET_ATI_SB \
331 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
332 AZX_DCAPS_SNOOP_TYPE(ATI))
333
334 /* quirks for ATI/AMD HDMI */
335 #define AZX_DCAPS_PRESET_ATI_HDMI \
336 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
337 AZX_DCAPS_NO_MSI64)
338
339 /* quirks for ATI HDMI with snoop off */
340 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
341 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
342
343 /* quirks for AMD SB */
344 #define AZX_DCAPS_PRESET_AMD_SB \
345 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
346 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
347
348 /* quirks for Nvidia */
349 #define AZX_DCAPS_PRESET_NVIDIA \
350 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
351 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
352
353 #define AZX_DCAPS_PRESET_CTHDA \
354 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
355 AZX_DCAPS_NO_64BIT |\
356 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
357
358 /*
359 * vga_switcheroo support
360 */
361 #ifdef SUPPORT_VGA_SWITCHEROO
362 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
363 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
364 #else
365 #define use_vga_switcheroo(chip) 0
366 #define needs_eld_notify_link(chip) false
367 #endif
368
369 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
370 ((pci)->device == 0x0c0c) || \
371 ((pci)->device == 0x0d0c) || \
372 ((pci)->device == 0x160c))
373
374 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
375
376 static const char * const driver_short_names[] = {
377 [AZX_DRIVER_ICH] = "HDA Intel",
378 [AZX_DRIVER_PCH] = "HDA Intel PCH",
379 [AZX_DRIVER_SCH] = "HDA Intel MID",
380 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
381 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
382 [AZX_DRIVER_ATI] = "HDA ATI SB",
383 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
384 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
385 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
386 [AZX_DRIVER_SIS] = "HDA SIS966",
387 [AZX_DRIVER_ULI] = "HDA ULI M5461",
388 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
389 [AZX_DRIVER_TERA] = "HDA Teradici",
390 [AZX_DRIVER_CTX] = "HDA Creative",
391 [AZX_DRIVER_CTHDA] = "HDA Creative",
392 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
393 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
394 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
395 };
396
397 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
398 static void set_default_power_save(struct azx *chip);
399
400 /*
401 * initialize the PCI registers
402 */
403 /* update bits in a PCI register byte */
404 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
405 unsigned char mask, unsigned char val)
406 {
407 unsigned char data;
408
409 pci_read_config_byte(pci, reg, &data);
410 data &= ~mask;
411 data |= (val & mask);
412 pci_write_config_byte(pci, reg, data);
413 }
414
415 static void azx_init_pci(struct azx *chip)
416 {
417 int snoop_type = azx_get_snoop_type(chip);
418
419 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
420 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
421 * Ensuring these bits are 0 clears playback static on some HD Audio
422 * codecs.
423 * The PCI register TCSEL is defined in the Intel manuals.
424 */
425 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
426 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
427 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
428 }
429
430 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
431 * we need to enable snoop.
432 */
433 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
434 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
435 azx_snoop(chip));
436 update_pci_byte(chip->pci,
437 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
438 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
439 }
440
441 /* For NVIDIA HDA, enable snoop */
442 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
443 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
444 azx_snoop(chip));
445 update_pci_byte(chip->pci,
446 NVIDIA_HDA_TRANSREG_ADDR,
447 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
448 update_pci_byte(chip->pci,
449 NVIDIA_HDA_ISTRM_COH,
450 0x01, NVIDIA_HDA_ENABLE_COHBIT);
451 update_pci_byte(chip->pci,
452 NVIDIA_HDA_OSTRM_COH,
453 0x01, NVIDIA_HDA_ENABLE_COHBIT);
454 }
455
456 /* Enable SCH/PCH snoop if needed */
457 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
458 unsigned short snoop;
459 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
460 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
461 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
462 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
463 if (!azx_snoop(chip))
464 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
465 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
466 pci_read_config_word(chip->pci,
467 INTEL_SCH_HDA_DEVC, &snoop);
468 }
469 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
470 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
471 "Disabled" : "Enabled");
472 }
473 }
474
475 /*
476 * In BXT-P A0, HD-Audio DMA requests is later than expected,
477 * and makes an audio stream sensitive to system latencies when
478 * 24/32 bits are playing.
479 * Adjusting threshold of DMA fifo to force the DMA request
480 * sooner to improve latency tolerance at the expense of power.
481 */
482 static void bxt_reduce_dma_latency(struct azx *chip)
483 {
484 u32 val;
485
486 val = azx_readl(chip, VS_EM4L);
487 val &= (0x3 << 20);
488 azx_writel(chip, VS_EM4L, val);
489 }
490
491 /*
492 * ML_LCAP bits:
493 * bit 0: 6 MHz Supported
494 * bit 1: 12 MHz Supported
495 * bit 2: 24 MHz Supported
496 * bit 3: 48 MHz Supported
497 * bit 4: 96 MHz Supported
498 * bit 5: 192 MHz Supported
499 */
500 static int intel_get_lctl_scf(struct azx *chip)
501 {
502 struct hdac_bus *bus = azx_bus(chip);
503 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
504 u32 val, t;
505 int i;
506
507 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
508
509 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
510 t = preferred_bits[i];
511 if (val & (1 << t))
512 return t;
513 }
514
515 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
516 return 0;
517 }
518
519 static int intel_ml_lctl_set_power(struct azx *chip, int state)
520 {
521 struct hdac_bus *bus = azx_bus(chip);
522 u32 val;
523 int timeout;
524
525 /*
526 * the codecs are sharing the first link setting by default
527 * If other links are enabled for stream, they need similar fix
528 */
529 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
530 val &= ~AZX_MLCTL_SPA;
531 val |= state << AZX_MLCTL_SPA_SHIFT;
532 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
533 /* wait for CPA */
534 timeout = 50;
535 while (timeout) {
536 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
537 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
538 return 0;
539 timeout--;
540 udelay(10);
541 }
542
543 return -1;
544 }
545
546 static void intel_init_lctl(struct azx *chip)
547 {
548 struct hdac_bus *bus = azx_bus(chip);
549 u32 val;
550 int ret;
551
552 /* 0. check lctl register value is correct or not */
553 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
554 /* if SCF is already set, let's use it */
555 if ((val & ML_LCTL_SCF_MASK) != 0)
556 return;
557
558 /*
559 * Before operating on SPA, CPA must match SPA.
560 * Any deviation may result in undefined behavior.
561 */
562 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
563 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
564 return;
565
566 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
567 ret = intel_ml_lctl_set_power(chip, 0);
568 udelay(100);
569 if (ret)
570 goto set_spa;
571
572 /* 2. update SCF to select a properly audio clock*/
573 val &= ~ML_LCTL_SCF_MASK;
574 val |= intel_get_lctl_scf(chip);
575 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
576
577 set_spa:
578 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
579 intel_ml_lctl_set_power(chip, 1);
580 udelay(100);
581 }
582
583 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
584 {
585 struct hdac_bus *bus = azx_bus(chip);
586 struct pci_dev *pci = chip->pci;
587 u32 val;
588
589 snd_hdac_set_codec_wakeup(bus, true);
590 if (chip->driver_type == AZX_DRIVER_SKL) {
591 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
592 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
593 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
594 }
595 azx_init_chip(chip, full_reset);
596 if (chip->driver_type == AZX_DRIVER_SKL) {
597 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
598 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
599 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
600 }
601
602 snd_hdac_set_codec_wakeup(bus, false);
603
604 /* reduce dma latency to avoid noise */
605 if (IS_BXT(pci))
606 bxt_reduce_dma_latency(chip);
607
608 if (bus->mlcap != NULL)
609 intel_init_lctl(chip);
610 }
611
612 /* calculate runtime delay from LPIB */
613 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
614 unsigned int pos)
615 {
616 struct snd_pcm_substream *substream = azx_dev->core.substream;
617 int stream = substream->stream;
618 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
619 int delay;
620
621 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
622 delay = pos - lpib_pos;
623 else
624 delay = lpib_pos - pos;
625 if (delay < 0) {
626 if (delay >= azx_dev->core.delay_negative_threshold)
627 delay = 0;
628 else
629 delay += azx_dev->core.bufsize;
630 }
631
632 if (delay >= azx_dev->core.period_bytes) {
633 dev_info(chip->card->dev,
634 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
635 delay, azx_dev->core.period_bytes);
636 delay = 0;
637 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
638 chip->get_delay[stream] = NULL;
639 }
640
641 return bytes_to_frames(substream->runtime, delay);
642 }
643
644 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
645
646 /* called from IRQ */
647 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
648 {
649 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
650 int ok;
651
652 ok = azx_position_ok(chip, azx_dev);
653 if (ok == 1) {
654 azx_dev->irq_pending = 0;
655 return ok;
656 } else if (ok == 0) {
657 /* bogus IRQ, process it later */
658 azx_dev->irq_pending = 1;
659 schedule_work(&hda->irq_pending_work);
660 }
661 return 0;
662 }
663
664 #define display_power(chip, enable) \
665 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
666
667 /*
668 * Check whether the current DMA position is acceptable for updating
669 * periods. Returns non-zero if it's OK.
670 *
671 * Many HD-audio controllers appear pretty inaccurate about
672 * the update-IRQ timing. The IRQ is issued before actually the
673 * data is processed. So, we need to process it afterwords in a
674 * workqueue.
675 */
676 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
677 {
678 struct snd_pcm_substream *substream = azx_dev->core.substream;
679 int stream = substream->stream;
680 u32 wallclk;
681 unsigned int pos;
682
683 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
684 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
685 return -1; /* bogus (too early) interrupt */
686
687 if (chip->get_position[stream])
688 pos = chip->get_position[stream](chip, azx_dev);
689 else { /* use the position buffer as default */
690 pos = azx_get_pos_posbuf(chip, azx_dev);
691 if (!pos || pos == (u32)-1) {
692 dev_info(chip->card->dev,
693 "Invalid position buffer, using LPIB read method instead.\n");
694 chip->get_position[stream] = azx_get_pos_lpib;
695 if (chip->get_position[0] == azx_get_pos_lpib &&
696 chip->get_position[1] == azx_get_pos_lpib)
697 azx_bus(chip)->use_posbuf = false;
698 pos = azx_get_pos_lpib(chip, azx_dev);
699 chip->get_delay[stream] = NULL;
700 } else {
701 chip->get_position[stream] = azx_get_pos_posbuf;
702 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
703 chip->get_delay[stream] = azx_get_delay_from_lpib;
704 }
705 }
706
707 if (pos >= azx_dev->core.bufsize)
708 pos = 0;
709
710 if (WARN_ONCE(!azx_dev->core.period_bytes,
711 "hda-intel: zero azx_dev->period_bytes"))
712 return -1; /* this shouldn't happen! */
713 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
714 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
715 /* NG - it's below the first next period boundary */
716 return chip->bdl_pos_adj ? 0 : -1;
717 azx_dev->core.start_wallclk += wallclk;
718 return 1; /* OK, it's fine */
719 }
720
721 /*
722 * The work for pending PCM period updates.
723 */
724 static void azx_irq_pending_work(struct work_struct *work)
725 {
726 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
727 struct azx *chip = &hda->chip;
728 struct hdac_bus *bus = azx_bus(chip);
729 struct hdac_stream *s;
730 int pending, ok;
731
732 if (!hda->irq_pending_warned) {
733 dev_info(chip->card->dev,
734 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
735 chip->card->number);
736 hda->irq_pending_warned = 1;
737 }
738
739 for (;;) {
740 pending = 0;
741 spin_lock_irq(&bus->reg_lock);
742 list_for_each_entry(s, &bus->stream_list, list) {
743 struct azx_dev *azx_dev = stream_to_azx_dev(s);
744 if (!azx_dev->irq_pending ||
745 !s->substream ||
746 !s->running)
747 continue;
748 ok = azx_position_ok(chip, azx_dev);
749 if (ok > 0) {
750 azx_dev->irq_pending = 0;
751 spin_unlock(&bus->reg_lock);
752 snd_pcm_period_elapsed(s->substream);
753 spin_lock(&bus->reg_lock);
754 } else if (ok < 0) {
755 pending = 0; /* too early */
756 } else
757 pending++;
758 }
759 spin_unlock_irq(&bus->reg_lock);
760 if (!pending)
761 return;
762 msleep(1);
763 }
764 }
765
766 /* clear irq_pending flags and assure no on-going workq */
767 static void azx_clear_irq_pending(struct azx *chip)
768 {
769 struct hdac_bus *bus = azx_bus(chip);
770 struct hdac_stream *s;
771
772 spin_lock_irq(&bus->reg_lock);
773 list_for_each_entry(s, &bus->stream_list, list) {
774 struct azx_dev *azx_dev = stream_to_azx_dev(s);
775 azx_dev->irq_pending = 0;
776 }
777 spin_unlock_irq(&bus->reg_lock);
778 }
779
780 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
781 {
782 struct hdac_bus *bus = azx_bus(chip);
783
784 if (request_irq(chip->pci->irq, azx_interrupt,
785 chip->msi ? 0 : IRQF_SHARED,
786 chip->card->irq_descr, chip)) {
787 dev_err(chip->card->dev,
788 "unable to grab IRQ %d, disabling device\n",
789 chip->pci->irq);
790 if (do_disconnect)
791 snd_card_disconnect(chip->card);
792 return -1;
793 }
794 bus->irq = chip->pci->irq;
795 chip->card->sync_irq = bus->irq;
796 pci_intx(chip->pci, !chip->msi);
797 return 0;
798 }
799
800 /* get the current DMA position with correction on VIA chips */
801 static unsigned int azx_via_get_position(struct azx *chip,
802 struct azx_dev *azx_dev)
803 {
804 unsigned int link_pos, mini_pos, bound_pos;
805 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
806 unsigned int fifo_size;
807
808 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
809 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
810 /* Playback, no problem using link position */
811 return link_pos;
812 }
813
814 /* Capture */
815 /* For new chipset,
816 * use mod to get the DMA position just like old chipset
817 */
818 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
819 mod_dma_pos %= azx_dev->core.period_bytes;
820
821 fifo_size = azx_stream(azx_dev)->fifo_size - 1;
822
823 if (azx_dev->insufficient) {
824 /* Link position never gather than FIFO size */
825 if (link_pos <= fifo_size)
826 return 0;
827
828 azx_dev->insufficient = 0;
829 }
830
831 if (link_pos <= fifo_size)
832 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
833 else
834 mini_pos = link_pos - fifo_size;
835
836 /* Find nearest previous boudary */
837 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
838 mod_link_pos = link_pos % azx_dev->core.period_bytes;
839 if (mod_link_pos >= fifo_size)
840 bound_pos = link_pos - mod_link_pos;
841 else if (mod_dma_pos >= mod_mini_pos)
842 bound_pos = mini_pos - mod_mini_pos;
843 else {
844 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
845 if (bound_pos >= azx_dev->core.bufsize)
846 bound_pos = 0;
847 }
848
849 /* Calculate real DMA position we want */
850 return bound_pos + mod_dma_pos;
851 }
852
853 #define AMD_FIFO_SIZE 32
854
855 /* get the current DMA position with FIFO size correction */
856 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
857 {
858 struct snd_pcm_substream *substream = azx_dev->core.substream;
859 struct snd_pcm_runtime *runtime = substream->runtime;
860 unsigned int pos, delay;
861
862 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
863 if (!runtime)
864 return pos;
865
866 runtime->delay = AMD_FIFO_SIZE;
867 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
868 if (azx_dev->insufficient) {
869 if (pos < delay) {
870 delay = pos;
871 runtime->delay = bytes_to_frames(runtime, pos);
872 } else {
873 azx_dev->insufficient = 0;
874 }
875 }
876
877 /* correct the DMA position for capture stream */
878 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
879 if (pos < delay)
880 pos += azx_dev->core.bufsize;
881 pos -= delay;
882 }
883
884 return pos;
885 }
886
887 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
888 unsigned int pos)
889 {
890 struct snd_pcm_substream *substream = azx_dev->core.substream;
891
892 /* just read back the calculated value in the above */
893 return substream->runtime->delay;
894 }
895
896 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
897 struct azx_dev *azx_dev)
898 {
899 return _snd_hdac_chip_readl(azx_bus(chip),
900 AZX_REG_VS_SDXDPIB_XBASE +
901 (AZX_REG_VS_SDXDPIB_XINTERVAL *
902 azx_dev->core.index));
903 }
904
905 /* get the current DMA position with correction on SKL+ chips */
906 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
907 {
908 /* DPIB register gives a more accurate position for playback */
909 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
910 return azx_skl_get_dpib_pos(chip, azx_dev);
911
912 /* For capture, we need to read posbuf, but it requires a delay
913 * for the possible boundary overlap; the read of DPIB fetches the
914 * actual posbuf
915 */
916 udelay(20);
917 azx_skl_get_dpib_pos(chip, azx_dev);
918 return azx_get_pos_posbuf(chip, azx_dev);
919 }
920
921 #ifdef CONFIG_PM
922 static DEFINE_MUTEX(card_list_lock);
923 static LIST_HEAD(card_list);
924
925 static void azx_add_card_list(struct azx *chip)
926 {
927 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
928 mutex_lock(&card_list_lock);
929 list_add(&hda->list, &card_list);
930 mutex_unlock(&card_list_lock);
931 }
932
933 static void azx_del_card_list(struct azx *chip)
934 {
935 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
936 mutex_lock(&card_list_lock);
937 list_del_init(&hda->list);
938 mutex_unlock(&card_list_lock);
939 }
940
941 /* trigger power-save check at writing parameter */
942 static int param_set_xint(const char *val, const struct kernel_param *kp)
943 {
944 struct hda_intel *hda;
945 struct azx *chip;
946 int prev = power_save;
947 int ret = param_set_int(val, kp);
948
949 if (ret || prev == power_save)
950 return ret;
951
952 mutex_lock(&card_list_lock);
953 list_for_each_entry(hda, &card_list, list) {
954 chip = &hda->chip;
955 if (!hda->probe_continued || chip->disabled)
956 continue;
957 snd_hda_set_power_save(&chip->bus, power_save * 1000);
958 }
959 mutex_unlock(&card_list_lock);
960 return 0;
961 }
962
963 /*
964 * power management
965 */
966 static bool azx_is_pm_ready(struct snd_card *card)
967 {
968 struct azx *chip;
969 struct hda_intel *hda;
970
971 if (!card)
972 return false;
973 chip = card->private_data;
974 hda = container_of(chip, struct hda_intel, chip);
975 if (chip->disabled || hda->init_failed || !chip->running)
976 return false;
977 return true;
978 }
979
980 static void __azx_runtime_suspend(struct azx *chip)
981 {
982 azx_stop_chip(chip);
983 azx_enter_link_reset(chip);
984 azx_clear_irq_pending(chip);
985 display_power(chip, false);
986 }
987
988 static void __azx_runtime_resume(struct azx *chip, bool from_rt)
989 {
990 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
991 struct hdac_bus *bus = azx_bus(chip);
992 struct hda_codec *codec;
993 int status;
994
995 display_power(chip, true);
996 if (hda->need_i915_power)
997 snd_hdac_i915_set_bclk(bus);
998
999 /* Read STATESTS before controller reset */
1000 status = azx_readw(chip, STATESTS);
1001
1002 azx_init_pci(chip);
1003 hda_intel_init_chip(chip, true);
1004
1005 if (status && from_rt) {
1006 list_for_each_codec(codec, &chip->bus)
1007 if (status & (1 << codec->addr))
1008 schedule_delayed_work(&codec->jackpoll_work,
1009 codec->jackpoll_interval);
1010 }
1011
1012 /* power down again for link-controlled chips */
1013 if (!hda->need_i915_power)
1014 display_power(chip, false);
1015 }
1016
1017 #ifdef CONFIG_PM_SLEEP
1018 static int azx_suspend(struct device *dev)
1019 {
1020 struct snd_card *card = dev_get_drvdata(dev);
1021 struct azx *chip;
1022 struct hdac_bus *bus;
1023
1024 if (!azx_is_pm_ready(card))
1025 return 0;
1026
1027 chip = card->private_data;
1028 bus = azx_bus(chip);
1029 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1030 __azx_runtime_suspend(chip);
1031 if (bus->irq >= 0) {
1032 free_irq(bus->irq, chip);
1033 bus->irq = -1;
1034 chip->card->sync_irq = -1;
1035 }
1036
1037 if (chip->msi)
1038 pci_disable_msi(chip->pci);
1039
1040 trace_azx_suspend(chip);
1041 return 0;
1042 }
1043
1044 static int azx_resume(struct device *dev)
1045 {
1046 struct snd_card *card = dev_get_drvdata(dev);
1047 struct azx *chip;
1048
1049 if (!azx_is_pm_ready(card))
1050 return 0;
1051
1052 chip = card->private_data;
1053 if (chip->msi)
1054 if (pci_enable_msi(chip->pci) < 0)
1055 chip->msi = 0;
1056 if (azx_acquire_irq(chip, 1) < 0)
1057 return -EIO;
1058 __azx_runtime_resume(chip, false);
1059 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1060
1061 trace_azx_resume(chip);
1062 return 0;
1063 }
1064
1065 /* put codec down to D3 at hibernation for Intel SKL+;
1066 * otherwise BIOS may still access the codec and screw up the driver
1067 */
1068 static int azx_freeze_noirq(struct device *dev)
1069 {
1070 struct snd_card *card = dev_get_drvdata(dev);
1071 struct azx *chip = card->private_data;
1072 struct pci_dev *pci = to_pci_dev(dev);
1073
1074 if (chip->driver_type == AZX_DRIVER_SKL)
1075 pci_set_power_state(pci, PCI_D3hot);
1076
1077 return 0;
1078 }
1079
1080 static int azx_thaw_noirq(struct device *dev)
1081 {
1082 struct snd_card *card = dev_get_drvdata(dev);
1083 struct azx *chip = card->private_data;
1084 struct pci_dev *pci = to_pci_dev(dev);
1085
1086 if (chip->driver_type == AZX_DRIVER_SKL)
1087 pci_set_power_state(pci, PCI_D0);
1088
1089 return 0;
1090 }
1091 #endif /* CONFIG_PM_SLEEP */
1092
1093 static int azx_runtime_suspend(struct device *dev)
1094 {
1095 struct snd_card *card = dev_get_drvdata(dev);
1096 struct azx *chip;
1097
1098 if (!azx_is_pm_ready(card))
1099 return 0;
1100 chip = card->private_data;
1101 if (!azx_has_pm_runtime(chip))
1102 return 0;
1103
1104 /* enable controller wake up event */
1105 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1106 STATESTS_INT_MASK);
1107
1108 __azx_runtime_suspend(chip);
1109 trace_azx_runtime_suspend(chip);
1110 return 0;
1111 }
1112
1113 static int azx_runtime_resume(struct device *dev)
1114 {
1115 struct snd_card *card = dev_get_drvdata(dev);
1116 struct azx *chip;
1117
1118 if (!azx_is_pm_ready(card))
1119 return 0;
1120 chip = card->private_data;
1121 if (!azx_has_pm_runtime(chip))
1122 return 0;
1123 __azx_runtime_resume(chip, true);
1124
1125 /* disable controller Wake Up event*/
1126 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1127 ~STATESTS_INT_MASK);
1128
1129 trace_azx_runtime_resume(chip);
1130 return 0;
1131 }
1132
1133 static int azx_runtime_idle(struct device *dev)
1134 {
1135 struct snd_card *card = dev_get_drvdata(dev);
1136 struct azx *chip;
1137 struct hda_intel *hda;
1138
1139 if (!card)
1140 return 0;
1141
1142 chip = card->private_data;
1143 hda = container_of(chip, struct hda_intel, chip);
1144 if (chip->disabled || hda->init_failed)
1145 return 0;
1146
1147 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1148 azx_bus(chip)->codec_powered || !chip->running)
1149 return -EBUSY;
1150
1151 /* ELD notification gets broken when HD-audio bus is off */
1152 if (needs_eld_notify_link(chip))
1153 return -EBUSY;
1154
1155 return 0;
1156 }
1157
1158 static const struct dev_pm_ops azx_pm = {
1159 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1160 #ifdef CONFIG_PM_SLEEP
1161 .freeze_noirq = azx_freeze_noirq,
1162 .thaw_noirq = azx_thaw_noirq,
1163 #endif
1164 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1165 };
1166
1167 #define AZX_PM_OPS &azx_pm
1168 #else
1169 #define azx_add_card_list(chip) /* NOP */
1170 #define azx_del_card_list(chip) /* NOP */
1171 #define AZX_PM_OPS NULL
1172 #endif /* CONFIG_PM */
1173
1174
1175 static int azx_probe_continue(struct azx *chip);
1176
1177 #ifdef SUPPORT_VGA_SWITCHEROO
1178 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1179
1180 static void azx_vs_set_state(struct pci_dev *pci,
1181 enum vga_switcheroo_state state)
1182 {
1183 struct snd_card *card = pci_get_drvdata(pci);
1184 struct azx *chip = card->private_data;
1185 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1186 struct hda_codec *codec;
1187 bool disabled;
1188
1189 wait_for_completion(&hda->probe_wait);
1190 if (hda->init_failed)
1191 return;
1192
1193 disabled = (state == VGA_SWITCHEROO_OFF);
1194 if (chip->disabled == disabled)
1195 return;
1196
1197 if (!hda->probe_continued) {
1198 chip->disabled = disabled;
1199 if (!disabled) {
1200 dev_info(chip->card->dev,
1201 "Start delayed initialization\n");
1202 if (azx_probe_continue(chip) < 0) {
1203 dev_err(chip->card->dev, "initialization error\n");
1204 hda->init_failed = true;
1205 }
1206 }
1207 } else {
1208 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1209 disabled ? "Disabling" : "Enabling");
1210 if (disabled) {
1211 list_for_each_codec(codec, &chip->bus) {
1212 pm_runtime_suspend(hda_codec_dev(codec));
1213 pm_runtime_disable(hda_codec_dev(codec));
1214 }
1215 pm_runtime_suspend(card->dev);
1216 pm_runtime_disable(card->dev);
1217 /* when we get suspended by vga_switcheroo we end up in D3cold,
1218 * however we have no ACPI handle, so pci/acpi can't put us there,
1219 * put ourselves there */
1220 pci->current_state = PCI_D3cold;
1221 chip->disabled = true;
1222 if (snd_hda_lock_devices(&chip->bus))
1223 dev_warn(chip->card->dev,
1224 "Cannot lock devices!\n");
1225 } else {
1226 snd_hda_unlock_devices(&chip->bus);
1227 chip->disabled = false;
1228 pm_runtime_enable(card->dev);
1229 list_for_each_codec(codec, &chip->bus) {
1230 pm_runtime_enable(hda_codec_dev(codec));
1231 pm_runtime_resume(hda_codec_dev(codec));
1232 }
1233 }
1234 }
1235 }
1236
1237 static bool azx_vs_can_switch(struct pci_dev *pci)
1238 {
1239 struct snd_card *card = pci_get_drvdata(pci);
1240 struct azx *chip = card->private_data;
1241 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1242
1243 wait_for_completion(&hda->probe_wait);
1244 if (hda->init_failed)
1245 return false;
1246 if (chip->disabled || !hda->probe_continued)
1247 return true;
1248 if (snd_hda_lock_devices(&chip->bus))
1249 return false;
1250 snd_hda_unlock_devices(&chip->bus);
1251 return true;
1252 }
1253
1254 /*
1255 * The discrete GPU cannot power down unless the HDA controller runtime
1256 * suspends, so activate runtime PM on codecs even if power_save == 0.
1257 */
1258 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1259 {
1260 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1261 struct hda_codec *codec;
1262
1263 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1264 list_for_each_codec(codec, &chip->bus)
1265 codec->auto_runtime_pm = 1;
1266 /* reset the power save setup */
1267 if (chip->running)
1268 set_default_power_save(chip);
1269 }
1270 }
1271
1272 static void azx_vs_gpu_bound(struct pci_dev *pci,
1273 enum vga_switcheroo_client_id client_id)
1274 {
1275 struct snd_card *card = pci_get_drvdata(pci);
1276 struct azx *chip = card->private_data;
1277
1278 if (client_id == VGA_SWITCHEROO_DIS)
1279 chip->bus.keep_power = 0;
1280 setup_vga_switcheroo_runtime_pm(chip);
1281 }
1282
1283 static void init_vga_switcheroo(struct azx *chip)
1284 {
1285 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1286 struct pci_dev *p = get_bound_vga(chip->pci);
1287 struct pci_dev *parent;
1288 if (p) {
1289 dev_info(chip->card->dev,
1290 "Handle vga_switcheroo audio client\n");
1291 hda->use_vga_switcheroo = 1;
1292
1293 /* cleared in either gpu_bound op or codec probe, or when its
1294 * upstream port has _PR3 (i.e. dGPU).
1295 */
1296 parent = pci_upstream_bridge(p);
1297 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1298 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1299 pci_dev_put(p);
1300 }
1301 }
1302
1303 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1304 .set_gpu_state = azx_vs_set_state,
1305 .can_switch = azx_vs_can_switch,
1306 .gpu_bound = azx_vs_gpu_bound,
1307 };
1308
1309 static int register_vga_switcheroo(struct azx *chip)
1310 {
1311 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1312 struct pci_dev *p;
1313 int err;
1314
1315 if (!hda->use_vga_switcheroo)
1316 return 0;
1317
1318 p = get_bound_vga(chip->pci);
1319 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1320 pci_dev_put(p);
1321
1322 if (err < 0)
1323 return err;
1324 hda->vga_switcheroo_registered = 1;
1325
1326 return 0;
1327 }
1328 #else
1329 #define init_vga_switcheroo(chip) /* NOP */
1330 #define register_vga_switcheroo(chip) 0
1331 #define check_hdmi_disabled(pci) false
1332 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
1333 #endif /* SUPPORT_VGA_SWITCHER */
1334
1335 /*
1336 * destructor
1337 */
1338 static int azx_free(struct azx *chip)
1339 {
1340 struct pci_dev *pci = chip->pci;
1341 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1342 struct hdac_bus *bus = azx_bus(chip);
1343
1344 if (azx_has_pm_runtime(chip) && chip->running)
1345 pm_runtime_get_noresume(&pci->dev);
1346 chip->running = 0;
1347
1348 azx_del_card_list(chip);
1349
1350 hda->init_failed = 1; /* to be sure */
1351 complete_all(&hda->probe_wait);
1352
1353 if (use_vga_switcheroo(hda)) {
1354 if (chip->disabled && hda->probe_continued)
1355 snd_hda_unlock_devices(&chip->bus);
1356 if (hda->vga_switcheroo_registered)
1357 vga_switcheroo_unregister_client(chip->pci);
1358 }
1359
1360 if (bus->chip_init) {
1361 azx_clear_irq_pending(chip);
1362 azx_stop_all_streams(chip);
1363 azx_stop_chip(chip);
1364 }
1365
1366 if (bus->irq >= 0)
1367 free_irq(bus->irq, (void*)chip);
1368 if (chip->msi)
1369 pci_disable_msi(chip->pci);
1370 iounmap(bus->remap_addr);
1371
1372 azx_free_stream_pages(chip);
1373 azx_free_streams(chip);
1374 snd_hdac_bus_exit(bus);
1375
1376 if (chip->region_requested)
1377 pci_release_regions(chip->pci);
1378
1379 pci_disable_device(chip->pci);
1380 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1381 release_firmware(chip->fw);
1382 #endif
1383 display_power(chip, false);
1384
1385 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1386 snd_hdac_i915_exit(bus);
1387 kfree(hda);
1388
1389 return 0;
1390 }
1391
1392 static int azx_dev_disconnect(struct snd_device *device)
1393 {
1394 struct azx *chip = device->device_data;
1395 struct hdac_bus *bus = azx_bus(chip);
1396
1397 chip->bus.shutdown = 1;
1398 cancel_work_sync(&bus->unsol_work);
1399
1400 return 0;
1401 }
1402
1403 static int azx_dev_free(struct snd_device *device)
1404 {
1405 return azx_free(device->device_data);
1406 }
1407
1408 #ifdef SUPPORT_VGA_SWITCHEROO
1409 #ifdef CONFIG_ACPI
1410 /* ATPX is in the integrated GPU's namespace */
1411 static bool atpx_present(void)
1412 {
1413 struct pci_dev *pdev = NULL;
1414 acpi_handle dhandle, atpx_handle;
1415 acpi_status status;
1416
1417 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1418 dhandle = ACPI_HANDLE(&pdev->dev);
1419 if (dhandle) {
1420 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1421 if (!ACPI_FAILURE(status)) {
1422 pci_dev_put(pdev);
1423 return true;
1424 }
1425 }
1426 }
1427 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
1428 dhandle = ACPI_HANDLE(&pdev->dev);
1429 if (dhandle) {
1430 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1431 if (!ACPI_FAILURE(status)) {
1432 pci_dev_put(pdev);
1433 return true;
1434 }
1435 }
1436 }
1437 return false;
1438 }
1439 #else
1440 static bool atpx_present(void)
1441 {
1442 return false;
1443 }
1444 #endif
1445
1446 /*
1447 * Check of disabled HDMI controller by vga_switcheroo
1448 */
1449 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1450 {
1451 struct pci_dev *p;
1452
1453 /* check only discrete GPU */
1454 switch (pci->vendor) {
1455 case PCI_VENDOR_ID_ATI:
1456 case PCI_VENDOR_ID_AMD:
1457 if (pci->devfn == 1) {
1458 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1459 pci->bus->number, 0);
1460 if (p) {
1461 /* ATPX is in the integrated GPU's ACPI namespace
1462 * rather than the dGPU's namespace. However,
1463 * the dGPU is the one who is involved in
1464 * vgaswitcheroo.
1465 */
1466 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1467 atpx_present())
1468 return p;
1469 pci_dev_put(p);
1470 }
1471 }
1472 break;
1473 case PCI_VENDOR_ID_NVIDIA:
1474 if (pci->devfn == 1) {
1475 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1476 pci->bus->number, 0);
1477 if (p) {
1478 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1479 return p;
1480 pci_dev_put(p);
1481 }
1482 }
1483 break;
1484 }
1485 return NULL;
1486 }
1487
1488 static bool check_hdmi_disabled(struct pci_dev *pci)
1489 {
1490 bool vga_inactive = false;
1491 struct pci_dev *p = get_bound_vga(pci);
1492
1493 if (p) {
1494 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1495 vga_inactive = true;
1496 pci_dev_put(p);
1497 }
1498 return vga_inactive;
1499 }
1500 #endif /* SUPPORT_VGA_SWITCHEROO */
1501
1502 /*
1503 * white/black-listing for position_fix
1504 */
1505 static const struct snd_pci_quirk position_fix_list[] = {
1506 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1507 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1508 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1509 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1510 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1511 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1512 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1513 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1514 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1515 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1516 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1517 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1518 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1519 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1520 {}
1521 };
1522
1523 static int check_position_fix(struct azx *chip, int fix)
1524 {
1525 const struct snd_pci_quirk *q;
1526
1527 switch (fix) {
1528 case POS_FIX_AUTO:
1529 case POS_FIX_LPIB:
1530 case POS_FIX_POSBUF:
1531 case POS_FIX_VIACOMBO:
1532 case POS_FIX_COMBO:
1533 case POS_FIX_SKL:
1534 case POS_FIX_FIFO:
1535 return fix;
1536 }
1537
1538 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1539 if (q) {
1540 dev_info(chip->card->dev,
1541 "position_fix set to %d for device %04x:%04x\n",
1542 q->value, q->subvendor, q->subdevice);
1543 return q->value;
1544 }
1545
1546 /* Check VIA/ATI HD Audio Controller exist */
1547 if (chip->driver_type == AZX_DRIVER_VIA) {
1548 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1549 return POS_FIX_VIACOMBO;
1550 }
1551 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1552 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1553 return POS_FIX_FIFO;
1554 }
1555 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1556 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1557 return POS_FIX_LPIB;
1558 }
1559 if (chip->driver_type == AZX_DRIVER_SKL) {
1560 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1561 return POS_FIX_SKL;
1562 }
1563 return POS_FIX_AUTO;
1564 }
1565
1566 static void assign_position_fix(struct azx *chip, int fix)
1567 {
1568 static const azx_get_pos_callback_t callbacks[] = {
1569 [POS_FIX_AUTO] = NULL,
1570 [POS_FIX_LPIB] = azx_get_pos_lpib,
1571 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1572 [POS_FIX_VIACOMBO] = azx_via_get_position,
1573 [POS_FIX_COMBO] = azx_get_pos_lpib,
1574 [POS_FIX_SKL] = azx_get_pos_skl,
1575 [POS_FIX_FIFO] = azx_get_pos_fifo,
1576 };
1577
1578 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1579
1580 /* combo mode uses LPIB only for playback */
1581 if (fix == POS_FIX_COMBO)
1582 chip->get_position[1] = NULL;
1583
1584 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1585 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1586 chip->get_delay[0] = chip->get_delay[1] =
1587 azx_get_delay_from_lpib;
1588 }
1589
1590 if (fix == POS_FIX_FIFO)
1591 chip->get_delay[0] = chip->get_delay[1] =
1592 azx_get_delay_from_fifo;
1593 }
1594
1595 /*
1596 * black-lists for probe_mask
1597 */
1598 static const struct snd_pci_quirk probe_mask_list[] = {
1599 /* Thinkpad often breaks the controller communication when accessing
1600 * to the non-working (or non-existing) modem codec slot.
1601 */
1602 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1603 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1604 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1605 /* broken BIOS */
1606 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1607 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1608 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1609 /* forced codec slots */
1610 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1611 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1612 /* WinFast VP200 H (Teradici) user reported broken communication */
1613 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1614 {}
1615 };
1616
1617 #define AZX_FORCE_CODEC_MASK 0x100
1618
1619 static void check_probe_mask(struct azx *chip, int dev)
1620 {
1621 const struct snd_pci_quirk *q;
1622
1623 chip->codec_probe_mask = probe_mask[dev];
1624 if (chip->codec_probe_mask == -1) {
1625 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1626 if (q) {
1627 dev_info(chip->card->dev,
1628 "probe_mask set to 0x%x for device %04x:%04x\n",
1629 q->value, q->subvendor, q->subdevice);
1630 chip->codec_probe_mask = q->value;
1631 }
1632 }
1633
1634 /* check forced option */
1635 if (chip->codec_probe_mask != -1 &&
1636 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1637 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1638 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1639 (int)azx_bus(chip)->codec_mask);
1640 }
1641 }
1642
1643 /*
1644 * white/black-list for enable_msi
1645 */
1646 static const struct snd_pci_quirk msi_black_list[] = {
1647 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1648 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1649 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1650 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1651 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1652 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1653 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1654 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1655 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1656 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1657 {}
1658 };
1659
1660 static void check_msi(struct azx *chip)
1661 {
1662 const struct snd_pci_quirk *q;
1663
1664 if (enable_msi >= 0) {
1665 chip->msi = !!enable_msi;
1666 return;
1667 }
1668 chip->msi = 1; /* enable MSI as default */
1669 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1670 if (q) {
1671 dev_info(chip->card->dev,
1672 "msi for device %04x:%04x set to %d\n",
1673 q->subvendor, q->subdevice, q->value);
1674 chip->msi = q->value;
1675 return;
1676 }
1677
1678 /* NVidia chipsets seem to cause troubles with MSI */
1679 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1680 dev_info(chip->card->dev, "Disabling MSI\n");
1681 chip->msi = 0;
1682 }
1683 }
1684
1685 /* check the snoop mode availability */
1686 static void azx_check_snoop_available(struct azx *chip)
1687 {
1688 int snoop = hda_snoop;
1689
1690 if (snoop >= 0) {
1691 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1692 snoop ? "snoop" : "non-snoop");
1693 chip->snoop = snoop;
1694 chip->uc_buffer = !snoop;
1695 return;
1696 }
1697
1698 snoop = true;
1699 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1700 chip->driver_type == AZX_DRIVER_VIA) {
1701 /* force to non-snoop mode for a new VIA controller
1702 * when BIOS is set
1703 */
1704 u8 val;
1705 pci_read_config_byte(chip->pci, 0x42, &val);
1706 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1707 chip->pci->revision == 0x20))
1708 snoop = false;
1709 }
1710
1711 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1712 snoop = false;
1713
1714 chip->snoop = snoop;
1715 if (!snoop) {
1716 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1717 /* C-Media requires non-cached pages only for CORB/RIRB */
1718 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1719 chip->uc_buffer = true;
1720 }
1721 }
1722
1723 static void azx_probe_work(struct work_struct *work)
1724 {
1725 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1726 azx_probe_continue(&hda->chip);
1727 }
1728
1729 static int default_bdl_pos_adj(struct azx *chip)
1730 {
1731 /* some exceptions: Atoms seem problematic with value 1 */
1732 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1733 switch (chip->pci->device) {
1734 case 0x0f04: /* Baytrail */
1735 case 0x2284: /* Braswell */
1736 return 32;
1737 }
1738 }
1739
1740 switch (chip->driver_type) {
1741 case AZX_DRIVER_ICH:
1742 case AZX_DRIVER_PCH:
1743 return 1;
1744 default:
1745 return 32;
1746 }
1747 }
1748
1749 /*
1750 * constructor
1751 */
1752 static const struct hda_controller_ops pci_hda_ops;
1753
1754 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1755 int dev, unsigned int driver_caps,
1756 struct azx **rchip)
1757 {
1758 static const struct snd_device_ops ops = {
1759 .dev_disconnect = azx_dev_disconnect,
1760 .dev_free = azx_dev_free,
1761 };
1762 struct hda_intel *hda;
1763 struct azx *chip;
1764 int err;
1765
1766 *rchip = NULL;
1767
1768 err = pci_enable_device(pci);
1769 if (err < 0)
1770 return err;
1771
1772 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1773 if (!hda) {
1774 pci_disable_device(pci);
1775 return -ENOMEM;
1776 }
1777
1778 chip = &hda->chip;
1779 mutex_init(&chip->open_mutex);
1780 chip->card = card;
1781 chip->pci = pci;
1782 chip->ops = &pci_hda_ops;
1783 chip->driver_caps = driver_caps;
1784 chip->driver_type = driver_caps & 0xff;
1785 check_msi(chip);
1786 chip->dev_index = dev;
1787 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1788 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1789 INIT_LIST_HEAD(&chip->pcm_list);
1790 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1791 INIT_LIST_HEAD(&hda->list);
1792 init_vga_switcheroo(chip);
1793 init_completion(&hda->probe_wait);
1794
1795 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1796
1797 check_probe_mask(chip, dev);
1798
1799 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1800 chip->fallback_to_single_cmd = 1;
1801 else /* explicitly set to single_cmd or not */
1802 chip->single_cmd = single_cmd;
1803
1804 azx_check_snoop_available(chip);
1805
1806 if (bdl_pos_adj[dev] < 0)
1807 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1808 else
1809 chip->bdl_pos_adj = bdl_pos_adj[dev];
1810
1811 err = azx_bus_init(chip, model[dev]);
1812 if (err < 0) {
1813 kfree(hda);
1814 pci_disable_device(pci);
1815 return err;
1816 }
1817
1818 /* use the non-cached pages in non-snoop mode */
1819 if (!azx_snoop(chip))
1820 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1821
1822 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1823 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1824 chip->bus.core.needs_damn_long_delay = 1;
1825 }
1826
1827 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1828 if (err < 0) {
1829 dev_err(card->dev, "Error creating device [card]!\n");
1830 azx_free(chip);
1831 return err;
1832 }
1833
1834 /* continue probing in work context as may trigger request module */
1835 INIT_WORK(&hda->probe_work, azx_probe_work);
1836
1837 *rchip = chip;
1838
1839 return 0;
1840 }
1841
1842 static int azx_first_init(struct azx *chip)
1843 {
1844 int dev = chip->dev_index;
1845 struct pci_dev *pci = chip->pci;
1846 struct snd_card *card = chip->card;
1847 struct hdac_bus *bus = azx_bus(chip);
1848 int err;
1849 unsigned short gcap;
1850 unsigned int dma_bits = 64;
1851
1852 #if BITS_PER_LONG != 64
1853 /* Fix up base address on ULI M5461 */
1854 if (chip->driver_type == AZX_DRIVER_ULI) {
1855 u16 tmp3;
1856 pci_read_config_word(pci, 0x40, &tmp3);
1857 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1858 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1859 }
1860 #endif
1861
1862 err = pci_request_regions(pci, "ICH HD audio");
1863 if (err < 0)
1864 return err;
1865 chip->region_requested = 1;
1866
1867 bus->addr = pci_resource_start(pci, 0);
1868 bus->remap_addr = pci_ioremap_bar(pci, 0);
1869 if (bus->remap_addr == NULL) {
1870 dev_err(card->dev, "ioremap error\n");
1871 return -ENXIO;
1872 }
1873
1874 if (chip->driver_type == AZX_DRIVER_SKL)
1875 snd_hdac_bus_parse_capabilities(bus);
1876
1877 /*
1878 * Some Intel CPUs has always running timer (ART) feature and
1879 * controller may have Global time sync reporting capability, so
1880 * check both of these before declaring synchronized time reporting
1881 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1882 */
1883 chip->gts_present = false;
1884
1885 #ifdef CONFIG_X86
1886 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1887 chip->gts_present = true;
1888 #endif
1889
1890 if (chip->msi) {
1891 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1892 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1893 pci->no_64bit_msi = true;
1894 }
1895 if (pci_enable_msi(pci) < 0)
1896 chip->msi = 0;
1897 }
1898
1899 pci_set_master(pci);
1900
1901 gcap = azx_readw(chip, GCAP);
1902 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1903
1904 /* AMD devices support 40 or 48bit DMA, take the safe one */
1905 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1906 dma_bits = 40;
1907
1908 /* disable SB600 64bit support for safety */
1909 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1910 struct pci_dev *p_smbus;
1911 dma_bits = 40;
1912 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1913 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1914 NULL);
1915 if (p_smbus) {
1916 if (p_smbus->revision < 0x30)
1917 gcap &= ~AZX_GCAP_64OK;
1918 pci_dev_put(p_smbus);
1919 }
1920 }
1921
1922 /* NVidia hardware normally only supports up to 40 bits of DMA */
1923 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1924 dma_bits = 40;
1925
1926 /* disable 64bit DMA address on some devices */
1927 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1928 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1929 gcap &= ~AZX_GCAP_64OK;
1930 }
1931
1932 /* disable buffer size rounding to 128-byte multiples if supported */
1933 if (align_buffer_size >= 0)
1934 chip->align_buffer_size = !!align_buffer_size;
1935 else {
1936 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1937 chip->align_buffer_size = 0;
1938 else
1939 chip->align_buffer_size = 1;
1940 }
1941
1942 /* allow 64bit DMA address if supported by H/W */
1943 if (!(gcap & AZX_GCAP_64OK))
1944 dma_bits = 32;
1945 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1946 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1947 } else {
1948 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1949 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1950 }
1951
1952 /* read number of streams from GCAP register instead of using
1953 * hardcoded value
1954 */
1955 chip->capture_streams = (gcap >> 8) & 0x0f;
1956 chip->playback_streams = (gcap >> 12) & 0x0f;
1957 if (!chip->playback_streams && !chip->capture_streams) {
1958 /* gcap didn't give any info, switching to old method */
1959
1960 switch (chip->driver_type) {
1961 case AZX_DRIVER_ULI:
1962 chip->playback_streams = ULI_NUM_PLAYBACK;
1963 chip->capture_streams = ULI_NUM_CAPTURE;
1964 break;
1965 case AZX_DRIVER_ATIHDMI:
1966 case AZX_DRIVER_ATIHDMI_NS:
1967 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1968 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1969 break;
1970 case AZX_DRIVER_GENERIC:
1971 default:
1972 chip->playback_streams = ICH6_NUM_PLAYBACK;
1973 chip->capture_streams = ICH6_NUM_CAPTURE;
1974 break;
1975 }
1976 }
1977 chip->capture_index_offset = 0;
1978 chip->playback_index_offset = chip->capture_streams;
1979 chip->num_streams = chip->playback_streams + chip->capture_streams;
1980
1981 /* sanity check for the SDxCTL.STRM field overflow */
1982 if (chip->num_streams > 15 &&
1983 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1984 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1985 "forcing separate stream tags", chip->num_streams);
1986 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1987 }
1988
1989 /* initialize streams */
1990 err = azx_init_streams(chip);
1991 if (err < 0)
1992 return err;
1993
1994 err = azx_alloc_stream_pages(chip);
1995 if (err < 0)
1996 return err;
1997
1998 /* initialize chip */
1999 azx_init_pci(chip);
2000
2001 snd_hdac_i915_set_bclk(bus);
2002
2003 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2004
2005 /* codec detection */
2006 if (!azx_bus(chip)->codec_mask) {
2007 dev_err(card->dev, "no codecs found!\n");
2008 return -ENODEV;
2009 }
2010
2011 if (azx_acquire_irq(chip, 0) < 0)
2012 return -EBUSY;
2013
2014 strcpy(card->driver, "HDA-Intel");
2015 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2016 sizeof(card->shortname));
2017 snprintf(card->longname, sizeof(card->longname),
2018 "%s at 0x%lx irq %i",
2019 card->shortname, bus->addr, bus->irq);
2020
2021 return 0;
2022 }
2023
2024 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2025 /* callback from request_firmware_nowait() */
2026 static void azx_firmware_cb(const struct firmware *fw, void *context)
2027 {
2028 struct snd_card *card = context;
2029 struct azx *chip = card->private_data;
2030 struct pci_dev *pci = chip->pci;
2031
2032 if (!fw) {
2033 dev_err(card->dev, "Cannot load firmware, aborting\n");
2034 goto error;
2035 }
2036
2037 chip->fw = fw;
2038 if (!chip->disabled) {
2039 /* continue probing */
2040 if (azx_probe_continue(chip))
2041 goto error;
2042 }
2043 return; /* OK */
2044
2045 error:
2046 snd_card_free(card);
2047 pci_set_drvdata(pci, NULL);
2048 }
2049 #endif
2050
2051 static int disable_msi_reset_irq(struct azx *chip)
2052 {
2053 struct hdac_bus *bus = azx_bus(chip);
2054 int err;
2055
2056 free_irq(bus->irq, chip);
2057 bus->irq = -1;
2058 chip->card->sync_irq = -1;
2059 pci_disable_msi(chip->pci);
2060 chip->msi = 0;
2061 err = azx_acquire_irq(chip, 1);
2062 if (err < 0)
2063 return err;
2064
2065 return 0;
2066 }
2067
2068 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2069 struct vm_area_struct *area)
2070 {
2071 #ifdef CONFIG_X86
2072 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2073 struct azx *chip = apcm->chip;
2074 if (chip->uc_buffer)
2075 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2076 #endif
2077 }
2078
2079 static const struct hda_controller_ops pci_hda_ops = {
2080 .disable_msi_reset_irq = disable_msi_reset_irq,
2081 .pcm_mmap_prepare = pcm_mmap_prepare,
2082 .position_check = azx_position_check,
2083 };
2084
2085 static int azx_probe(struct pci_dev *pci,
2086 const struct pci_device_id *pci_id)
2087 {
2088 static int dev;
2089 struct snd_card *card;
2090 struct hda_intel *hda;
2091 struct azx *chip;
2092 bool schedule_probe;
2093 int err;
2094
2095 if (dev >= SNDRV_CARDS)
2096 return -ENODEV;
2097 if (!enable[dev]) {
2098 dev++;
2099 return -ENOENT;
2100 }
2101
2102 /*
2103 * stop probe if another Intel's DSP driver should be activated
2104 */
2105 if (dmic_detect) {
2106 err = snd_intel_dsp_driver_probe(pci);
2107 if (err != SND_INTEL_DSP_DRIVER_ANY &&
2108 err != SND_INTEL_DSP_DRIVER_LEGACY)
2109 return -ENODEV;
2110 } else {
2111 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2112 }
2113
2114 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2115 0, &card);
2116 if (err < 0) {
2117 dev_err(&pci->dev, "Error creating card!\n");
2118 return err;
2119 }
2120
2121 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2122 if (err < 0)
2123 goto out_free;
2124 card->private_data = chip;
2125 hda = container_of(chip, struct hda_intel, chip);
2126
2127 pci_set_drvdata(pci, card);
2128
2129 err = register_vga_switcheroo(chip);
2130 if (err < 0) {
2131 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2132 goto out_free;
2133 }
2134
2135 if (check_hdmi_disabled(pci)) {
2136 dev_info(card->dev, "VGA controller is disabled\n");
2137 dev_info(card->dev, "Delaying initialization\n");
2138 chip->disabled = true;
2139 }
2140
2141 schedule_probe = !chip->disabled;
2142
2143 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2144 if (patch[dev] && *patch[dev]) {
2145 dev_info(card->dev, "Applying patch firmware '%s'\n",
2146 patch[dev]);
2147 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2148 &pci->dev, GFP_KERNEL, card,
2149 azx_firmware_cb);
2150 if (err < 0)
2151 goto out_free;
2152 schedule_probe = false; /* continued in azx_firmware_cb() */
2153 }
2154 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2155
2156 #ifndef CONFIG_SND_HDA_I915
2157 if (CONTROLLER_IN_GPU(pci))
2158 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2159 #endif
2160
2161 if (schedule_probe)
2162 schedule_work(&hda->probe_work);
2163
2164 dev++;
2165 if (chip->disabled)
2166 complete_all(&hda->probe_wait);
2167 return 0;
2168
2169 out_free:
2170 snd_card_free(card);
2171 return err;
2172 }
2173
2174 #ifdef CONFIG_PM
2175 /* On some boards setting power_save to a non 0 value leads to clicking /
2176 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2177 * figure out how to avoid these sounds, but that is not always feasible.
2178 * So we keep a list of devices where we disable powersaving as its known
2179 * to causes problems on these devices.
2180 */
2181 static const struct snd_pci_quirk power_save_blacklist[] = {
2182 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2183 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2184 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2185 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2186 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2187 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2188 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2189 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2190 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2191 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2192 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2193 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2194 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2195 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2196 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2197 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2198 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2199 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2200 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2201 /* https://bugs.launchpad.net/bugs/1821663 */
2202 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2203 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2204 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2205 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2206 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2207 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2208 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2209 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2210 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2211 /* https://bugs.launchpad.net/bugs/1821663 */
2212 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2213 {}
2214 };
2215 #endif /* CONFIG_PM */
2216
2217 static void set_default_power_save(struct azx *chip)
2218 {
2219 int val = power_save;
2220
2221 #ifdef CONFIG_PM
2222 if (pm_blacklist) {
2223 const struct snd_pci_quirk *q;
2224
2225 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2226 if (q && val) {
2227 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2228 q->subvendor, q->subdevice);
2229 val = 0;
2230 }
2231 }
2232 #endif /* CONFIG_PM */
2233 snd_hda_set_power_save(&chip->bus, val * 1000);
2234 }
2235
2236 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2237 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2238 [AZX_DRIVER_NVIDIA] = 8,
2239 [AZX_DRIVER_TERA] = 1,
2240 };
2241
2242 static int azx_probe_continue(struct azx *chip)
2243 {
2244 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2245 struct hdac_bus *bus = azx_bus(chip);
2246 struct pci_dev *pci = chip->pci;
2247 int dev = chip->dev_index;
2248 int err;
2249
2250 to_hda_bus(bus)->bus_probing = 1;
2251 hda->probe_continued = 1;
2252
2253 /* bind with i915 if needed */
2254 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2255 err = snd_hdac_i915_init(bus);
2256 if (err < 0) {
2257 /* if the controller is bound only with HDMI/DP
2258 * (for HSW and BDW), we need to abort the probe;
2259 * for other chips, still continue probing as other
2260 * codecs can be on the same link.
2261 */
2262 if (CONTROLLER_IN_GPU(pci)) {
2263 dev_err(chip->card->dev,
2264 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2265 goto out_free;
2266 } else {
2267 /* don't bother any longer */
2268 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2269 }
2270 }
2271
2272 /* HSW/BDW controllers need this power */
2273 if (CONTROLLER_IN_GPU(pci))
2274 hda->need_i915_power = 1;
2275 }
2276
2277 /* Request display power well for the HDA controller or codec. For
2278 * Haswell/Broadwell, both the display HDA controller and codec need
2279 * this power. For other platforms, like Baytrail/Braswell, only the
2280 * display codec needs the power and it can be released after probe.
2281 */
2282 display_power(chip, true);
2283
2284 err = azx_first_init(chip);
2285 if (err < 0)
2286 goto out_free;
2287
2288 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2289 chip->beep_mode = beep_mode[dev];
2290 #endif
2291
2292 /* create codec instances */
2293 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2294 if (err < 0)
2295 goto out_free;
2296
2297 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2298 if (chip->fw) {
2299 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2300 chip->fw->data);
2301 if (err < 0)
2302 goto out_free;
2303 #ifndef CONFIG_PM
2304 release_firmware(chip->fw); /* no longer needed */
2305 chip->fw = NULL;
2306 #endif
2307 }
2308 #endif
2309 if ((probe_only[dev] & 1) == 0) {
2310 err = azx_codec_configure(chip);
2311 if (err < 0)
2312 goto out_free;
2313 }
2314
2315 err = snd_card_register(chip->card);
2316 if (err < 0)
2317 goto out_free;
2318
2319 setup_vga_switcheroo_runtime_pm(chip);
2320
2321 chip->running = 1;
2322 azx_add_card_list(chip);
2323
2324 set_default_power_save(chip);
2325
2326 if (azx_has_pm_runtime(chip))
2327 pm_runtime_put_autosuspend(&pci->dev);
2328
2329 out_free:
2330 if (err < 0 || !hda->need_i915_power)
2331 display_power(chip, false);
2332 if (err < 0)
2333 hda->init_failed = 1;
2334 complete_all(&hda->probe_wait);
2335 to_hda_bus(bus)->bus_probing = 0;
2336 return err;
2337 }
2338
2339 static void azx_remove(struct pci_dev *pci)
2340 {
2341 struct snd_card *card = pci_get_drvdata(pci);
2342 struct azx *chip;
2343 struct hda_intel *hda;
2344
2345 if (card) {
2346 /* cancel the pending probing work */
2347 chip = card->private_data;
2348 hda = container_of(chip, struct hda_intel, chip);
2349 /* FIXME: below is an ugly workaround.
2350 * Both device_release_driver() and driver_probe_device()
2351 * take *both* the device's and its parent's lock before
2352 * calling the remove() and probe() callbacks. The codec
2353 * probe takes the locks of both the codec itself and its
2354 * parent, i.e. the PCI controller dev. Meanwhile, when
2355 * the PCI controller is unbound, it takes its lock, too
2356 * ==> ouch, a deadlock!
2357 * As a workaround, we unlock temporarily here the controller
2358 * device during cancel_work_sync() call.
2359 */
2360 device_unlock(&pci->dev);
2361 cancel_work_sync(&hda->probe_work);
2362 device_lock(&pci->dev);
2363
2364 snd_card_free(card);
2365 }
2366 }
2367
2368 static void azx_shutdown(struct pci_dev *pci)
2369 {
2370 struct snd_card *card = pci_get_drvdata(pci);
2371 struct azx *chip;
2372
2373 if (!card)
2374 return;
2375 chip = card->private_data;
2376 if (chip && chip->running)
2377 azx_stop_chip(chip);
2378 }
2379
2380 /* PCI IDs */
2381 static const struct pci_device_id azx_ids[] = {
2382 /* CPT */
2383 { PCI_DEVICE(0x8086, 0x1c20),
2384 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2385 /* PBG */
2386 { PCI_DEVICE(0x8086, 0x1d20),
2387 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2388 /* Panther Point */
2389 { PCI_DEVICE(0x8086, 0x1e20),
2390 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2391 /* Lynx Point */
2392 { PCI_DEVICE(0x8086, 0x8c20),
2393 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2394 /* 9 Series */
2395 { PCI_DEVICE(0x8086, 0x8ca0),
2396 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2397 /* Wellsburg */
2398 { PCI_DEVICE(0x8086, 0x8d20),
2399 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2400 { PCI_DEVICE(0x8086, 0x8d21),
2401 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2402 /* Lewisburg */
2403 { PCI_DEVICE(0x8086, 0xa1f0),
2404 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2405 { PCI_DEVICE(0x8086, 0xa270),
2406 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2407 /* Lynx Point-LP */
2408 { PCI_DEVICE(0x8086, 0x9c20),
2409 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2410 /* Lynx Point-LP */
2411 { PCI_DEVICE(0x8086, 0x9c21),
2412 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2413 /* Wildcat Point-LP */
2414 { PCI_DEVICE(0x8086, 0x9ca0),
2415 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2416 /* Sunrise Point */
2417 { PCI_DEVICE(0x8086, 0xa170),
2418 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2419 /* Sunrise Point-LP */
2420 { PCI_DEVICE(0x8086, 0x9d70),
2421 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2422 /* Kabylake */
2423 { PCI_DEVICE(0x8086, 0xa171),
2424 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2425 /* Kabylake-LP */
2426 { PCI_DEVICE(0x8086, 0x9d71),
2427 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2428 /* Kabylake-H */
2429 { PCI_DEVICE(0x8086, 0xa2f0),
2430 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2431 /* Coffelake */
2432 { PCI_DEVICE(0x8086, 0xa348),
2433 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2434 /* Cannonlake */
2435 { PCI_DEVICE(0x8086, 0x9dc8),
2436 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2437 /* CometLake-LP */
2438 { PCI_DEVICE(0x8086, 0x02C8),
2439 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2440 /* CometLake-H */
2441 { PCI_DEVICE(0x8086, 0x06C8),
2442 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2443 /* CometLake-S */
2444 { PCI_DEVICE(0x8086, 0xa3f0),
2445 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2446 /* Icelake */
2447 { PCI_DEVICE(0x8086, 0x34c8),
2448 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2449 /* Jasperlake */
2450 { PCI_DEVICE(0x8086, 0x38c8),
2451 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2452 /* Tigerlake */
2453 { PCI_DEVICE(0x8086, 0xa0c8),
2454 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2455 /* Elkhart Lake */
2456 { PCI_DEVICE(0x8086, 0x4b55),
2457 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2458 /* Broxton-P(Apollolake) */
2459 { PCI_DEVICE(0x8086, 0x5a98),
2460 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2461 /* Broxton-T */
2462 { PCI_DEVICE(0x8086, 0x1a98),
2463 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2464 /* Gemini-Lake */
2465 { PCI_DEVICE(0x8086, 0x3198),
2466 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2467 /* Haswell */
2468 { PCI_DEVICE(0x8086, 0x0a0c),
2469 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2470 { PCI_DEVICE(0x8086, 0x0c0c),
2471 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2472 { PCI_DEVICE(0x8086, 0x0d0c),
2473 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2474 /* Broadwell */
2475 { PCI_DEVICE(0x8086, 0x160c),
2476 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2477 /* 5 Series/3400 */
2478 { PCI_DEVICE(0x8086, 0x3b56),
2479 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2480 /* Poulsbo */
2481 { PCI_DEVICE(0x8086, 0x811b),
2482 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2483 /* Oaktrail */
2484 { PCI_DEVICE(0x8086, 0x080a),
2485 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2486 /* BayTrail */
2487 { PCI_DEVICE(0x8086, 0x0f04),
2488 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2489 /* Braswell */
2490 { PCI_DEVICE(0x8086, 0x2284),
2491 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2492 /* ICH6 */
2493 { PCI_DEVICE(0x8086, 0x2668),
2494 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2495 /* ICH7 */
2496 { PCI_DEVICE(0x8086, 0x27d8),
2497 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2498 /* ESB2 */
2499 { PCI_DEVICE(0x8086, 0x269a),
2500 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2501 /* ICH8 */
2502 { PCI_DEVICE(0x8086, 0x284b),
2503 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2504 /* ICH9 */
2505 { PCI_DEVICE(0x8086, 0x293e),
2506 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2507 /* ICH9 */
2508 { PCI_DEVICE(0x8086, 0x293f),
2509 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2510 /* ICH10 */
2511 { PCI_DEVICE(0x8086, 0x3a3e),
2512 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2513 /* ICH10 */
2514 { PCI_DEVICE(0x8086, 0x3a6e),
2515 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2516 /* Generic Intel */
2517 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2518 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2519 .class_mask = 0xffffff,
2520 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2521 /* ATI SB 450/600/700/800/900 */
2522 { PCI_DEVICE(0x1002, 0x437b),
2523 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2524 { PCI_DEVICE(0x1002, 0x4383),
2525 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2526 /* AMD Hudson */
2527 { PCI_DEVICE(0x1022, 0x780d),
2528 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2529 /* AMD, X370 & co */
2530 { PCI_DEVICE(0x1022, 0x1457),
2531 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2532 /* AMD, X570 & co */
2533 { PCI_DEVICE(0x1022, 0x1487),
2534 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2535 /* AMD Stoney */
2536 { PCI_DEVICE(0x1022, 0x157a),
2537 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2538 AZX_DCAPS_PM_RUNTIME },
2539 /* AMD Raven */
2540 { PCI_DEVICE(0x1022, 0x15e3),
2541 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2542 /* ATI HDMI */
2543 { PCI_DEVICE(0x1002, 0x0002),
2544 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2545 { PCI_DEVICE(0x1002, 0x1308),
2546 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2547 { PCI_DEVICE(0x1002, 0x157a),
2548 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2549 { PCI_DEVICE(0x1002, 0x15b3),
2550 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2551 { PCI_DEVICE(0x1002, 0x793b),
2552 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2553 { PCI_DEVICE(0x1002, 0x7919),
2554 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2555 { PCI_DEVICE(0x1002, 0x960f),
2556 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2557 { PCI_DEVICE(0x1002, 0x970f),
2558 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2559 { PCI_DEVICE(0x1002, 0x9840),
2560 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2561 { PCI_DEVICE(0x1002, 0xaa00),
2562 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2563 { PCI_DEVICE(0x1002, 0xaa08),
2564 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2565 { PCI_DEVICE(0x1002, 0xaa10),
2566 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2567 { PCI_DEVICE(0x1002, 0xaa18),
2568 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2569 { PCI_DEVICE(0x1002, 0xaa20),
2570 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2571 { PCI_DEVICE(0x1002, 0xaa28),
2572 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2573 { PCI_DEVICE(0x1002, 0xaa30),
2574 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2575 { PCI_DEVICE(0x1002, 0xaa38),
2576 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2577 { PCI_DEVICE(0x1002, 0xaa40),
2578 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2579 { PCI_DEVICE(0x1002, 0xaa48),
2580 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2581 { PCI_DEVICE(0x1002, 0xaa50),
2582 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2583 { PCI_DEVICE(0x1002, 0xaa58),
2584 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2585 { PCI_DEVICE(0x1002, 0xaa60),
2586 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2587 { PCI_DEVICE(0x1002, 0xaa68),
2588 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2589 { PCI_DEVICE(0x1002, 0xaa80),
2590 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2591 { PCI_DEVICE(0x1002, 0xaa88),
2592 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2593 { PCI_DEVICE(0x1002, 0xaa90),
2594 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2595 { PCI_DEVICE(0x1002, 0xaa98),
2596 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2597 { PCI_DEVICE(0x1002, 0x9902),
2598 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2599 { PCI_DEVICE(0x1002, 0xaaa0),
2600 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2601 { PCI_DEVICE(0x1002, 0xaaa8),
2602 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2603 { PCI_DEVICE(0x1002, 0xaab0),
2604 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2605 { PCI_DEVICE(0x1002, 0xaac0),
2606 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2607 { PCI_DEVICE(0x1002, 0xaac8),
2608 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2609 { PCI_DEVICE(0x1002, 0xaad8),
2610 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2611 AZX_DCAPS_PM_RUNTIME },
2612 { PCI_DEVICE(0x1002, 0xaae0),
2613 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2614 AZX_DCAPS_PM_RUNTIME },
2615 { PCI_DEVICE(0x1002, 0xaae8),
2616 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2617 AZX_DCAPS_PM_RUNTIME },
2618 { PCI_DEVICE(0x1002, 0xaaf0),
2619 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2620 AZX_DCAPS_PM_RUNTIME },
2621 { PCI_DEVICE(0x1002, 0xaaf8),
2622 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2623 AZX_DCAPS_PM_RUNTIME },
2624 { PCI_DEVICE(0x1002, 0xab00),
2625 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2626 AZX_DCAPS_PM_RUNTIME },
2627 { PCI_DEVICE(0x1002, 0xab08),
2628 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2629 AZX_DCAPS_PM_RUNTIME },
2630 { PCI_DEVICE(0x1002, 0xab10),
2631 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2632 AZX_DCAPS_PM_RUNTIME },
2633 { PCI_DEVICE(0x1002, 0xab18),
2634 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2635 AZX_DCAPS_PM_RUNTIME },
2636 { PCI_DEVICE(0x1002, 0xab20),
2637 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2638 AZX_DCAPS_PM_RUNTIME },
2639 { PCI_DEVICE(0x1002, 0xab38),
2640 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2641 AZX_DCAPS_PM_RUNTIME },
2642 /* VIA VT8251/VT8237A */
2643 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2644 /* VIA GFX VT7122/VX900 */
2645 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2646 /* VIA GFX VT6122/VX11 */
2647 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2648 /* SIS966 */
2649 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2650 /* ULI M5461 */
2651 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2652 /* NVIDIA MCP */
2653 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2654 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2655 .class_mask = 0xffffff,
2656 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2657 /* Teradici */
2658 { PCI_DEVICE(0x6549, 0x1200),
2659 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2660 { PCI_DEVICE(0x6549, 0x2200),
2661 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2662 /* Creative X-Fi (CA0110-IBG) */
2663 /* CTHDA chips */
2664 { PCI_DEVICE(0x1102, 0x0010),
2665 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2666 { PCI_DEVICE(0x1102, 0x0012),
2667 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2668 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2669 /* the following entry conflicts with snd-ctxfi driver,
2670 * as ctxfi driver mutates from HD-audio to native mode with
2671 * a special command sequence.
2672 */
2673 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2674 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2675 .class_mask = 0xffffff,
2676 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2677 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2678 #else
2679 /* this entry seems still valid -- i.e. without emu20kx chip */
2680 { PCI_DEVICE(0x1102, 0x0009),
2681 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2682 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2683 #endif
2684 /* CM8888 */
2685 { PCI_DEVICE(0x13f6, 0x5011),
2686 .driver_data = AZX_DRIVER_CMEDIA |
2687 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2688 /* Vortex86MX */
2689 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2690 /* VMware HDAudio */
2691 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2692 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2693 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2694 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2695 .class_mask = 0xffffff,
2696 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2697 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2698 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2699 .class_mask = 0xffffff,
2700 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2701 /* Zhaoxin */
2702 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2703 { 0, }
2704 };
2705 MODULE_DEVICE_TABLE(pci, azx_ids);
2706
2707 /* pci_driver definition */
2708 static struct pci_driver azx_driver = {
2709 .name = KBUILD_MODNAME,
2710 .id_table = azx_ids,
2711 .probe = azx_probe,
2712 .remove = azx_remove,
2713 .shutdown = azx_shutdown,
2714 .driver = {
2715 .pm = AZX_PM_OPS,
2716 },
2717 };
2718
2719 module_pci_driver(azx_driver);
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