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[thirdparty/linux.git] / sound / pci / ice1712 / ice1724.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ALSA driver for VT1724 ICEnsemble ICE1724 / VIA VT1724 (Envy24HT)
4 * VIA VT1720 (Envy24PT)
5 *
6 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
7 * 2002 James Stafford <jstafford@ampltd.com>
8 * 2003 Takashi Iwai <tiwai@suse.de>
9 */
10
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <sound/core.h>
19 #include <sound/info.h>
20 #include <sound/rawmidi.h>
21 #include <sound/initval.h>
22
23 #include <sound/asoundef.h>
24
25 #include "ice1712.h"
26 #include "envy24ht.h"
27
28 /* lowlevel routines */
29 #include "amp.h"
30 #include "revo.h"
31 #include "aureon.h"
32 #include "vt1720_mobo.h"
33 #include "pontis.h"
34 #include "prodigy192.h"
35 #include "prodigy_hifi.h"
36 #include "juli.h"
37 #include "maya44.h"
38 #include "phase.h"
39 #include "wtm.h"
40 #include "se.h"
41 #include "quartet.h"
42 #include "psc724.h"
43
44 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
45 MODULE_DESCRIPTION("VIA ICEnsemble ICE1724/1720 (Envy24HT/PT)");
46 MODULE_LICENSE("GPL");
47 MODULE_SUPPORTED_DEVICE("{"
48 REVO_DEVICE_DESC
49 AMP_AUDIO2000_DEVICE_DESC
50 AUREON_DEVICE_DESC
51 VT1720_MOBO_DEVICE_DESC
52 PONTIS_DEVICE_DESC
53 PRODIGY192_DEVICE_DESC
54 PRODIGY_HIFI_DEVICE_DESC
55 JULI_DEVICE_DESC
56 MAYA44_DEVICE_DESC
57 PHASE_DEVICE_DESC
58 WTM_DEVICE_DESC
59 SE_DEVICE_DESC
60 QTET_DEVICE_DESC
61 "{VIA,VT1720},"
62 "{VIA,VT1724},"
63 "{ICEnsemble,Generic ICE1724},"
64 "{ICEnsemble,Generic Envy24HT}"
65 "{ICEnsemble,Generic Envy24PT}}");
66
67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
69 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
70 static char *model[SNDRV_CARDS];
71
72 module_param_array(index, int, NULL, 0444);
73 MODULE_PARM_DESC(index, "Index value for ICE1724 soundcard.");
74 module_param_array(id, charp, NULL, 0444);
75 MODULE_PARM_DESC(id, "ID string for ICE1724 soundcard.");
76 module_param_array(enable, bool, NULL, 0444);
77 MODULE_PARM_DESC(enable, "Enable ICE1724 soundcard.");
78 module_param_array(model, charp, NULL, 0444);
79 MODULE_PARM_DESC(model, "Use the given board model.");
80
81
82 /* Both VT1720 and VT1724 have the same PCI IDs */
83 static const struct pci_device_id snd_vt1724_ids[] = {
84 { PCI_VDEVICE(ICE, PCI_DEVICE_ID_VT1724), 0 },
85 { 0, }
86 };
87
88 MODULE_DEVICE_TABLE(pci, snd_vt1724_ids);
89
90
91 static int PRO_RATE_LOCKED;
92 static int PRO_RATE_RESET = 1;
93 static unsigned int PRO_RATE_DEFAULT = 44100;
94
95 static const char * const ext_clock_names[1] = { "IEC958 In" };
96
97 /*
98 * Basic I/O
99 */
100
101 /*
102 * default rates, default clock routines
103 */
104
105 /* check whether the clock mode is spdif-in */
106 static inline int stdclock_is_spdif_master(struct snd_ice1712 *ice)
107 {
108 return (inb(ICEMT1724(ice, RATE)) & VT1724_SPDIF_MASTER) ? 1 : 0;
109 }
110
111 /*
112 * locking rate makes sense only for internal clock mode
113 */
114 static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
115 {
116 return (!ice->is_spdif_master(ice)) && PRO_RATE_LOCKED;
117 }
118
119 /*
120 * ac97 section
121 */
122
123 static unsigned char snd_vt1724_ac97_ready(struct snd_ice1712 *ice)
124 {
125 unsigned char old_cmd;
126 int tm;
127 for (tm = 0; tm < 0x10000; tm++) {
128 old_cmd = inb(ICEMT1724(ice, AC97_CMD));
129 if (old_cmd & (VT1724_AC97_WRITE | VT1724_AC97_READ))
130 continue;
131 if (!(old_cmd & VT1724_AC97_READY))
132 continue;
133 return old_cmd;
134 }
135 dev_dbg(ice->card->dev, "snd_vt1724_ac97_ready: timeout\n");
136 return old_cmd;
137 }
138
139 static int snd_vt1724_ac97_wait_bit(struct snd_ice1712 *ice, unsigned char bit)
140 {
141 int tm;
142 for (tm = 0; tm < 0x10000; tm++)
143 if ((inb(ICEMT1724(ice, AC97_CMD)) & bit) == 0)
144 return 0;
145 dev_dbg(ice->card->dev, "snd_vt1724_ac97_wait_bit: timeout\n");
146 return -EIO;
147 }
148
149 static void snd_vt1724_ac97_write(struct snd_ac97 *ac97,
150 unsigned short reg,
151 unsigned short val)
152 {
153 struct snd_ice1712 *ice = ac97->private_data;
154 unsigned char old_cmd;
155
156 old_cmd = snd_vt1724_ac97_ready(ice);
157 old_cmd &= ~VT1724_AC97_ID_MASK;
158 old_cmd |= ac97->num;
159 outb(reg, ICEMT1724(ice, AC97_INDEX));
160 outw(val, ICEMT1724(ice, AC97_DATA));
161 outb(old_cmd | VT1724_AC97_WRITE, ICEMT1724(ice, AC97_CMD));
162 snd_vt1724_ac97_wait_bit(ice, VT1724_AC97_WRITE);
163 }
164
165 static unsigned short snd_vt1724_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
166 {
167 struct snd_ice1712 *ice = ac97->private_data;
168 unsigned char old_cmd;
169
170 old_cmd = snd_vt1724_ac97_ready(ice);
171 old_cmd &= ~VT1724_AC97_ID_MASK;
172 old_cmd |= ac97->num;
173 outb(reg, ICEMT1724(ice, AC97_INDEX));
174 outb(old_cmd | VT1724_AC97_READ, ICEMT1724(ice, AC97_CMD));
175 if (snd_vt1724_ac97_wait_bit(ice, VT1724_AC97_READ) < 0)
176 return ~0;
177 return inw(ICEMT1724(ice, AC97_DATA));
178 }
179
180
181 /*
182 * GPIO operations
183 */
184
185 /* set gpio direction 0 = read, 1 = write */
186 static void snd_vt1724_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
187 {
188 outl(data, ICEREG1724(ice, GPIO_DIRECTION));
189 inw(ICEREG1724(ice, GPIO_DIRECTION)); /* dummy read for pci-posting */
190 }
191
192 /* get gpio direction 0 = read, 1 = write */
193 static unsigned int snd_vt1724_get_gpio_dir(struct snd_ice1712 *ice)
194 {
195 return inl(ICEREG1724(ice, GPIO_DIRECTION));
196 }
197
198 /* set the gpio mask (0 = writable) */
199 static void snd_vt1724_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
200 {
201 outw(data, ICEREG1724(ice, GPIO_WRITE_MASK));
202 if (!ice->vt1720) /* VT1720 supports only 16 GPIO bits */
203 outb((data >> 16) & 0xff, ICEREG1724(ice, GPIO_WRITE_MASK_22));
204 inw(ICEREG1724(ice, GPIO_WRITE_MASK)); /* dummy read for pci-posting */
205 }
206
207 static unsigned int snd_vt1724_get_gpio_mask(struct snd_ice1712 *ice)
208 {
209 unsigned int mask;
210 if (!ice->vt1720)
211 mask = (unsigned int)inb(ICEREG1724(ice, GPIO_WRITE_MASK_22));
212 else
213 mask = 0;
214 mask = (mask << 16) | inw(ICEREG1724(ice, GPIO_WRITE_MASK));
215 return mask;
216 }
217
218 static void snd_vt1724_set_gpio_data(struct snd_ice1712 *ice, unsigned int data)
219 {
220 outw(data, ICEREG1724(ice, GPIO_DATA));
221 if (!ice->vt1720)
222 outb(data >> 16, ICEREG1724(ice, GPIO_DATA_22));
223 inw(ICEREG1724(ice, GPIO_DATA)); /* dummy read for pci-posting */
224 }
225
226 static unsigned int snd_vt1724_get_gpio_data(struct snd_ice1712 *ice)
227 {
228 unsigned int data;
229 if (!ice->vt1720)
230 data = (unsigned int)inb(ICEREG1724(ice, GPIO_DATA_22));
231 else
232 data = 0;
233 data = (data << 16) | inw(ICEREG1724(ice, GPIO_DATA));
234 return data;
235 }
236
237 /*
238 * MIDI
239 */
240
241 static void vt1724_midi_clear_rx(struct snd_ice1712 *ice)
242 {
243 unsigned int count;
244
245 for (count = inb(ICEREG1724(ice, MPU_RXFIFO)); count > 0; --count)
246 inb(ICEREG1724(ice, MPU_DATA));
247 }
248
249 static inline struct snd_rawmidi_substream *
250 get_rawmidi_substream(struct snd_ice1712 *ice, unsigned int stream)
251 {
252 return list_first_entry(&ice->rmidi[0]->streams[stream].substreams,
253 struct snd_rawmidi_substream, list);
254 }
255
256 static void enable_midi_irq(struct snd_ice1712 *ice, u8 flag, int enable);
257
258 static void vt1724_midi_write(struct snd_ice1712 *ice)
259 {
260 struct snd_rawmidi_substream *s;
261 int count, i;
262 u8 buffer[32];
263
264 s = get_rawmidi_substream(ice, SNDRV_RAWMIDI_STREAM_OUTPUT);
265 count = 31 - inb(ICEREG1724(ice, MPU_TXFIFO));
266 if (count > 0) {
267 count = snd_rawmidi_transmit(s, buffer, count);
268 for (i = 0; i < count; ++i)
269 outb(buffer[i], ICEREG1724(ice, MPU_DATA));
270 }
271 /* mask irq when all bytes have been transmitted.
272 * enabled again in output_trigger when the new data comes in.
273 */
274 enable_midi_irq(ice, VT1724_IRQ_MPU_TX,
275 !snd_rawmidi_transmit_empty(s));
276 }
277
278 static void vt1724_midi_read(struct snd_ice1712 *ice)
279 {
280 struct snd_rawmidi_substream *s;
281 int count, i;
282 u8 buffer[32];
283
284 s = get_rawmidi_substream(ice, SNDRV_RAWMIDI_STREAM_INPUT);
285 count = inb(ICEREG1724(ice, MPU_RXFIFO));
286 if (count > 0) {
287 count = min(count, 32);
288 for (i = 0; i < count; ++i)
289 buffer[i] = inb(ICEREG1724(ice, MPU_DATA));
290 snd_rawmidi_receive(s, buffer, count);
291 }
292 }
293
294 /* call with ice->reg_lock */
295 static void enable_midi_irq(struct snd_ice1712 *ice, u8 flag, int enable)
296 {
297 u8 mask = inb(ICEREG1724(ice, IRQMASK));
298 if (enable)
299 mask &= ~flag;
300 else
301 mask |= flag;
302 outb(mask, ICEREG1724(ice, IRQMASK));
303 }
304
305 static void vt1724_enable_midi_irq(struct snd_rawmidi_substream *substream,
306 u8 flag, int enable)
307 {
308 struct snd_ice1712 *ice = substream->rmidi->private_data;
309
310 spin_lock_irq(&ice->reg_lock);
311 enable_midi_irq(ice, flag, enable);
312 spin_unlock_irq(&ice->reg_lock);
313 }
314
315 static int vt1724_midi_output_open(struct snd_rawmidi_substream *s)
316 {
317 return 0;
318 }
319
320 static int vt1724_midi_output_close(struct snd_rawmidi_substream *s)
321 {
322 return 0;
323 }
324
325 static void vt1724_midi_output_trigger(struct snd_rawmidi_substream *s, int up)
326 {
327 struct snd_ice1712 *ice = s->rmidi->private_data;
328 unsigned long flags;
329
330 spin_lock_irqsave(&ice->reg_lock, flags);
331 if (up) {
332 ice->midi_output = 1;
333 vt1724_midi_write(ice);
334 } else {
335 ice->midi_output = 0;
336 enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
337 }
338 spin_unlock_irqrestore(&ice->reg_lock, flags);
339 }
340
341 static void vt1724_midi_output_drain(struct snd_rawmidi_substream *s)
342 {
343 struct snd_ice1712 *ice = s->rmidi->private_data;
344 unsigned long timeout;
345
346 vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_TX, 0);
347 /* 32 bytes should be transmitted in less than about 12 ms */
348 timeout = jiffies + msecs_to_jiffies(15);
349 do {
350 if (inb(ICEREG1724(ice, MPU_CTRL)) & VT1724_MPU_TX_EMPTY)
351 break;
352 schedule_timeout_uninterruptible(1);
353 } while (time_after(timeout, jiffies));
354 }
355
356 static const struct snd_rawmidi_ops vt1724_midi_output_ops = {
357 .open = vt1724_midi_output_open,
358 .close = vt1724_midi_output_close,
359 .trigger = vt1724_midi_output_trigger,
360 .drain = vt1724_midi_output_drain,
361 };
362
363 static int vt1724_midi_input_open(struct snd_rawmidi_substream *s)
364 {
365 vt1724_midi_clear_rx(s->rmidi->private_data);
366 vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_RX, 1);
367 return 0;
368 }
369
370 static int vt1724_midi_input_close(struct snd_rawmidi_substream *s)
371 {
372 vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_RX, 0);
373 return 0;
374 }
375
376 static void vt1724_midi_input_trigger(struct snd_rawmidi_substream *s, int up)
377 {
378 struct snd_ice1712 *ice = s->rmidi->private_data;
379 unsigned long flags;
380
381 spin_lock_irqsave(&ice->reg_lock, flags);
382 if (up) {
383 ice->midi_input = 1;
384 vt1724_midi_read(ice);
385 } else {
386 ice->midi_input = 0;
387 }
388 spin_unlock_irqrestore(&ice->reg_lock, flags);
389 }
390
391 static const struct snd_rawmidi_ops vt1724_midi_input_ops = {
392 .open = vt1724_midi_input_open,
393 .close = vt1724_midi_input_close,
394 .trigger = vt1724_midi_input_trigger,
395 };
396
397
398 /*
399 * Interrupt handler
400 */
401
402 static irqreturn_t snd_vt1724_interrupt(int irq, void *dev_id)
403 {
404 struct snd_ice1712 *ice = dev_id;
405 unsigned char status;
406 unsigned char status_mask =
407 VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX | VT1724_IRQ_MTPCM;
408 int handled = 0;
409 int timeout = 0;
410
411 while (1) {
412 status = inb(ICEREG1724(ice, IRQSTAT));
413 status &= status_mask;
414 if (status == 0)
415 break;
416 spin_lock(&ice->reg_lock);
417 if (++timeout > 10) {
418 status = inb(ICEREG1724(ice, IRQSTAT));
419 dev_err(ice->card->dev,
420 "Too long irq loop, status = 0x%x\n", status);
421 if (status & VT1724_IRQ_MPU_TX) {
422 dev_err(ice->card->dev, "Disabling MPU_TX\n");
423 enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
424 }
425 spin_unlock(&ice->reg_lock);
426 break;
427 }
428 handled = 1;
429 if (status & VT1724_IRQ_MPU_TX) {
430 if (ice->midi_output)
431 vt1724_midi_write(ice);
432 else
433 enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
434 /* Due to mysterical reasons, MPU_TX is always
435 * generated (and can't be cleared) when a PCM
436 * playback is going. So let's ignore at the
437 * next loop.
438 */
439 status_mask &= ~VT1724_IRQ_MPU_TX;
440 }
441 if (status & VT1724_IRQ_MPU_RX) {
442 if (ice->midi_input)
443 vt1724_midi_read(ice);
444 else
445 vt1724_midi_clear_rx(ice);
446 }
447 /* ack MPU irq */
448 outb(status, ICEREG1724(ice, IRQSTAT));
449 spin_unlock(&ice->reg_lock);
450 if (status & VT1724_IRQ_MTPCM) {
451 /*
452 * Multi-track PCM
453 * PCM assignment are:
454 * Playback DMA0 (M/C) = playback_pro_substream
455 * Playback DMA1 = playback_con_substream_ds[0]
456 * Playback DMA2 = playback_con_substream_ds[1]
457 * Playback DMA3 = playback_con_substream_ds[2]
458 * Playback DMA4 (SPDIF) = playback_con_substream
459 * Record DMA0 = capture_pro_substream
460 * Record DMA1 = capture_con_substream
461 */
462 unsigned char mtstat = inb(ICEMT1724(ice, IRQ));
463 if (mtstat & VT1724_MULTI_PDMA0) {
464 if (ice->playback_pro_substream)
465 snd_pcm_period_elapsed(ice->playback_pro_substream);
466 }
467 if (mtstat & VT1724_MULTI_RDMA0) {
468 if (ice->capture_pro_substream)
469 snd_pcm_period_elapsed(ice->capture_pro_substream);
470 }
471 if (mtstat & VT1724_MULTI_PDMA1) {
472 if (ice->playback_con_substream_ds[0])
473 snd_pcm_period_elapsed(ice->playback_con_substream_ds[0]);
474 }
475 if (mtstat & VT1724_MULTI_PDMA2) {
476 if (ice->playback_con_substream_ds[1])
477 snd_pcm_period_elapsed(ice->playback_con_substream_ds[1]);
478 }
479 if (mtstat & VT1724_MULTI_PDMA3) {
480 if (ice->playback_con_substream_ds[2])
481 snd_pcm_period_elapsed(ice->playback_con_substream_ds[2]);
482 }
483 if (mtstat & VT1724_MULTI_PDMA4) {
484 if (ice->playback_con_substream)
485 snd_pcm_period_elapsed(ice->playback_con_substream);
486 }
487 if (mtstat & VT1724_MULTI_RDMA1) {
488 if (ice->capture_con_substream)
489 snd_pcm_period_elapsed(ice->capture_con_substream);
490 }
491 /* ack anyway to avoid freeze */
492 outb(mtstat, ICEMT1724(ice, IRQ));
493 /* ought to really handle this properly */
494 if (mtstat & VT1724_MULTI_FIFO_ERR) {
495 unsigned char fstat = inb(ICEMT1724(ice, DMA_FIFO_ERR));
496 outb(fstat, ICEMT1724(ice, DMA_FIFO_ERR));
497 outb(VT1724_MULTI_FIFO_ERR | inb(ICEMT1724(ice, DMA_INT_MASK)), ICEMT1724(ice, DMA_INT_MASK));
498 /* If I don't do this, I get machine lockup due to continual interrupts */
499 }
500
501 }
502 }
503 return IRQ_RETVAL(handled);
504 }
505
506 /*
507 * PCM code - professional part (multitrack)
508 */
509
510 static const unsigned int rates[] = {
511 8000, 9600, 11025, 12000, 16000, 22050, 24000,
512 32000, 44100, 48000, 64000, 88200, 96000,
513 176400, 192000,
514 };
515
516 static const struct snd_pcm_hw_constraint_list hw_constraints_rates_96 = {
517 .count = ARRAY_SIZE(rates) - 2, /* up to 96000 */
518 .list = rates,
519 .mask = 0,
520 };
521
522 static const struct snd_pcm_hw_constraint_list hw_constraints_rates_48 = {
523 .count = ARRAY_SIZE(rates) - 5, /* up to 48000 */
524 .list = rates,
525 .mask = 0,
526 };
527
528 static const struct snd_pcm_hw_constraint_list hw_constraints_rates_192 = {
529 .count = ARRAY_SIZE(rates),
530 .list = rates,
531 .mask = 0,
532 };
533
534 struct vt1724_pcm_reg {
535 unsigned int addr; /* ADDR register offset */
536 unsigned int size; /* SIZE register offset */
537 unsigned int count; /* COUNT register offset */
538 unsigned int start; /* start & pause bit */
539 };
540
541 static int snd_vt1724_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
542 {
543 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
544 unsigned char what;
545 unsigned char old;
546 struct snd_pcm_substream *s;
547
548 what = 0;
549 snd_pcm_group_for_each_entry(s, substream) {
550 if (snd_pcm_substream_chip(s) == ice) {
551 const struct vt1724_pcm_reg *reg;
552 reg = s->runtime->private_data;
553 what |= reg->start;
554 snd_pcm_trigger_done(s, substream);
555 }
556 }
557
558 switch (cmd) {
559 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
560 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
561 spin_lock(&ice->reg_lock);
562 old = inb(ICEMT1724(ice, DMA_PAUSE));
563 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
564 old |= what;
565 else
566 old &= ~what;
567 outb(old, ICEMT1724(ice, DMA_PAUSE));
568 spin_unlock(&ice->reg_lock);
569 break;
570
571 case SNDRV_PCM_TRIGGER_START:
572 case SNDRV_PCM_TRIGGER_STOP:
573 case SNDRV_PCM_TRIGGER_SUSPEND:
574 spin_lock(&ice->reg_lock);
575 old = inb(ICEMT1724(ice, DMA_CONTROL));
576 if (cmd == SNDRV_PCM_TRIGGER_START)
577 old |= what;
578 else
579 old &= ~what;
580 outb(old, ICEMT1724(ice, DMA_CONTROL));
581 spin_unlock(&ice->reg_lock);
582 break;
583
584 case SNDRV_PCM_TRIGGER_RESUME:
585 /* apps will have to restart stream */
586 break;
587
588 default:
589 return -EINVAL;
590 }
591 return 0;
592 }
593
594 /*
595 */
596
597 #define DMA_STARTS (VT1724_RDMA0_START|VT1724_PDMA0_START|VT1724_RDMA1_START|\
598 VT1724_PDMA1_START|VT1724_PDMA2_START|VT1724_PDMA3_START|VT1724_PDMA4_START)
599 #define DMA_PAUSES (VT1724_RDMA0_PAUSE|VT1724_PDMA0_PAUSE|VT1724_RDMA1_PAUSE|\
600 VT1724_PDMA1_PAUSE|VT1724_PDMA2_PAUSE|VT1724_PDMA3_PAUSE|VT1724_PDMA4_PAUSE)
601
602 static const unsigned int stdclock_rate_list[16] = {
603 48000, 24000, 12000, 9600, 32000, 16000, 8000, 96000, 44100,
604 22050, 11025, 88200, 176400, 0, 192000, 64000
605 };
606
607 static unsigned int stdclock_get_rate(struct snd_ice1712 *ice)
608 {
609 return stdclock_rate_list[inb(ICEMT1724(ice, RATE)) & 15];
610 }
611
612 static void stdclock_set_rate(struct snd_ice1712 *ice, unsigned int rate)
613 {
614 int i;
615 for (i = 0; i < ARRAY_SIZE(stdclock_rate_list); i++) {
616 if (stdclock_rate_list[i] == rate) {
617 outb(i, ICEMT1724(ice, RATE));
618 return;
619 }
620 }
621 }
622
623 static unsigned char stdclock_set_mclk(struct snd_ice1712 *ice,
624 unsigned int rate)
625 {
626 unsigned char val, old;
627 /* check MT02 */
628 if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
629 val = old = inb(ICEMT1724(ice, I2S_FORMAT));
630 if (rate > 96000)
631 val |= VT1724_MT_I2S_MCLK_128X; /* 128x MCLK */
632 else
633 val &= ~VT1724_MT_I2S_MCLK_128X; /* 256x MCLK */
634 if (val != old) {
635 outb(val, ICEMT1724(ice, I2S_FORMAT));
636 /* master clock changed */
637 return 1;
638 }
639 }
640 /* no change in master clock */
641 return 0;
642 }
643
644 static int snd_vt1724_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate,
645 int force)
646 {
647 unsigned long flags;
648 unsigned char mclk_change;
649 unsigned int i, old_rate;
650
651 if (rate > ice->hw_rates->list[ice->hw_rates->count - 1])
652 return -EINVAL;
653
654 spin_lock_irqsave(&ice->reg_lock, flags);
655 if ((inb(ICEMT1724(ice, DMA_CONTROL)) & DMA_STARTS) ||
656 (inb(ICEMT1724(ice, DMA_PAUSE)) & DMA_PAUSES)) {
657 /* running? we cannot change the rate now... */
658 spin_unlock_irqrestore(&ice->reg_lock, flags);
659 return ((rate == ice->cur_rate) && !force) ? 0 : -EBUSY;
660 }
661 if (!force && is_pro_rate_locked(ice)) {
662 /* comparing required and current rate - makes sense for
663 * internal clock only */
664 spin_unlock_irqrestore(&ice->reg_lock, flags);
665 return (rate == ice->cur_rate) ? 0 : -EBUSY;
666 }
667
668 if (force || !ice->is_spdif_master(ice)) {
669 /* force means the rate was switched by ucontrol, otherwise
670 * setting clock rate for internal clock mode */
671 old_rate = ice->get_rate(ice);
672 if (force || (old_rate != rate))
673 ice->set_rate(ice, rate);
674 else if (rate == ice->cur_rate) {
675 spin_unlock_irqrestore(&ice->reg_lock, flags);
676 return 0;
677 }
678 }
679
680 ice->cur_rate = rate;
681
682 /* setting master clock */
683 mclk_change = ice->set_mclk(ice, rate);
684
685 spin_unlock_irqrestore(&ice->reg_lock, flags);
686
687 if (mclk_change && ice->gpio.i2s_mclk_changed)
688 ice->gpio.i2s_mclk_changed(ice);
689 if (ice->gpio.set_pro_rate)
690 ice->gpio.set_pro_rate(ice, rate);
691
692 /* set up codecs */
693 for (i = 0; i < ice->akm_codecs; i++) {
694 if (ice->akm[i].ops.set_rate_val)
695 ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
696 }
697 if (ice->spdif.ops.setup_rate)
698 ice->spdif.ops.setup_rate(ice, rate);
699
700 return 0;
701 }
702
703 static int snd_vt1724_pcm_hw_params(struct snd_pcm_substream *substream,
704 struct snd_pcm_hw_params *hw_params)
705 {
706 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
707 int i, chs;
708
709 chs = params_channels(hw_params);
710 mutex_lock(&ice->open_mutex);
711 /* mark surround channels */
712 if (substream == ice->playback_pro_substream) {
713 /* PDMA0 can be multi-channel up to 8 */
714 chs = chs / 2 - 1;
715 for (i = 0; i < chs; i++) {
716 if (ice->pcm_reserved[i] &&
717 ice->pcm_reserved[i] != substream) {
718 mutex_unlock(&ice->open_mutex);
719 return -EBUSY;
720 }
721 ice->pcm_reserved[i] = substream;
722 }
723 for (; i < 3; i++) {
724 if (ice->pcm_reserved[i] == substream)
725 ice->pcm_reserved[i] = NULL;
726 }
727 } else {
728 for (i = 0; i < 3; i++) {
729 /* check individual playback stream */
730 if (ice->playback_con_substream_ds[i] == substream) {
731 if (ice->pcm_reserved[i] &&
732 ice->pcm_reserved[i] != substream) {
733 mutex_unlock(&ice->open_mutex);
734 return -EBUSY;
735 }
736 ice->pcm_reserved[i] = substream;
737 break;
738 }
739 }
740 }
741 mutex_unlock(&ice->open_mutex);
742
743 return snd_vt1724_set_pro_rate(ice, params_rate(hw_params), 0);
744 }
745
746 static int snd_vt1724_pcm_hw_free(struct snd_pcm_substream *substream)
747 {
748 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
749 int i;
750
751 mutex_lock(&ice->open_mutex);
752 /* unmark surround channels */
753 for (i = 0; i < 3; i++)
754 if (ice->pcm_reserved[i] == substream)
755 ice->pcm_reserved[i] = NULL;
756 mutex_unlock(&ice->open_mutex);
757 return 0;
758 }
759
760 static int snd_vt1724_playback_pro_prepare(struct snd_pcm_substream *substream)
761 {
762 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
763 unsigned char val;
764 unsigned int size;
765
766 spin_lock_irq(&ice->reg_lock);
767 val = (8 - substream->runtime->channels) >> 1;
768 outb(val, ICEMT1724(ice, BURST));
769
770 outl(substream->runtime->dma_addr, ICEMT1724(ice, PLAYBACK_ADDR));
771
772 size = (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1;
773 /* outl(size, ICEMT1724(ice, PLAYBACK_SIZE)); */
774 outw(size, ICEMT1724(ice, PLAYBACK_SIZE));
775 outb(size >> 16, ICEMT1724(ice, PLAYBACK_SIZE) + 2);
776 size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
777 /* outl(size, ICEMT1724(ice, PLAYBACK_COUNT)); */
778 outw(size, ICEMT1724(ice, PLAYBACK_COUNT));
779 outb(size >> 16, ICEMT1724(ice, PLAYBACK_COUNT) + 2);
780
781 spin_unlock_irq(&ice->reg_lock);
782
783 /*
784 dev_dbg(ice->card->dev, "pro prepare: ch = %d, addr = 0x%x, "
785 "buffer = 0x%x, period = 0x%x\n",
786 substream->runtime->channels,
787 (unsigned int)substream->runtime->dma_addr,
788 snd_pcm_lib_buffer_bytes(substream),
789 snd_pcm_lib_period_bytes(substream));
790 */
791 return 0;
792 }
793
794 static snd_pcm_uframes_t snd_vt1724_playback_pro_pointer(struct snd_pcm_substream *substream)
795 {
796 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
797 size_t ptr;
798
799 if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & VT1724_PDMA0_START))
800 return 0;
801 #if 0 /* read PLAYBACK_ADDR */
802 ptr = inl(ICEMT1724(ice, PLAYBACK_ADDR));
803 if (ptr < substream->runtime->dma_addr) {
804 dev_dbg(ice->card->dev, "invalid negative ptr\n");
805 return 0;
806 }
807 ptr -= substream->runtime->dma_addr;
808 ptr = bytes_to_frames(substream->runtime, ptr);
809 if (ptr >= substream->runtime->buffer_size) {
810 dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
811 (int)ptr, (int)substream->runtime->period_size);
812 return 0;
813 }
814 #else /* read PLAYBACK_SIZE */
815 ptr = inl(ICEMT1724(ice, PLAYBACK_SIZE)) & 0xffffff;
816 ptr = (ptr + 1) << 2;
817 ptr = bytes_to_frames(substream->runtime, ptr);
818 if (!ptr)
819 ;
820 else if (ptr <= substream->runtime->buffer_size)
821 ptr = substream->runtime->buffer_size - ptr;
822 else {
823 dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
824 (int)ptr, (int)substream->runtime->buffer_size);
825 ptr = 0;
826 }
827 #endif
828 return ptr;
829 }
830
831 static int snd_vt1724_pcm_prepare(struct snd_pcm_substream *substream)
832 {
833 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
834 const struct vt1724_pcm_reg *reg = substream->runtime->private_data;
835
836 spin_lock_irq(&ice->reg_lock);
837 outl(substream->runtime->dma_addr, ice->profi_port + reg->addr);
838 outw((snd_pcm_lib_buffer_bytes(substream) >> 2) - 1,
839 ice->profi_port + reg->size);
840 outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1,
841 ice->profi_port + reg->count);
842 spin_unlock_irq(&ice->reg_lock);
843 return 0;
844 }
845
846 static snd_pcm_uframes_t snd_vt1724_pcm_pointer(struct snd_pcm_substream *substream)
847 {
848 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
849 const struct vt1724_pcm_reg *reg = substream->runtime->private_data;
850 size_t ptr;
851
852 if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & reg->start))
853 return 0;
854 #if 0 /* use ADDR register */
855 ptr = inl(ice->profi_port + reg->addr);
856 ptr -= substream->runtime->dma_addr;
857 return bytes_to_frames(substream->runtime, ptr);
858 #else /* use SIZE register */
859 ptr = inw(ice->profi_port + reg->size);
860 ptr = (ptr + 1) << 2;
861 ptr = bytes_to_frames(substream->runtime, ptr);
862 if (!ptr)
863 ;
864 else if (ptr <= substream->runtime->buffer_size)
865 ptr = substream->runtime->buffer_size - ptr;
866 else {
867 dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
868 (int)ptr, (int)substream->runtime->buffer_size);
869 ptr = 0;
870 }
871 return ptr;
872 #endif
873 }
874
875 static const struct vt1724_pcm_reg vt1724_pdma0_reg = {
876 .addr = VT1724_MT_PLAYBACK_ADDR,
877 .size = VT1724_MT_PLAYBACK_SIZE,
878 .count = VT1724_MT_PLAYBACK_COUNT,
879 .start = VT1724_PDMA0_START,
880 };
881
882 static const struct vt1724_pcm_reg vt1724_pdma4_reg = {
883 .addr = VT1724_MT_PDMA4_ADDR,
884 .size = VT1724_MT_PDMA4_SIZE,
885 .count = VT1724_MT_PDMA4_COUNT,
886 .start = VT1724_PDMA4_START,
887 };
888
889 static const struct vt1724_pcm_reg vt1724_rdma0_reg = {
890 .addr = VT1724_MT_CAPTURE_ADDR,
891 .size = VT1724_MT_CAPTURE_SIZE,
892 .count = VT1724_MT_CAPTURE_COUNT,
893 .start = VT1724_RDMA0_START,
894 };
895
896 static const struct vt1724_pcm_reg vt1724_rdma1_reg = {
897 .addr = VT1724_MT_RDMA1_ADDR,
898 .size = VT1724_MT_RDMA1_SIZE,
899 .count = VT1724_MT_RDMA1_COUNT,
900 .start = VT1724_RDMA1_START,
901 };
902
903 #define vt1724_playback_pro_reg vt1724_pdma0_reg
904 #define vt1724_playback_spdif_reg vt1724_pdma4_reg
905 #define vt1724_capture_pro_reg vt1724_rdma0_reg
906 #define vt1724_capture_spdif_reg vt1724_rdma1_reg
907
908 static const struct snd_pcm_hardware snd_vt1724_playback_pro = {
909 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
910 SNDRV_PCM_INFO_BLOCK_TRANSFER |
911 SNDRV_PCM_INFO_MMAP_VALID |
912 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
913 .formats = SNDRV_PCM_FMTBIT_S32_LE,
914 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_192000,
915 .rate_min = 8000,
916 .rate_max = 192000,
917 .channels_min = 2,
918 .channels_max = 8,
919 .buffer_bytes_max = (1UL << 21), /* 19bits dword */
920 .period_bytes_min = 8 * 4 * 2, /* FIXME: constraints needed */
921 .period_bytes_max = (1UL << 21),
922 .periods_min = 2,
923 .periods_max = 1024,
924 };
925
926 static const struct snd_pcm_hardware snd_vt1724_spdif = {
927 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
928 SNDRV_PCM_INFO_BLOCK_TRANSFER |
929 SNDRV_PCM_INFO_MMAP_VALID |
930 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
931 .formats = SNDRV_PCM_FMTBIT_S32_LE,
932 .rates = (SNDRV_PCM_RATE_32000|SNDRV_PCM_RATE_44100|
933 SNDRV_PCM_RATE_48000|SNDRV_PCM_RATE_88200|
934 SNDRV_PCM_RATE_96000|SNDRV_PCM_RATE_176400|
935 SNDRV_PCM_RATE_192000),
936 .rate_min = 32000,
937 .rate_max = 192000,
938 .channels_min = 2,
939 .channels_max = 2,
940 .buffer_bytes_max = (1UL << 18), /* 16bits dword */
941 .period_bytes_min = 2 * 4 * 2,
942 .period_bytes_max = (1UL << 18),
943 .periods_min = 2,
944 .periods_max = 1024,
945 };
946
947 static const struct snd_pcm_hardware snd_vt1724_2ch_stereo = {
948 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
949 SNDRV_PCM_INFO_BLOCK_TRANSFER |
950 SNDRV_PCM_INFO_MMAP_VALID |
951 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
952 .formats = SNDRV_PCM_FMTBIT_S32_LE,
953 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_192000,
954 .rate_min = 8000,
955 .rate_max = 192000,
956 .channels_min = 2,
957 .channels_max = 2,
958 .buffer_bytes_max = (1UL << 18), /* 16bits dword */
959 .period_bytes_min = 2 * 4 * 2,
960 .period_bytes_max = (1UL << 18),
961 .periods_min = 2,
962 .periods_max = 1024,
963 };
964
965 /*
966 * set rate constraints
967 */
968 static void set_std_hw_rates(struct snd_ice1712 *ice)
969 {
970 if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
971 /* I2S */
972 /* VT1720 doesn't support more than 96kHz */
973 if ((ice->eeprom.data[ICE_EEP2_I2S] & 0x08) && !ice->vt1720)
974 ice->hw_rates = &hw_constraints_rates_192;
975 else
976 ice->hw_rates = &hw_constraints_rates_96;
977 } else {
978 /* ACLINK */
979 ice->hw_rates = &hw_constraints_rates_48;
980 }
981 }
982
983 static int set_rate_constraints(struct snd_ice1712 *ice,
984 struct snd_pcm_substream *substream)
985 {
986 struct snd_pcm_runtime *runtime = substream->runtime;
987
988 runtime->hw.rate_min = ice->hw_rates->list[0];
989 runtime->hw.rate_max = ice->hw_rates->list[ice->hw_rates->count - 1];
990 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
991 return snd_pcm_hw_constraint_list(runtime, 0,
992 SNDRV_PCM_HW_PARAM_RATE,
993 ice->hw_rates);
994 }
995
996 /* if the card has the internal rate locked (is_pro_locked), limit runtime
997 hw rates to the current internal rate only.
998 */
999 static void constrain_rate_if_locked(struct snd_pcm_substream *substream)
1000 {
1001 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1002 struct snd_pcm_runtime *runtime = substream->runtime;
1003 unsigned int rate;
1004 if (is_pro_rate_locked(ice)) {
1005 rate = ice->get_rate(ice);
1006 if (rate >= runtime->hw.rate_min
1007 && rate <= runtime->hw.rate_max) {
1008 runtime->hw.rate_min = rate;
1009 runtime->hw.rate_max = rate;
1010 }
1011 }
1012 }
1013
1014
1015 /* multi-channel playback needs alignment 8x32bit regardless of the channels
1016 * actually used
1017 */
1018 #define VT1724_BUFFER_ALIGN 0x20
1019
1020 static int snd_vt1724_playback_pro_open(struct snd_pcm_substream *substream)
1021 {
1022 struct snd_pcm_runtime *runtime = substream->runtime;
1023 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1024 int chs, num_indeps;
1025
1026 runtime->private_data = (void *)&vt1724_playback_pro_reg;
1027 ice->playback_pro_substream = substream;
1028 runtime->hw = snd_vt1724_playback_pro;
1029 snd_pcm_set_sync(substream);
1030 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1031 set_rate_constraints(ice, substream);
1032 mutex_lock(&ice->open_mutex);
1033 /* calculate the currently available channels */
1034 num_indeps = ice->num_total_dacs / 2 - 1;
1035 for (chs = 0; chs < num_indeps; chs++) {
1036 if (ice->pcm_reserved[chs])
1037 break;
1038 }
1039 chs = (chs + 1) * 2;
1040 runtime->hw.channels_max = chs;
1041 if (chs > 2) /* channels must be even */
1042 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1043 mutex_unlock(&ice->open_mutex);
1044 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1045 VT1724_BUFFER_ALIGN);
1046 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1047 VT1724_BUFFER_ALIGN);
1048 constrain_rate_if_locked(substream);
1049 if (ice->pro_open)
1050 ice->pro_open(ice, substream);
1051 return 0;
1052 }
1053
1054 static int snd_vt1724_capture_pro_open(struct snd_pcm_substream *substream)
1055 {
1056 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1057 struct snd_pcm_runtime *runtime = substream->runtime;
1058
1059 runtime->private_data = (void *)&vt1724_capture_pro_reg;
1060 ice->capture_pro_substream = substream;
1061 runtime->hw = snd_vt1724_2ch_stereo;
1062 snd_pcm_set_sync(substream);
1063 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1064 set_rate_constraints(ice, substream);
1065 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1066 VT1724_BUFFER_ALIGN);
1067 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1068 VT1724_BUFFER_ALIGN);
1069 constrain_rate_if_locked(substream);
1070 if (ice->pro_open)
1071 ice->pro_open(ice, substream);
1072 return 0;
1073 }
1074
1075 static int snd_vt1724_playback_pro_close(struct snd_pcm_substream *substream)
1076 {
1077 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1078
1079 if (PRO_RATE_RESET)
1080 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1081 ice->playback_pro_substream = NULL;
1082
1083 return 0;
1084 }
1085
1086 static int snd_vt1724_capture_pro_close(struct snd_pcm_substream *substream)
1087 {
1088 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1089
1090 if (PRO_RATE_RESET)
1091 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1092 ice->capture_pro_substream = NULL;
1093 return 0;
1094 }
1095
1096 static const struct snd_pcm_ops snd_vt1724_playback_pro_ops = {
1097 .open = snd_vt1724_playback_pro_open,
1098 .close = snd_vt1724_playback_pro_close,
1099 .hw_params = snd_vt1724_pcm_hw_params,
1100 .hw_free = snd_vt1724_pcm_hw_free,
1101 .prepare = snd_vt1724_playback_pro_prepare,
1102 .trigger = snd_vt1724_pcm_trigger,
1103 .pointer = snd_vt1724_playback_pro_pointer,
1104 };
1105
1106 static const struct snd_pcm_ops snd_vt1724_capture_pro_ops = {
1107 .open = snd_vt1724_capture_pro_open,
1108 .close = snd_vt1724_capture_pro_close,
1109 .hw_params = snd_vt1724_pcm_hw_params,
1110 .hw_free = snd_vt1724_pcm_hw_free,
1111 .prepare = snd_vt1724_pcm_prepare,
1112 .trigger = snd_vt1724_pcm_trigger,
1113 .pointer = snd_vt1724_pcm_pointer,
1114 };
1115
1116 static int snd_vt1724_pcm_profi(struct snd_ice1712 *ice, int device)
1117 {
1118 struct snd_pcm *pcm;
1119 int capt, err;
1120
1121 if ((ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_ADC_MASK) ==
1122 VT1724_CFG_ADC_NONE)
1123 capt = 0;
1124 else
1125 capt = 1;
1126 err = snd_pcm_new(ice->card, "ICE1724", device, 1, capt, &pcm);
1127 if (err < 0)
1128 return err;
1129
1130 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_vt1724_playback_pro_ops);
1131 if (capt)
1132 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
1133 &snd_vt1724_capture_pro_ops);
1134
1135 pcm->private_data = ice;
1136 pcm->info_flags = 0;
1137 strcpy(pcm->name, "ICE1724");
1138
1139 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1140 &ice->pci->dev, 256*1024, 256*1024);
1141
1142 ice->pcm_pro = pcm;
1143
1144 return 0;
1145 }
1146
1147
1148 /*
1149 * SPDIF PCM
1150 */
1151
1152 /* update spdif control bits; call with reg_lock */
1153 static void update_spdif_bits(struct snd_ice1712 *ice, unsigned int val)
1154 {
1155 unsigned char cbit, disabled;
1156
1157 cbit = inb(ICEREG1724(ice, SPDIF_CFG));
1158 disabled = cbit & ~VT1724_CFG_SPDIF_OUT_EN;
1159 if (cbit != disabled)
1160 outb(disabled, ICEREG1724(ice, SPDIF_CFG));
1161 outw(val, ICEMT1724(ice, SPDIF_CTRL));
1162 if (cbit != disabled)
1163 outb(cbit, ICEREG1724(ice, SPDIF_CFG));
1164 outw(val, ICEMT1724(ice, SPDIF_CTRL));
1165 }
1166
1167 /* update SPDIF control bits according to the given rate */
1168 static void update_spdif_rate(struct snd_ice1712 *ice, unsigned int rate)
1169 {
1170 unsigned int val, nval;
1171 unsigned long flags;
1172
1173 spin_lock_irqsave(&ice->reg_lock, flags);
1174 nval = val = inw(ICEMT1724(ice, SPDIF_CTRL));
1175 nval &= ~(7 << 12);
1176 switch (rate) {
1177 case 44100: break;
1178 case 48000: nval |= 2 << 12; break;
1179 case 32000: nval |= 3 << 12; break;
1180 case 88200: nval |= 4 << 12; break;
1181 case 96000: nval |= 5 << 12; break;
1182 case 192000: nval |= 6 << 12; break;
1183 case 176400: nval |= 7 << 12; break;
1184 }
1185 if (val != nval)
1186 update_spdif_bits(ice, nval);
1187 spin_unlock_irqrestore(&ice->reg_lock, flags);
1188 }
1189
1190 static int snd_vt1724_playback_spdif_prepare(struct snd_pcm_substream *substream)
1191 {
1192 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1193 if (!ice->force_pdma4)
1194 update_spdif_rate(ice, substream->runtime->rate);
1195 return snd_vt1724_pcm_prepare(substream);
1196 }
1197
1198 static int snd_vt1724_playback_spdif_open(struct snd_pcm_substream *substream)
1199 {
1200 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1201 struct snd_pcm_runtime *runtime = substream->runtime;
1202
1203 runtime->private_data = (void *)&vt1724_playback_spdif_reg;
1204 ice->playback_con_substream = substream;
1205 if (ice->force_pdma4) {
1206 runtime->hw = snd_vt1724_2ch_stereo;
1207 set_rate_constraints(ice, substream);
1208 } else
1209 runtime->hw = snd_vt1724_spdif;
1210 snd_pcm_set_sync(substream);
1211 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1212 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1213 VT1724_BUFFER_ALIGN);
1214 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1215 VT1724_BUFFER_ALIGN);
1216 constrain_rate_if_locked(substream);
1217 if (ice->spdif.ops.open)
1218 ice->spdif.ops.open(ice, substream);
1219 return 0;
1220 }
1221
1222 static int snd_vt1724_playback_spdif_close(struct snd_pcm_substream *substream)
1223 {
1224 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1225
1226 if (PRO_RATE_RESET)
1227 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1228 ice->playback_con_substream = NULL;
1229 if (ice->spdif.ops.close)
1230 ice->spdif.ops.close(ice, substream);
1231
1232 return 0;
1233 }
1234
1235 static int snd_vt1724_capture_spdif_open(struct snd_pcm_substream *substream)
1236 {
1237 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1238 struct snd_pcm_runtime *runtime = substream->runtime;
1239
1240 runtime->private_data = (void *)&vt1724_capture_spdif_reg;
1241 ice->capture_con_substream = substream;
1242 if (ice->force_rdma1) {
1243 runtime->hw = snd_vt1724_2ch_stereo;
1244 set_rate_constraints(ice, substream);
1245 } else
1246 runtime->hw = snd_vt1724_spdif;
1247 snd_pcm_set_sync(substream);
1248 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1249 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1250 VT1724_BUFFER_ALIGN);
1251 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1252 VT1724_BUFFER_ALIGN);
1253 constrain_rate_if_locked(substream);
1254 if (ice->spdif.ops.open)
1255 ice->spdif.ops.open(ice, substream);
1256 return 0;
1257 }
1258
1259 static int snd_vt1724_capture_spdif_close(struct snd_pcm_substream *substream)
1260 {
1261 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1262
1263 if (PRO_RATE_RESET)
1264 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1265 ice->capture_con_substream = NULL;
1266 if (ice->spdif.ops.close)
1267 ice->spdif.ops.close(ice, substream);
1268
1269 return 0;
1270 }
1271
1272 static const struct snd_pcm_ops snd_vt1724_playback_spdif_ops = {
1273 .open = snd_vt1724_playback_spdif_open,
1274 .close = snd_vt1724_playback_spdif_close,
1275 .hw_params = snd_vt1724_pcm_hw_params,
1276 .hw_free = snd_vt1724_pcm_hw_free,
1277 .prepare = snd_vt1724_playback_spdif_prepare,
1278 .trigger = snd_vt1724_pcm_trigger,
1279 .pointer = snd_vt1724_pcm_pointer,
1280 };
1281
1282 static const struct snd_pcm_ops snd_vt1724_capture_spdif_ops = {
1283 .open = snd_vt1724_capture_spdif_open,
1284 .close = snd_vt1724_capture_spdif_close,
1285 .hw_params = snd_vt1724_pcm_hw_params,
1286 .hw_free = snd_vt1724_pcm_hw_free,
1287 .prepare = snd_vt1724_pcm_prepare,
1288 .trigger = snd_vt1724_pcm_trigger,
1289 .pointer = snd_vt1724_pcm_pointer,
1290 };
1291
1292
1293 static int snd_vt1724_pcm_spdif(struct snd_ice1712 *ice, int device)
1294 {
1295 char *name;
1296 struct snd_pcm *pcm;
1297 int play, capt;
1298 int err;
1299
1300 if (ice->force_pdma4 ||
1301 (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_OUT_INT)) {
1302 play = 1;
1303 ice->has_spdif = 1;
1304 } else
1305 play = 0;
1306 if (ice->force_rdma1 ||
1307 (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_IN)) {
1308 capt = 1;
1309 ice->has_spdif = 1;
1310 } else
1311 capt = 0;
1312 if (!play && !capt)
1313 return 0; /* no spdif device */
1314
1315 if (ice->force_pdma4 || ice->force_rdma1)
1316 name = "ICE1724 Secondary";
1317 else
1318 name = "ICE1724 IEC958";
1319 err = snd_pcm_new(ice->card, name, device, play, capt, &pcm);
1320 if (err < 0)
1321 return err;
1322
1323 if (play)
1324 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1325 &snd_vt1724_playback_spdif_ops);
1326 if (capt)
1327 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
1328 &snd_vt1724_capture_spdif_ops);
1329
1330 pcm->private_data = ice;
1331 pcm->info_flags = 0;
1332 strcpy(pcm->name, name);
1333
1334 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1335 &ice->pci->dev, 256*1024, 256*1024);
1336
1337 ice->pcm = pcm;
1338
1339 return 0;
1340 }
1341
1342
1343 /*
1344 * independent surround PCMs
1345 */
1346
1347 static const struct vt1724_pcm_reg vt1724_playback_dma_regs[3] = {
1348 {
1349 .addr = VT1724_MT_PDMA1_ADDR,
1350 .size = VT1724_MT_PDMA1_SIZE,
1351 .count = VT1724_MT_PDMA1_COUNT,
1352 .start = VT1724_PDMA1_START,
1353 },
1354 {
1355 .addr = VT1724_MT_PDMA2_ADDR,
1356 .size = VT1724_MT_PDMA2_SIZE,
1357 .count = VT1724_MT_PDMA2_COUNT,
1358 .start = VT1724_PDMA2_START,
1359 },
1360 {
1361 .addr = VT1724_MT_PDMA3_ADDR,
1362 .size = VT1724_MT_PDMA3_SIZE,
1363 .count = VT1724_MT_PDMA3_COUNT,
1364 .start = VT1724_PDMA3_START,
1365 },
1366 };
1367
1368 static int snd_vt1724_playback_indep_prepare(struct snd_pcm_substream *substream)
1369 {
1370 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1371 unsigned char val;
1372
1373 spin_lock_irq(&ice->reg_lock);
1374 val = 3 - substream->number;
1375 if (inb(ICEMT1724(ice, BURST)) < val)
1376 outb(val, ICEMT1724(ice, BURST));
1377 spin_unlock_irq(&ice->reg_lock);
1378 return snd_vt1724_pcm_prepare(substream);
1379 }
1380
1381 static int snd_vt1724_playback_indep_open(struct snd_pcm_substream *substream)
1382 {
1383 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1384 struct snd_pcm_runtime *runtime = substream->runtime;
1385
1386 mutex_lock(&ice->open_mutex);
1387 /* already used by PDMA0? */
1388 if (ice->pcm_reserved[substream->number]) {
1389 mutex_unlock(&ice->open_mutex);
1390 return -EBUSY; /* FIXME: should handle blocking mode properly */
1391 }
1392 mutex_unlock(&ice->open_mutex);
1393 runtime->private_data = (void *)&vt1724_playback_dma_regs[substream->number];
1394 ice->playback_con_substream_ds[substream->number] = substream;
1395 runtime->hw = snd_vt1724_2ch_stereo;
1396 snd_pcm_set_sync(substream);
1397 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1398 set_rate_constraints(ice, substream);
1399 return 0;
1400 }
1401
1402 static int snd_vt1724_playback_indep_close(struct snd_pcm_substream *substream)
1403 {
1404 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1405
1406 if (PRO_RATE_RESET)
1407 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1408 ice->playback_con_substream_ds[substream->number] = NULL;
1409 ice->pcm_reserved[substream->number] = NULL;
1410
1411 return 0;
1412 }
1413
1414 static const struct snd_pcm_ops snd_vt1724_playback_indep_ops = {
1415 .open = snd_vt1724_playback_indep_open,
1416 .close = snd_vt1724_playback_indep_close,
1417 .hw_params = snd_vt1724_pcm_hw_params,
1418 .hw_free = snd_vt1724_pcm_hw_free,
1419 .prepare = snd_vt1724_playback_indep_prepare,
1420 .trigger = snd_vt1724_pcm_trigger,
1421 .pointer = snd_vt1724_pcm_pointer,
1422 };
1423
1424
1425 static int snd_vt1724_pcm_indep(struct snd_ice1712 *ice, int device)
1426 {
1427 struct snd_pcm *pcm;
1428 int play;
1429 int err;
1430
1431 play = ice->num_total_dacs / 2 - 1;
1432 if (play <= 0)
1433 return 0;
1434
1435 err = snd_pcm_new(ice->card, "ICE1724 Surrounds", device, play, 0, &pcm);
1436 if (err < 0)
1437 return err;
1438
1439 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1440 &snd_vt1724_playback_indep_ops);
1441
1442 pcm->private_data = ice;
1443 pcm->info_flags = 0;
1444 strcpy(pcm->name, "ICE1724 Surround PCM");
1445
1446 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1447 &ice->pci->dev, 256*1024, 256*1024);
1448
1449 ice->pcm_ds = pcm;
1450
1451 return 0;
1452 }
1453
1454
1455 /*
1456 * Mixer section
1457 */
1458
1459 static int snd_vt1724_ac97_mixer(struct snd_ice1712 *ice)
1460 {
1461 int err;
1462
1463 if (!(ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S)) {
1464 struct snd_ac97_bus *pbus;
1465 struct snd_ac97_template ac97;
1466 static const struct snd_ac97_bus_ops ops = {
1467 .write = snd_vt1724_ac97_write,
1468 .read = snd_vt1724_ac97_read,
1469 };
1470
1471 /* cold reset */
1472 outb(inb(ICEMT1724(ice, AC97_CMD)) | 0x80, ICEMT1724(ice, AC97_CMD));
1473 mdelay(5); /* FIXME */
1474 outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD));
1475
1476 err = snd_ac97_bus(ice->card, 0, &ops, NULL, &pbus);
1477 if (err < 0)
1478 return err;
1479 memset(&ac97, 0, sizeof(ac97));
1480 ac97.private_data = ice;
1481 err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
1482 if (err < 0)
1483 dev_warn(ice->card->dev,
1484 "cannot initialize pro ac97, skipped\n");
1485 else
1486 return 0;
1487 }
1488 /* I2S mixer only */
1489 strcat(ice->card->mixername, "ICE1724 - multitrack");
1490 return 0;
1491 }
1492
1493 /*
1494 *
1495 */
1496
1497 static inline unsigned int eeprom_triple(struct snd_ice1712 *ice, int idx)
1498 {
1499 return (unsigned int)ice->eeprom.data[idx] | \
1500 ((unsigned int)ice->eeprom.data[idx + 1] << 8) | \
1501 ((unsigned int)ice->eeprom.data[idx + 2] << 16);
1502 }
1503
1504 static void snd_vt1724_proc_read(struct snd_info_entry *entry,
1505 struct snd_info_buffer *buffer)
1506 {
1507 struct snd_ice1712 *ice = entry->private_data;
1508 unsigned int idx;
1509
1510 snd_iprintf(buffer, "%s\n\n", ice->card->longname);
1511 snd_iprintf(buffer, "EEPROM:\n");
1512
1513 snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
1514 snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
1515 snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
1516 snd_iprintf(buffer, " System Config : 0x%x\n",
1517 ice->eeprom.data[ICE_EEP2_SYSCONF]);
1518 snd_iprintf(buffer, " ACLink : 0x%x\n",
1519 ice->eeprom.data[ICE_EEP2_ACLINK]);
1520 snd_iprintf(buffer, " I2S : 0x%x\n",
1521 ice->eeprom.data[ICE_EEP2_I2S]);
1522 snd_iprintf(buffer, " S/PDIF : 0x%x\n",
1523 ice->eeprom.data[ICE_EEP2_SPDIF]);
1524 snd_iprintf(buffer, " GPIO direction : 0x%x\n",
1525 ice->eeprom.gpiodir);
1526 snd_iprintf(buffer, " GPIO mask : 0x%x\n",
1527 ice->eeprom.gpiomask);
1528 snd_iprintf(buffer, " GPIO state : 0x%x\n",
1529 ice->eeprom.gpiostate);
1530 for (idx = 0x12; idx < ice->eeprom.size; idx++)
1531 snd_iprintf(buffer, " Extra #%02i : 0x%x\n",
1532 idx, ice->eeprom.data[idx]);
1533
1534 snd_iprintf(buffer, "\nRegisters:\n");
1535
1536 snd_iprintf(buffer, " PSDOUT03 : 0x%08x\n",
1537 (unsigned)inl(ICEMT1724(ice, ROUTE_PLAYBACK)));
1538 for (idx = 0x0; idx < 0x20 ; idx++)
1539 snd_iprintf(buffer, " CCS%02x : 0x%02x\n",
1540 idx, inb(ice->port+idx));
1541 for (idx = 0x0; idx < 0x30 ; idx++)
1542 snd_iprintf(buffer, " MT%02x : 0x%02x\n",
1543 idx, inb(ice->profi_port+idx));
1544 }
1545
1546 static void snd_vt1724_proc_init(struct snd_ice1712 *ice)
1547 {
1548 snd_card_ro_proc_new(ice->card, "ice1724", ice, snd_vt1724_proc_read);
1549 }
1550
1551 /*
1552 *
1553 */
1554
1555 static int snd_vt1724_eeprom_info(struct snd_kcontrol *kcontrol,
1556 struct snd_ctl_elem_info *uinfo)
1557 {
1558 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1559 uinfo->count = sizeof(struct snd_ice1712_eeprom);
1560 return 0;
1561 }
1562
1563 static int snd_vt1724_eeprom_get(struct snd_kcontrol *kcontrol,
1564 struct snd_ctl_elem_value *ucontrol)
1565 {
1566 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1567
1568 memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
1569 return 0;
1570 }
1571
1572 static const struct snd_kcontrol_new snd_vt1724_eeprom = {
1573 .iface = SNDRV_CTL_ELEM_IFACE_CARD,
1574 .name = "ICE1724 EEPROM",
1575 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1576 .info = snd_vt1724_eeprom_info,
1577 .get = snd_vt1724_eeprom_get
1578 };
1579
1580 /*
1581 */
1582 static int snd_vt1724_spdif_info(struct snd_kcontrol *kcontrol,
1583 struct snd_ctl_elem_info *uinfo)
1584 {
1585 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1586 uinfo->count = 1;
1587 return 0;
1588 }
1589
1590 static unsigned int encode_spdif_bits(struct snd_aes_iec958 *diga)
1591 {
1592 unsigned int val, rbits;
1593
1594 val = diga->status[0] & 0x03; /* professional, non-audio */
1595 if (val & 0x01) {
1596 /* professional */
1597 if ((diga->status[0] & IEC958_AES0_PRO_EMPHASIS) ==
1598 IEC958_AES0_PRO_EMPHASIS_5015)
1599 val |= 1U << 3;
1600 rbits = (diga->status[4] >> 3) & 0x0f;
1601 if (rbits) {
1602 switch (rbits) {
1603 case 2: val |= 5 << 12; break; /* 96k */
1604 case 3: val |= 6 << 12; break; /* 192k */
1605 case 10: val |= 4 << 12; break; /* 88.2k */
1606 case 11: val |= 7 << 12; break; /* 176.4k */
1607 }
1608 } else {
1609 switch (diga->status[0] & IEC958_AES0_PRO_FS) {
1610 case IEC958_AES0_PRO_FS_44100:
1611 break;
1612 case IEC958_AES0_PRO_FS_32000:
1613 val |= 3U << 12;
1614 break;
1615 default:
1616 val |= 2U << 12;
1617 break;
1618 }
1619 }
1620 } else {
1621 /* consumer */
1622 val |= diga->status[1] & 0x04; /* copyright */
1623 if ((diga->status[0] & IEC958_AES0_CON_EMPHASIS) ==
1624 IEC958_AES0_CON_EMPHASIS_5015)
1625 val |= 1U << 3;
1626 val |= (unsigned int)(diga->status[1] & 0x3f) << 4; /* category */
1627 val |= (unsigned int)(diga->status[3] & IEC958_AES3_CON_FS) << 12; /* fs */
1628 }
1629 return val;
1630 }
1631
1632 static void decode_spdif_bits(struct snd_aes_iec958 *diga, unsigned int val)
1633 {
1634 memset(diga->status, 0, sizeof(diga->status));
1635 diga->status[0] = val & 0x03; /* professional, non-audio */
1636 if (val & 0x01) {
1637 /* professional */
1638 if (val & (1U << 3))
1639 diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_5015;
1640 switch ((val >> 12) & 0x7) {
1641 case 0:
1642 break;
1643 case 2:
1644 diga->status[0] |= IEC958_AES0_PRO_FS_32000;
1645 break;
1646 default:
1647 diga->status[0] |= IEC958_AES0_PRO_FS_48000;
1648 break;
1649 }
1650 } else {
1651 /* consumer */
1652 diga->status[0] |= val & (1U << 2); /* copyright */
1653 if (val & (1U << 3))
1654 diga->status[0] |= IEC958_AES0_CON_EMPHASIS_5015;
1655 diga->status[1] |= (val >> 4) & 0x3f; /* category */
1656 diga->status[3] |= (val >> 12) & 0x07; /* fs */
1657 }
1658 }
1659
1660 static int snd_vt1724_spdif_default_get(struct snd_kcontrol *kcontrol,
1661 struct snd_ctl_elem_value *ucontrol)
1662 {
1663 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1664 unsigned int val;
1665 val = inw(ICEMT1724(ice, SPDIF_CTRL));
1666 decode_spdif_bits(&ucontrol->value.iec958, val);
1667 return 0;
1668 }
1669
1670 static int snd_vt1724_spdif_default_put(struct snd_kcontrol *kcontrol,
1671 struct snd_ctl_elem_value *ucontrol)
1672 {
1673 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1674 unsigned int val, old;
1675
1676 val = encode_spdif_bits(&ucontrol->value.iec958);
1677 spin_lock_irq(&ice->reg_lock);
1678 old = inw(ICEMT1724(ice, SPDIF_CTRL));
1679 if (val != old)
1680 update_spdif_bits(ice, val);
1681 spin_unlock_irq(&ice->reg_lock);
1682 return val != old;
1683 }
1684
1685 static const struct snd_kcontrol_new snd_vt1724_spdif_default =
1686 {
1687 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1688 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1689 .info = snd_vt1724_spdif_info,
1690 .get = snd_vt1724_spdif_default_get,
1691 .put = snd_vt1724_spdif_default_put
1692 };
1693
1694 static int snd_vt1724_spdif_maskc_get(struct snd_kcontrol *kcontrol,
1695 struct snd_ctl_elem_value *ucontrol)
1696 {
1697 ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
1698 IEC958_AES0_PROFESSIONAL |
1699 IEC958_AES0_CON_NOT_COPYRIGHT |
1700 IEC958_AES0_CON_EMPHASIS;
1701 ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
1702 IEC958_AES1_CON_CATEGORY;
1703 ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
1704 return 0;
1705 }
1706
1707 static int snd_vt1724_spdif_maskp_get(struct snd_kcontrol *kcontrol,
1708 struct snd_ctl_elem_value *ucontrol)
1709 {
1710 ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
1711 IEC958_AES0_PROFESSIONAL |
1712 IEC958_AES0_PRO_FS |
1713 IEC958_AES0_PRO_EMPHASIS;
1714 return 0;
1715 }
1716
1717 static const struct snd_kcontrol_new snd_vt1724_spdif_maskc =
1718 {
1719 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1720 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1721 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1722 .info = snd_vt1724_spdif_info,
1723 .get = snd_vt1724_spdif_maskc_get,
1724 };
1725
1726 static const struct snd_kcontrol_new snd_vt1724_spdif_maskp =
1727 {
1728 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1729 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1730 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1731 .info = snd_vt1724_spdif_info,
1732 .get = snd_vt1724_spdif_maskp_get,
1733 };
1734
1735 #define snd_vt1724_spdif_sw_info snd_ctl_boolean_mono_info
1736
1737 static int snd_vt1724_spdif_sw_get(struct snd_kcontrol *kcontrol,
1738 struct snd_ctl_elem_value *ucontrol)
1739 {
1740 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1741 ucontrol->value.integer.value[0] = inb(ICEREG1724(ice, SPDIF_CFG)) &
1742 VT1724_CFG_SPDIF_OUT_EN ? 1 : 0;
1743 return 0;
1744 }
1745
1746 static int snd_vt1724_spdif_sw_put(struct snd_kcontrol *kcontrol,
1747 struct snd_ctl_elem_value *ucontrol)
1748 {
1749 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1750 unsigned char old, val;
1751
1752 spin_lock_irq(&ice->reg_lock);
1753 old = val = inb(ICEREG1724(ice, SPDIF_CFG));
1754 val &= ~VT1724_CFG_SPDIF_OUT_EN;
1755 if (ucontrol->value.integer.value[0])
1756 val |= VT1724_CFG_SPDIF_OUT_EN;
1757 if (old != val)
1758 outb(val, ICEREG1724(ice, SPDIF_CFG));
1759 spin_unlock_irq(&ice->reg_lock);
1760 return old != val;
1761 }
1762
1763 static const struct snd_kcontrol_new snd_vt1724_spdif_switch =
1764 {
1765 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1766 /* FIXME: the following conflict with IEC958 Playback Route */
1767 /* .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, SWITCH), */
1768 .name = SNDRV_CTL_NAME_IEC958("Output ", NONE, SWITCH),
1769 .info = snd_vt1724_spdif_sw_info,
1770 .get = snd_vt1724_spdif_sw_get,
1771 .put = snd_vt1724_spdif_sw_put
1772 };
1773
1774
1775 #if 0 /* NOT USED YET */
1776 /*
1777 * GPIO access from extern
1778 */
1779
1780 #define snd_vt1724_gpio_info snd_ctl_boolean_mono_info
1781
1782 int snd_vt1724_gpio_get(struct snd_kcontrol *kcontrol,
1783 struct snd_ctl_elem_value *ucontrol)
1784 {
1785 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1786 int shift = kcontrol->private_value & 0xff;
1787 int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
1788
1789 snd_ice1712_save_gpio_status(ice);
1790 ucontrol->value.integer.value[0] =
1791 (snd_ice1712_gpio_read(ice) & (1 << shift) ? 1 : 0) ^ invert;
1792 snd_ice1712_restore_gpio_status(ice);
1793 return 0;
1794 }
1795
1796 int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
1797 struct snd_ctl_elem_value *ucontrol)
1798 {
1799 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1800 int shift = kcontrol->private_value & 0xff;
1801 int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
1802 unsigned int val, nval;
1803
1804 if (kcontrol->private_value & (1 << 31))
1805 return -EPERM;
1806 nval = (ucontrol->value.integer.value[0] ? (1 << shift) : 0) ^ invert;
1807 snd_ice1712_save_gpio_status(ice);
1808 val = snd_ice1712_gpio_read(ice);
1809 nval |= val & ~(1 << shift);
1810 if (val != nval)
1811 snd_ice1712_gpio_write(ice, nval);
1812 snd_ice1712_restore_gpio_status(ice);
1813 return val != nval;
1814 }
1815 #endif /* NOT USED YET */
1816
1817 /*
1818 * rate
1819 */
1820 static int snd_vt1724_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
1821 struct snd_ctl_elem_info *uinfo)
1822 {
1823 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1824 int hw_rates_count = ice->hw_rates->count;
1825 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1826 uinfo->count = 1;
1827
1828 /* internal clocks */
1829 uinfo->value.enumerated.items = hw_rates_count;
1830 /* external clocks */
1831 if (ice->force_rdma1 ||
1832 (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_IN))
1833 uinfo->value.enumerated.items += ice->ext_clock_count;
1834 /* upper limit - keep at top */
1835 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1836 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1837 if (uinfo->value.enumerated.item >= hw_rates_count)
1838 /* ext_clock items */
1839 strcpy(uinfo->value.enumerated.name,
1840 ice->ext_clock_names[
1841 uinfo->value.enumerated.item - hw_rates_count]);
1842 else
1843 /* int clock items */
1844 sprintf(uinfo->value.enumerated.name, "%d",
1845 ice->hw_rates->list[uinfo->value.enumerated.item]);
1846 return 0;
1847 }
1848
1849 static int snd_vt1724_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
1850 struct snd_ctl_elem_value *ucontrol)
1851 {
1852 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1853 unsigned int i, rate;
1854
1855 spin_lock_irq(&ice->reg_lock);
1856 if (ice->is_spdif_master(ice)) {
1857 ucontrol->value.enumerated.item[0] = ice->hw_rates->count +
1858 ice->get_spdif_master_type(ice);
1859 } else {
1860 rate = ice->get_rate(ice);
1861 ucontrol->value.enumerated.item[0] = 0;
1862 for (i = 0; i < ice->hw_rates->count; i++) {
1863 if (ice->hw_rates->list[i] == rate) {
1864 ucontrol->value.enumerated.item[0] = i;
1865 break;
1866 }
1867 }
1868 }
1869 spin_unlock_irq(&ice->reg_lock);
1870 return 0;
1871 }
1872
1873 static int stdclock_get_spdif_master_type(struct snd_ice1712 *ice)
1874 {
1875 /* standard external clock - only single type - SPDIF IN */
1876 return 0;
1877 }
1878
1879 /* setting clock to external - SPDIF */
1880 static int stdclock_set_spdif_clock(struct snd_ice1712 *ice, int type)
1881 {
1882 unsigned char oval;
1883 unsigned char i2s_oval;
1884 oval = inb(ICEMT1724(ice, RATE));
1885 outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
1886 /* setting 256fs */
1887 i2s_oval = inb(ICEMT1724(ice, I2S_FORMAT));
1888 outb(i2s_oval & ~VT1724_MT_I2S_MCLK_128X, ICEMT1724(ice, I2S_FORMAT));
1889 return 0;
1890 }
1891
1892
1893 static int snd_vt1724_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
1894 struct snd_ctl_elem_value *ucontrol)
1895 {
1896 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1897 unsigned int old_rate, new_rate;
1898 unsigned int item = ucontrol->value.enumerated.item[0];
1899 unsigned int first_ext_clock = ice->hw_rates->count;
1900
1901 if (item > first_ext_clock + ice->ext_clock_count - 1)
1902 return -EINVAL;
1903
1904 /* if rate = 0 => external clock */
1905 spin_lock_irq(&ice->reg_lock);
1906 if (ice->is_spdif_master(ice))
1907 old_rate = 0;
1908 else
1909 old_rate = ice->get_rate(ice);
1910 if (item >= first_ext_clock) {
1911 /* switching to external clock */
1912 ice->set_spdif_clock(ice, item - first_ext_clock);
1913 new_rate = 0;
1914 } else {
1915 /* internal on-card clock */
1916 new_rate = ice->hw_rates->list[item];
1917 ice->pro_rate_default = new_rate;
1918 spin_unlock_irq(&ice->reg_lock);
1919 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 1);
1920 spin_lock_irq(&ice->reg_lock);
1921 }
1922 spin_unlock_irq(&ice->reg_lock);
1923
1924 /* the first switch to the ext. clock mode? */
1925 if (old_rate != new_rate && !new_rate) {
1926 /* notify akm chips as well */
1927 unsigned int i;
1928 if (ice->gpio.set_pro_rate)
1929 ice->gpio.set_pro_rate(ice, 0);
1930 for (i = 0; i < ice->akm_codecs; i++) {
1931 if (ice->akm[i].ops.set_rate_val)
1932 ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
1933 }
1934 }
1935 return old_rate != new_rate;
1936 }
1937
1938 static const struct snd_kcontrol_new snd_vt1724_pro_internal_clock = {
1939 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1940 .name = "Multi Track Internal Clock",
1941 .info = snd_vt1724_pro_internal_clock_info,
1942 .get = snd_vt1724_pro_internal_clock_get,
1943 .put = snd_vt1724_pro_internal_clock_put
1944 };
1945
1946 #define snd_vt1724_pro_rate_locking_info snd_ctl_boolean_mono_info
1947
1948 static int snd_vt1724_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
1949 struct snd_ctl_elem_value *ucontrol)
1950 {
1951 ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
1952 return 0;
1953 }
1954
1955 static int snd_vt1724_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
1956 struct snd_ctl_elem_value *ucontrol)
1957 {
1958 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1959 int change = 0, nval;
1960
1961 nval = ucontrol->value.integer.value[0] ? 1 : 0;
1962 spin_lock_irq(&ice->reg_lock);
1963 change = PRO_RATE_LOCKED != nval;
1964 PRO_RATE_LOCKED = nval;
1965 spin_unlock_irq(&ice->reg_lock);
1966 return change;
1967 }
1968
1969 static const struct snd_kcontrol_new snd_vt1724_pro_rate_locking = {
1970 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1971 .name = "Multi Track Rate Locking",
1972 .info = snd_vt1724_pro_rate_locking_info,
1973 .get = snd_vt1724_pro_rate_locking_get,
1974 .put = snd_vt1724_pro_rate_locking_put
1975 };
1976
1977 #define snd_vt1724_pro_rate_reset_info snd_ctl_boolean_mono_info
1978
1979 static int snd_vt1724_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
1980 struct snd_ctl_elem_value *ucontrol)
1981 {
1982 ucontrol->value.integer.value[0] = PRO_RATE_RESET ? 1 : 0;
1983 return 0;
1984 }
1985
1986 static int snd_vt1724_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
1987 struct snd_ctl_elem_value *ucontrol)
1988 {
1989 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1990 int change = 0, nval;
1991
1992 nval = ucontrol->value.integer.value[0] ? 1 : 0;
1993 spin_lock_irq(&ice->reg_lock);
1994 change = PRO_RATE_RESET != nval;
1995 PRO_RATE_RESET = nval;
1996 spin_unlock_irq(&ice->reg_lock);
1997 return change;
1998 }
1999
2000 static const struct snd_kcontrol_new snd_vt1724_pro_rate_reset = {
2001 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2002 .name = "Multi Track Rate Reset",
2003 .info = snd_vt1724_pro_rate_reset_info,
2004 .get = snd_vt1724_pro_rate_reset_get,
2005 .put = snd_vt1724_pro_rate_reset_put
2006 };
2007
2008
2009 /*
2010 * routing
2011 */
2012 static int snd_vt1724_pro_route_info(struct snd_kcontrol *kcontrol,
2013 struct snd_ctl_elem_info *uinfo)
2014 {
2015 static const char * const texts[] = {
2016 "PCM Out", /* 0 */
2017 "H/W In 0", "H/W In 1", /* 1-2 */
2018 "IEC958 In L", "IEC958 In R", /* 3-4 */
2019 };
2020
2021 return snd_ctl_enum_info(uinfo, 1, 5, texts);
2022 }
2023
2024 static inline int analog_route_shift(int idx)
2025 {
2026 return (idx % 2) * 12 + ((idx / 2) * 3) + 8;
2027 }
2028
2029 static inline int digital_route_shift(int idx)
2030 {
2031 return idx * 3;
2032 }
2033
2034 int snd_ice1724_get_route_val(struct snd_ice1712 *ice, int shift)
2035 {
2036 unsigned long val;
2037 unsigned char eitem;
2038 static const unsigned char xlate[8] = {
2039 0, 255, 1, 2, 255, 255, 3, 4,
2040 };
2041
2042 val = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
2043 val >>= shift;
2044 val &= 7; /* we now have 3 bits per output */
2045 eitem = xlate[val];
2046 if (eitem == 255) {
2047 snd_BUG();
2048 return 0;
2049 }
2050 return eitem;
2051 }
2052
2053 int snd_ice1724_put_route_val(struct snd_ice1712 *ice, unsigned int val,
2054 int shift)
2055 {
2056 unsigned int old_val, nval;
2057 int change;
2058 static const unsigned char xroute[8] = {
2059 0, /* PCM */
2060 2, /* PSDIN0 Left */
2061 3, /* PSDIN0 Right */
2062 6, /* SPDIN Left */
2063 7, /* SPDIN Right */
2064 };
2065
2066 nval = xroute[val % 5];
2067 val = old_val = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
2068 val &= ~(0x07 << shift);
2069 val |= nval << shift;
2070 change = val != old_val;
2071 if (change)
2072 outl(val, ICEMT1724(ice, ROUTE_PLAYBACK));
2073 return change;
2074 }
2075
2076 static int snd_vt1724_pro_route_analog_get(struct snd_kcontrol *kcontrol,
2077 struct snd_ctl_elem_value *ucontrol)
2078 {
2079 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2080 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2081 ucontrol->value.enumerated.item[0] =
2082 snd_ice1724_get_route_val(ice, analog_route_shift(idx));
2083 return 0;
2084 }
2085
2086 static int snd_vt1724_pro_route_analog_put(struct snd_kcontrol *kcontrol,
2087 struct snd_ctl_elem_value *ucontrol)
2088 {
2089 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2090 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2091 return snd_ice1724_put_route_val(ice,
2092 ucontrol->value.enumerated.item[0],
2093 analog_route_shift(idx));
2094 }
2095
2096 static int snd_vt1724_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
2097 struct snd_ctl_elem_value *ucontrol)
2098 {
2099 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2100 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2101 ucontrol->value.enumerated.item[0] =
2102 snd_ice1724_get_route_val(ice, digital_route_shift(idx));
2103 return 0;
2104 }
2105
2106 static int snd_vt1724_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
2107 struct snd_ctl_elem_value *ucontrol)
2108 {
2109 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2110 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2111 return snd_ice1724_put_route_val(ice,
2112 ucontrol->value.enumerated.item[0],
2113 digital_route_shift(idx));
2114 }
2115
2116 static const struct snd_kcontrol_new snd_vt1724_mixer_pro_analog_route =
2117 {
2118 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2119 .name = "H/W Playback Route",
2120 .info = snd_vt1724_pro_route_info,
2121 .get = snd_vt1724_pro_route_analog_get,
2122 .put = snd_vt1724_pro_route_analog_put,
2123 };
2124
2125 static const struct snd_kcontrol_new snd_vt1724_mixer_pro_spdif_route = {
2126 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2127 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, NONE) "Route",
2128 .info = snd_vt1724_pro_route_info,
2129 .get = snd_vt1724_pro_route_spdif_get,
2130 .put = snd_vt1724_pro_route_spdif_put,
2131 .count = 2,
2132 };
2133
2134
2135 static int snd_vt1724_pro_peak_info(struct snd_kcontrol *kcontrol,
2136 struct snd_ctl_elem_info *uinfo)
2137 {
2138 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2139 uinfo->count = 22; /* FIXME: for compatibility with ice1712... */
2140 uinfo->value.integer.min = 0;
2141 uinfo->value.integer.max = 255;
2142 return 0;
2143 }
2144
2145 static int snd_vt1724_pro_peak_get(struct snd_kcontrol *kcontrol,
2146 struct snd_ctl_elem_value *ucontrol)
2147 {
2148 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2149 int idx;
2150
2151 spin_lock_irq(&ice->reg_lock);
2152 for (idx = 0; idx < 22; idx++) {
2153 outb(idx, ICEMT1724(ice, MONITOR_PEAKINDEX));
2154 ucontrol->value.integer.value[idx] =
2155 inb(ICEMT1724(ice, MONITOR_PEAKDATA));
2156 }
2157 spin_unlock_irq(&ice->reg_lock);
2158 return 0;
2159 }
2160
2161 static const struct snd_kcontrol_new snd_vt1724_mixer_pro_peak = {
2162 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2163 .name = "Multi Track Peak",
2164 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
2165 .info = snd_vt1724_pro_peak_info,
2166 .get = snd_vt1724_pro_peak_get
2167 };
2168
2169 /*
2170 *
2171 */
2172
2173 static const struct snd_ice1712_card_info no_matched;
2174
2175
2176 /*
2177 ooAoo cards with no controls
2178 */
2179 static const unsigned char ooaoo_sq210_eeprom[] = {
2180 [ICE_EEP2_SYSCONF] = 0x4c, /* 49MHz crystal, no mpu401, no ADC,
2181 1xDACs */
2182 [ICE_EEP2_ACLINK] = 0x80, /* I2S */
2183 [ICE_EEP2_I2S] = 0x78, /* no volume, 96k, 24bit, 192k */
2184 [ICE_EEP2_SPDIF] = 0xc1, /* out-en, out-int, out-ext */
2185 [ICE_EEP2_GPIO_DIR] = 0x00, /* no GPIOs are used */
2186 [ICE_EEP2_GPIO_DIR1] = 0x00,
2187 [ICE_EEP2_GPIO_DIR2] = 0x00,
2188 [ICE_EEP2_GPIO_MASK] = 0xff,
2189 [ICE_EEP2_GPIO_MASK1] = 0xff,
2190 [ICE_EEP2_GPIO_MASK2] = 0xff,
2191
2192 [ICE_EEP2_GPIO_STATE] = 0x00, /* inputs */
2193 [ICE_EEP2_GPIO_STATE1] = 0x00, /* all 1, but GPIO_CPLD_RW
2194 and GPIO15 always zero */
2195 [ICE_EEP2_GPIO_STATE2] = 0x00, /* inputs */
2196 };
2197
2198
2199 static const struct snd_ice1712_card_info snd_vt1724_ooaoo_cards[] = {
2200 {
2201 .name = "ooAoo SQ210a",
2202 .model = "sq210a",
2203 .eeprom_size = sizeof(ooaoo_sq210_eeprom),
2204 .eeprom_data = ooaoo_sq210_eeprom,
2205 },
2206 { } /* terminator */
2207 };
2208
2209 static const struct snd_ice1712_card_info *card_tables[] = {
2210 snd_vt1724_revo_cards,
2211 snd_vt1724_amp_cards,
2212 snd_vt1724_aureon_cards,
2213 snd_vt1720_mobo_cards,
2214 snd_vt1720_pontis_cards,
2215 snd_vt1724_prodigy_hifi_cards,
2216 snd_vt1724_prodigy192_cards,
2217 snd_vt1724_juli_cards,
2218 snd_vt1724_maya44_cards,
2219 snd_vt1724_phase_cards,
2220 snd_vt1724_wtm_cards,
2221 snd_vt1724_se_cards,
2222 snd_vt1724_qtet_cards,
2223 snd_vt1724_ooaoo_cards,
2224 snd_vt1724_psc724_cards,
2225 NULL,
2226 };
2227
2228
2229 /*
2230 */
2231
2232 static void wait_i2c_busy(struct snd_ice1712 *ice)
2233 {
2234 int t = 0x10000;
2235 while ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_BUSY) && t--)
2236 ;
2237 if (t == -1)
2238 dev_err(ice->card->dev, "i2c busy timeout\n");
2239 }
2240
2241 unsigned char snd_vt1724_read_i2c(struct snd_ice1712 *ice,
2242 unsigned char dev, unsigned char addr)
2243 {
2244 unsigned char val;
2245
2246 mutex_lock(&ice->i2c_mutex);
2247 wait_i2c_busy(ice);
2248 outb(addr, ICEREG1724(ice, I2C_BYTE_ADDR));
2249 outb(dev & ~VT1724_I2C_WRITE, ICEREG1724(ice, I2C_DEV_ADDR));
2250 wait_i2c_busy(ice);
2251 val = inb(ICEREG1724(ice, I2C_DATA));
2252 mutex_unlock(&ice->i2c_mutex);
2253 /*
2254 dev_dbg(ice->card->dev, "i2c_read: [0x%x,0x%x] = 0x%x\n", dev, addr, val);
2255 */
2256 return val;
2257 }
2258
2259 void snd_vt1724_write_i2c(struct snd_ice1712 *ice,
2260 unsigned char dev, unsigned char addr, unsigned char data)
2261 {
2262 mutex_lock(&ice->i2c_mutex);
2263 wait_i2c_busy(ice);
2264 /*
2265 dev_dbg(ice->card->dev, "i2c_write: [0x%x,0x%x] = 0x%x\n", dev, addr, data);
2266 */
2267 outb(addr, ICEREG1724(ice, I2C_BYTE_ADDR));
2268 outb(data, ICEREG1724(ice, I2C_DATA));
2269 outb(dev | VT1724_I2C_WRITE, ICEREG1724(ice, I2C_DEV_ADDR));
2270 wait_i2c_busy(ice);
2271 mutex_unlock(&ice->i2c_mutex);
2272 }
2273
2274 static int snd_vt1724_read_eeprom(struct snd_ice1712 *ice,
2275 const char *modelname)
2276 {
2277 const int dev = 0xa0; /* EEPROM device address */
2278 unsigned int i, size;
2279 const struct snd_ice1712_card_info * const *tbl, *c;
2280
2281 if (!modelname || !*modelname) {
2282 ice->eeprom.subvendor = 0;
2283 if ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_EEPROM) != 0)
2284 ice->eeprom.subvendor =
2285 (snd_vt1724_read_i2c(ice, dev, 0x00) << 0) |
2286 (snd_vt1724_read_i2c(ice, dev, 0x01) << 8) |
2287 (snd_vt1724_read_i2c(ice, dev, 0x02) << 16) |
2288 (snd_vt1724_read_i2c(ice, dev, 0x03) << 24);
2289 if (ice->eeprom.subvendor == 0 ||
2290 ice->eeprom.subvendor == (unsigned int)-1) {
2291 /* invalid subvendor from EEPROM, try the PCI
2292 * subststem ID instead
2293 */
2294 u16 vendor, device;
2295 pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID,
2296 &vendor);
2297 pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
2298 ice->eeprom.subvendor =
2299 ((unsigned int)swab16(vendor) << 16) | swab16(device);
2300 if (ice->eeprom.subvendor == 0 ||
2301 ice->eeprom.subvendor == (unsigned int)-1) {
2302 dev_err(ice->card->dev,
2303 "No valid ID is found\n");
2304 return -ENXIO;
2305 }
2306 }
2307 }
2308 for (tbl = card_tables; *tbl; tbl++) {
2309 for (c = *tbl; c->name; c++) {
2310 if (modelname && c->model &&
2311 !strcmp(modelname, c->model)) {
2312 dev_info(ice->card->dev,
2313 "Using board model %s\n",
2314 c->name);
2315 ice->eeprom.subvendor = c->subvendor;
2316 } else if (c->subvendor != ice->eeprom.subvendor)
2317 continue;
2318 ice->card_info = c;
2319 if (!c->eeprom_size || !c->eeprom_data)
2320 goto found;
2321 /* if the EEPROM is given by the driver, use it */
2322 dev_dbg(ice->card->dev, "using the defined eeprom..\n");
2323 ice->eeprom.version = 2;
2324 ice->eeprom.size = c->eeprom_size + 6;
2325 memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
2326 goto read_skipped;
2327 }
2328 }
2329 dev_warn(ice->card->dev, "No matching model found for ID 0x%x\n",
2330 ice->eeprom.subvendor);
2331 #ifdef CONFIG_PM_SLEEP
2332 /* assume AC97-only card which can suspend without additional code */
2333 ice->pm_suspend_enabled = 1;
2334 #endif
2335
2336 found:
2337 ice->eeprom.size = snd_vt1724_read_i2c(ice, dev, 0x04);
2338 if (ice->eeprom.size < 6)
2339 ice->eeprom.size = 32;
2340 else if (ice->eeprom.size > 32) {
2341 dev_err(ice->card->dev, "Invalid EEPROM (size = %i)\n",
2342 ice->eeprom.size);
2343 return -EIO;
2344 }
2345 ice->eeprom.version = snd_vt1724_read_i2c(ice, dev, 0x05);
2346 if (ice->eeprom.version != 1 && ice->eeprom.version != 2)
2347 dev_warn(ice->card->dev, "Invalid EEPROM version %i\n",
2348 ice->eeprom.version);
2349 size = ice->eeprom.size - 6;
2350 for (i = 0; i < size; i++)
2351 ice->eeprom.data[i] = snd_vt1724_read_i2c(ice, dev, i + 6);
2352
2353 read_skipped:
2354 ice->eeprom.gpiomask = eeprom_triple(ice, ICE_EEP2_GPIO_MASK);
2355 ice->eeprom.gpiostate = eeprom_triple(ice, ICE_EEP2_GPIO_STATE);
2356 ice->eeprom.gpiodir = eeprom_triple(ice, ICE_EEP2_GPIO_DIR);
2357
2358 return 0;
2359 }
2360
2361
2362
2363 static void snd_vt1724_chip_reset(struct snd_ice1712 *ice)
2364 {
2365 outb(VT1724_RESET , ICEREG1724(ice, CONTROL));
2366 inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
2367 msleep(10);
2368 outb(0, ICEREG1724(ice, CONTROL));
2369 inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
2370 msleep(10);
2371 }
2372
2373 static int snd_vt1724_chip_init(struct snd_ice1712 *ice)
2374 {
2375 outb(ice->eeprom.data[ICE_EEP2_SYSCONF], ICEREG1724(ice, SYS_CFG));
2376 outb(ice->eeprom.data[ICE_EEP2_ACLINK], ICEREG1724(ice, AC97_CFG));
2377 outb(ice->eeprom.data[ICE_EEP2_I2S], ICEREG1724(ice, I2S_FEATURES));
2378 outb(ice->eeprom.data[ICE_EEP2_SPDIF], ICEREG1724(ice, SPDIF_CFG));
2379
2380 ice->gpio.write_mask = ice->eeprom.gpiomask;
2381 ice->gpio.direction = ice->eeprom.gpiodir;
2382 snd_vt1724_set_gpio_mask(ice, ice->eeprom.gpiomask);
2383 snd_vt1724_set_gpio_dir(ice, ice->eeprom.gpiodir);
2384 snd_vt1724_set_gpio_data(ice, ice->eeprom.gpiostate);
2385
2386 outb(0, ICEREG1724(ice, POWERDOWN));
2387
2388 /* MPU_RX and TX irq masks are cleared later dynamically */
2389 outb(VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX , ICEREG1724(ice, IRQMASK));
2390
2391 /* don't handle FIFO overrun/underruns (just yet),
2392 * since they cause machine lockups
2393 */
2394 outb(VT1724_MULTI_FIFO_ERR, ICEMT1724(ice, DMA_INT_MASK));
2395
2396 return 0;
2397 }
2398
2399 static int snd_vt1724_spdif_build_controls(struct snd_ice1712 *ice)
2400 {
2401 int err;
2402 struct snd_kcontrol *kctl;
2403
2404 if (snd_BUG_ON(!ice->pcm))
2405 return -EIO;
2406
2407 if (!ice->own_routing) {
2408 err = snd_ctl_add(ice->card,
2409 snd_ctl_new1(&snd_vt1724_mixer_pro_spdif_route, ice));
2410 if (err < 0)
2411 return err;
2412 }
2413
2414 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_spdif_switch, ice));
2415 if (err < 0)
2416 return err;
2417
2418 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_default, ice));
2419 if (err < 0)
2420 return err;
2421 kctl->id.device = ice->pcm->device;
2422 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_maskc, ice));
2423 if (err < 0)
2424 return err;
2425 kctl->id.device = ice->pcm->device;
2426 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_maskp, ice));
2427 if (err < 0)
2428 return err;
2429 kctl->id.device = ice->pcm->device;
2430 #if 0 /* use default only */
2431 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_stream, ice));
2432 if (err < 0)
2433 return err;
2434 kctl->id.device = ice->pcm->device;
2435 ice->spdif.stream_ctl = kctl;
2436 #endif
2437 return 0;
2438 }
2439
2440
2441 static int snd_vt1724_build_controls(struct snd_ice1712 *ice)
2442 {
2443 int err;
2444
2445 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_eeprom, ice));
2446 if (err < 0)
2447 return err;
2448 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_internal_clock, ice));
2449 if (err < 0)
2450 return err;
2451
2452 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_rate_locking, ice));
2453 if (err < 0)
2454 return err;
2455 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_rate_reset, ice));
2456 if (err < 0)
2457 return err;
2458
2459 if (!ice->own_routing && ice->num_total_dacs > 0) {
2460 struct snd_kcontrol_new tmp = snd_vt1724_mixer_pro_analog_route;
2461 tmp.count = ice->num_total_dacs;
2462 if (ice->vt1720 && tmp.count > 2)
2463 tmp.count = 2;
2464 err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
2465 if (err < 0)
2466 return err;
2467 }
2468
2469 return snd_ctl_add(ice->card,
2470 snd_ctl_new1(&snd_vt1724_mixer_pro_peak, ice));
2471 }
2472
2473 static int snd_vt1724_free(struct snd_ice1712 *ice)
2474 {
2475 if (!ice->port)
2476 goto __hw_end;
2477 /* mask all interrupts */
2478 outb(0xff, ICEMT1724(ice, DMA_INT_MASK));
2479 outb(0xff, ICEREG1724(ice, IRQMASK));
2480 /* --- */
2481 __hw_end:
2482 if (ice->irq >= 0)
2483 free_irq(ice->irq, ice);
2484 pci_release_regions(ice->pci);
2485 snd_ice1712_akm4xxx_free(ice);
2486 pci_disable_device(ice->pci);
2487 kfree(ice->spec);
2488 kfree(ice);
2489 return 0;
2490 }
2491
2492 static int snd_vt1724_dev_free(struct snd_device *device)
2493 {
2494 struct snd_ice1712 *ice = device->device_data;
2495 return snd_vt1724_free(ice);
2496 }
2497
2498 static int snd_vt1724_create(struct snd_card *card,
2499 struct pci_dev *pci,
2500 const char *modelname,
2501 struct snd_ice1712 **r_ice1712)
2502 {
2503 struct snd_ice1712 *ice;
2504 int err;
2505 static const struct snd_device_ops ops = {
2506 .dev_free = snd_vt1724_dev_free,
2507 };
2508
2509 *r_ice1712 = NULL;
2510
2511 /* enable PCI device */
2512 err = pci_enable_device(pci);
2513 if (err < 0)
2514 return err;
2515
2516 ice = kzalloc(sizeof(*ice), GFP_KERNEL);
2517 if (ice == NULL) {
2518 pci_disable_device(pci);
2519 return -ENOMEM;
2520 }
2521 ice->vt1724 = 1;
2522 spin_lock_init(&ice->reg_lock);
2523 mutex_init(&ice->gpio_mutex);
2524 mutex_init(&ice->open_mutex);
2525 mutex_init(&ice->i2c_mutex);
2526 ice->gpio.set_mask = snd_vt1724_set_gpio_mask;
2527 ice->gpio.get_mask = snd_vt1724_get_gpio_mask;
2528 ice->gpio.set_dir = snd_vt1724_set_gpio_dir;
2529 ice->gpio.get_dir = snd_vt1724_get_gpio_dir;
2530 ice->gpio.set_data = snd_vt1724_set_gpio_data;
2531 ice->gpio.get_data = snd_vt1724_get_gpio_data;
2532 ice->card = card;
2533 ice->pci = pci;
2534 ice->irq = -1;
2535 pci_set_master(pci);
2536 snd_vt1724_proc_init(ice);
2537
2538 card->private_data = ice;
2539
2540 err = pci_request_regions(pci, "ICE1724");
2541 if (err < 0) {
2542 kfree(ice);
2543 pci_disable_device(pci);
2544 return err;
2545 }
2546 ice->port = pci_resource_start(pci, 0);
2547 ice->profi_port = pci_resource_start(pci, 1);
2548
2549 if (request_irq(pci->irq, snd_vt1724_interrupt,
2550 IRQF_SHARED, KBUILD_MODNAME, ice)) {
2551 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2552 snd_vt1724_free(ice);
2553 return -EIO;
2554 }
2555
2556 ice->irq = pci->irq;
2557 card->sync_irq = ice->irq;
2558
2559 snd_vt1724_chip_reset(ice);
2560 if (snd_vt1724_read_eeprom(ice, modelname) < 0) {
2561 snd_vt1724_free(ice);
2562 return -EIO;
2563 }
2564 if (snd_vt1724_chip_init(ice) < 0) {
2565 snd_vt1724_free(ice);
2566 return -EIO;
2567 }
2568
2569 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops);
2570 if (err < 0) {
2571 snd_vt1724_free(ice);
2572 return err;
2573 }
2574
2575 *r_ice1712 = ice;
2576 return 0;
2577 }
2578
2579
2580 /*
2581 *
2582 * Registration
2583 *
2584 */
2585
2586 static int snd_vt1724_probe(struct pci_dev *pci,
2587 const struct pci_device_id *pci_id)
2588 {
2589 static int dev;
2590 struct snd_card *card;
2591 struct snd_ice1712 *ice;
2592 int pcm_dev = 0, err;
2593 const struct snd_ice1712_card_info * const *tbl, *c;
2594
2595 if (dev >= SNDRV_CARDS)
2596 return -ENODEV;
2597 if (!enable[dev]) {
2598 dev++;
2599 return -ENOENT;
2600 }
2601
2602 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2603 0, &card);
2604 if (err < 0)
2605 return err;
2606
2607 strcpy(card->driver, "ICE1724");
2608 strcpy(card->shortname, "ICEnsemble ICE1724");
2609
2610 err = snd_vt1724_create(card, pci, model[dev], &ice);
2611 if (err < 0) {
2612 snd_card_free(card);
2613 return err;
2614 }
2615
2616 /* field init before calling chip_init */
2617 ice->ext_clock_count = 0;
2618
2619 for (tbl = card_tables; *tbl; tbl++) {
2620 for (c = *tbl; c->name; c++) {
2621 if ((model[dev] && c->model &&
2622 !strcmp(model[dev], c->model)) ||
2623 (c->subvendor == ice->eeprom.subvendor)) {
2624 strcpy(card->shortname, c->name);
2625 if (c->driver) /* specific driver? */
2626 strcpy(card->driver, c->driver);
2627 if (c->chip_init) {
2628 err = c->chip_init(ice);
2629 if (err < 0) {
2630 snd_card_free(card);
2631 return err;
2632 }
2633 }
2634 goto __found;
2635 }
2636 }
2637 }
2638 c = &no_matched;
2639 __found:
2640 /*
2641 * VT1724 has separate DMAs for the analog and the SPDIF streams while
2642 * ICE1712 has only one for both (mixed up).
2643 *
2644 * Confusingly the analog PCM is named "professional" here because it
2645 * was called so in ice1712 driver, and vt1724 driver is derived from
2646 * ice1712 driver.
2647 */
2648 ice->pro_rate_default = PRO_RATE_DEFAULT;
2649 if (!ice->is_spdif_master)
2650 ice->is_spdif_master = stdclock_is_spdif_master;
2651 if (!ice->get_rate)
2652 ice->get_rate = stdclock_get_rate;
2653 if (!ice->set_rate)
2654 ice->set_rate = stdclock_set_rate;
2655 if (!ice->set_mclk)
2656 ice->set_mclk = stdclock_set_mclk;
2657 if (!ice->set_spdif_clock)
2658 ice->set_spdif_clock = stdclock_set_spdif_clock;
2659 if (!ice->get_spdif_master_type)
2660 ice->get_spdif_master_type = stdclock_get_spdif_master_type;
2661 if (!ice->ext_clock_names)
2662 ice->ext_clock_names = ext_clock_names;
2663 if (!ice->ext_clock_count)
2664 ice->ext_clock_count = ARRAY_SIZE(ext_clock_names);
2665
2666 if (!ice->hw_rates)
2667 set_std_hw_rates(ice);
2668
2669 err = snd_vt1724_pcm_profi(ice, pcm_dev++);
2670 if (err < 0) {
2671 snd_card_free(card);
2672 return err;
2673 }
2674
2675 err = snd_vt1724_pcm_spdif(ice, pcm_dev++);
2676 if (err < 0) {
2677 snd_card_free(card);
2678 return err;
2679 }
2680
2681 err = snd_vt1724_pcm_indep(ice, pcm_dev++);
2682 if (err < 0) {
2683 snd_card_free(card);
2684 return err;
2685 }
2686
2687 err = snd_vt1724_ac97_mixer(ice);
2688 if (err < 0) {
2689 snd_card_free(card);
2690 return err;
2691 }
2692
2693 err = snd_vt1724_build_controls(ice);
2694 if (err < 0) {
2695 snd_card_free(card);
2696 return err;
2697 }
2698
2699 if (ice->pcm && ice->has_spdif) { /* has SPDIF I/O */
2700 err = snd_vt1724_spdif_build_controls(ice);
2701 if (err < 0) {
2702 snd_card_free(card);
2703 return err;
2704 }
2705 }
2706
2707 if (c->build_controls) {
2708 err = c->build_controls(ice);
2709 if (err < 0) {
2710 snd_card_free(card);
2711 return err;
2712 }
2713 }
2714
2715 if (!c->no_mpu401) {
2716 if (ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_MPU401) {
2717 struct snd_rawmidi *rmidi;
2718
2719 err = snd_rawmidi_new(card, "MIDI", 0, 1, 1, &rmidi);
2720 if (err < 0) {
2721 snd_card_free(card);
2722 return err;
2723 }
2724 ice->rmidi[0] = rmidi;
2725 rmidi->private_data = ice;
2726 strcpy(rmidi->name, "ICE1724 MIDI");
2727 rmidi->info_flags = SNDRV_RAWMIDI_INFO_OUTPUT |
2728 SNDRV_RAWMIDI_INFO_INPUT |
2729 SNDRV_RAWMIDI_INFO_DUPLEX;
2730 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT,
2731 &vt1724_midi_output_ops);
2732 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT,
2733 &vt1724_midi_input_ops);
2734
2735 /* set watermarks */
2736 outb(VT1724_MPU_RX_FIFO | 0x1,
2737 ICEREG1724(ice, MPU_FIFO_WM));
2738 outb(0x1, ICEREG1724(ice, MPU_FIFO_WM));
2739 /* set UART mode */
2740 outb(VT1724_MPU_UART, ICEREG1724(ice, MPU_CTRL));
2741 }
2742 }
2743
2744 sprintf(card->longname, "%s at 0x%lx, irq %i",
2745 card->shortname, ice->port, ice->irq);
2746
2747 err = snd_card_register(card);
2748 if (err < 0) {
2749 snd_card_free(card);
2750 return err;
2751 }
2752 pci_set_drvdata(pci, card);
2753 dev++;
2754 return 0;
2755 }
2756
2757 static void snd_vt1724_remove(struct pci_dev *pci)
2758 {
2759 struct snd_card *card = pci_get_drvdata(pci);
2760 struct snd_ice1712 *ice = card->private_data;
2761
2762 if (ice->card_info && ice->card_info->chip_exit)
2763 ice->card_info->chip_exit(ice);
2764 snd_card_free(card);
2765 }
2766
2767 #ifdef CONFIG_PM_SLEEP
2768 static int snd_vt1724_suspend(struct device *dev)
2769 {
2770 struct snd_card *card = dev_get_drvdata(dev);
2771 struct snd_ice1712 *ice = card->private_data;
2772
2773 if (!ice->pm_suspend_enabled)
2774 return 0;
2775
2776 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2777
2778 snd_ac97_suspend(ice->ac97);
2779
2780 spin_lock_irq(&ice->reg_lock);
2781 ice->pm_saved_is_spdif_master = ice->is_spdif_master(ice);
2782 ice->pm_saved_spdif_ctrl = inw(ICEMT1724(ice, SPDIF_CTRL));
2783 ice->pm_saved_spdif_cfg = inb(ICEREG1724(ice, SPDIF_CFG));
2784 ice->pm_saved_route = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
2785 spin_unlock_irq(&ice->reg_lock);
2786
2787 if (ice->pm_suspend)
2788 ice->pm_suspend(ice);
2789 return 0;
2790 }
2791
2792 static int snd_vt1724_resume(struct device *dev)
2793 {
2794 struct snd_card *card = dev_get_drvdata(dev);
2795 struct snd_ice1712 *ice = card->private_data;
2796
2797 if (!ice->pm_suspend_enabled)
2798 return 0;
2799
2800 snd_vt1724_chip_reset(ice);
2801
2802 if (snd_vt1724_chip_init(ice) < 0) {
2803 snd_card_disconnect(card);
2804 return -EIO;
2805 }
2806
2807 if (ice->pm_resume)
2808 ice->pm_resume(ice);
2809
2810 if (ice->pm_saved_is_spdif_master) {
2811 /* switching to external clock via SPDIF */
2812 ice->set_spdif_clock(ice, 0);
2813 } else {
2814 /* internal on-card clock */
2815 int rate;
2816 if (ice->cur_rate)
2817 rate = ice->cur_rate;
2818 else
2819 rate = ice->pro_rate_default;
2820 snd_vt1724_set_pro_rate(ice, rate, 1);
2821 }
2822
2823 update_spdif_bits(ice, ice->pm_saved_spdif_ctrl);
2824
2825 outb(ice->pm_saved_spdif_cfg, ICEREG1724(ice, SPDIF_CFG));
2826 outl(ice->pm_saved_route, ICEMT1724(ice, ROUTE_PLAYBACK));
2827
2828 snd_ac97_resume(ice->ac97);
2829
2830 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2831 return 0;
2832 }
2833
2834 static SIMPLE_DEV_PM_OPS(snd_vt1724_pm, snd_vt1724_suspend, snd_vt1724_resume);
2835 #define SND_VT1724_PM_OPS &snd_vt1724_pm
2836 #else
2837 #define SND_VT1724_PM_OPS NULL
2838 #endif /* CONFIG_PM_SLEEP */
2839
2840 static struct pci_driver vt1724_driver = {
2841 .name = KBUILD_MODNAME,
2842 .id_table = snd_vt1724_ids,
2843 .probe = snd_vt1724_probe,
2844 .remove = snd_vt1724_remove,
2845 .driver = {
2846 .pm = SND_VT1724_PM_OPS,
2847 },
2848 };
2849
2850 module_pci_driver(vt1724_driver);
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