sound/pci/ice1712/quartet.c

   1 /*
   2  *   ALSA driver for ICEnsemble VT1724 (Envy24HT)
   3  *
   4  *   Lowlevel functions for Infrasonic Quartet
   5  *
   6  *      Copyright (c) 2009 Pavel Hofman <pavel.hofman@ivitera.com>
   7  *
   8  *
   9  *   This program is free software; you can redistribute it and/or modify
  10  *   it under the terms of the GNU General Public License as published by
  11  *   the Free Software Foundation; either version 2 of the License, or
  12  *   (at your option) any later version.
  13  *
  14  *   This program is distributed in the hope that it will be useful,
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *   GNU General Public License for more details.
  18  *
  19  *   You should have received a copy of the GNU General Public License
  20  *   along with this program; if not, write to the Free Software
  21  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  *
  23  */
  24
  25 #include <linux/delay.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/init.h>
  28 #include <linux/slab.h>
  29 #include <linux/string.h>
  30 #include <sound/core.h>
  31 #include <sound/tlv.h>
  32 #include <sound/info.h>
  33
  34 #include "ice1712.h"
  35 #include "envy24ht.h"
  36 #include <sound/ak4113.h>
  37 #include "quartet.h"
  38
  39 struct qtet_spec {
  40         struct ak4113 *ak4113;
  41         unsigned int scr;       /* system control register */
  42         unsigned int mcr;       /* monitoring control register */
  43         unsigned int cpld;      /* cpld register */
  44 };
  45
  46 struct qtet_kcontrol_private {
  47         unsigned int bit;
  48         void (*set_register)(struct snd_ice1712 *ice, unsigned int val);
  49         unsigned int (*get_register)(struct snd_ice1712 *ice);
  50         const char * const texts[2];
  51 };
  52
  53 enum {
  54         IN12_SEL = 0,
  55         IN34_SEL,
  56         AIN34_SEL,
  57         COAX_OUT,
  58         IN12_MON12,
  59         IN12_MON34,
  60         IN34_MON12,
  61         IN34_MON34,
  62         OUT12_MON34,
  63         OUT34_MON12,
  64 };
  65
  66 static const char * const ext_clock_names[3] = {"IEC958 In", "Word Clock 1xFS",
  67         "Word Clock 256xFS"};
  68
  69 /* chip address on I2C bus */
  70 #define AK4113_ADDR             0x26    /* S/PDIF receiver */
  71
  72 /* chip address on SPI bus */
  73 #define AK4620_ADDR             0x02    /* ADC/DAC */
  74
  75
  76 /*
  77  * GPIO pins
  78  */
  79
  80 /* GPIO0 - O - DATA0, def. 0 */
  81 #define GPIO_D0                 (1<<0)
  82 /* GPIO1 - I/O - DATA1, Jack Detect Input0 (0:present, 1:missing), def. 1 */
  83 #define GPIO_D1_JACKDTC0        (1<<1)
  84 /* GPIO2 - I/O - DATA2, Jack Detect Input1 (0:present, 1:missing), def. 1 */
  85 #define GPIO_D2_JACKDTC1        (1<<2)
  86 /* GPIO3 - I/O - DATA3, def. 1 */
  87 #define GPIO_D3                 (1<<3)
  88 /* GPIO4 - I/O - DATA4, SPI CDTO, def. 1 */
  89 #define GPIO_D4_SPI_CDTO        (1<<4)
  90 /* GPIO5 - I/O - DATA5, SPI CCLK, def. 1 */
  91 #define GPIO_D5_SPI_CCLK        (1<<5)
  92 /* GPIO6 - I/O - DATA6, Cable Detect Input (0:detected, 1:not detected */
  93 #define GPIO_D6_CD              (1<<6)
  94 /* GPIO7 - I/O - DATA7, Device Detect Input (0:detected, 1:not detected */
  95 #define GPIO_D7_DD              (1<<7)
  96 /* GPIO8 - O - CPLD Chip Select, def. 1 */
  97 #define GPIO_CPLD_CSN           (1<<8)
  98 /* GPIO9 - O - CPLD register read/write (0:write, 1:read), def. 0 */
  99 #define GPIO_CPLD_RW            (1<<9)
 100 /* GPIO10 - O - SPI Chip Select for CODEC#0, def. 1 */
 101 #define GPIO_SPI_CSN0           (1<<10)
 102 /* GPIO11 - O - SPI Chip Select for CODEC#1, def. 1 */
 103 #define GPIO_SPI_CSN1           (1<<11)
 104 /* GPIO12 - O - Ex. Register Output Enable (0:enable, 1:disable), def. 1,
 105  * init 0 */
 106 #define GPIO_EX_GPIOE           (1<<12)
 107 /* GPIO13 - O - Ex. Register0 Chip Select for System Control Register,
 108  * def. 1 */
 109 #define GPIO_SCR                (1<<13)
 110 /* GPIO14 - O - Ex. Register1 Chip Select for Monitor Control Register,
 111  * def. 1 */
 112 #define GPIO_MCR                (1<<14)
 113
 114 #define GPIO_SPI_ALL            (GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK |\
 115                 GPIO_SPI_CSN0 | GPIO_SPI_CSN1)
 116
 117 #define GPIO_DATA_MASK          (GPIO_D0 | GPIO_D1_JACKDTC0 | \
 118                 GPIO_D2_JACKDTC1 | GPIO_D3 | \
 119                 GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK | \
 120                 GPIO_D6_CD | GPIO_D7_DD)
 121
 122 /* System Control Register GPIO_SCR data bits */
 123 /* Mic/Line select relay (0:line, 1:mic) */
 124 #define SCR_RELAY               GPIO_D0
 125 /* Phantom power drive control (0:5V, 1:48V) */
 126 #define SCR_PHP_V               GPIO_D1_JACKDTC0
 127 /* H/W mute control (0:Normal, 1:Mute) */
 128 #define SCR_MUTE                GPIO_D2_JACKDTC1
 129 /* Phantom power control (0:Phantom on, 1:off) */
 130 #define SCR_PHP                 GPIO_D3
 131 /* Analog input 1/2 Source Select */
 132 #define SCR_AIN12_SEL0          GPIO_D4_SPI_CDTO
 133 #define SCR_AIN12_SEL1          GPIO_D5_SPI_CCLK
 134 /* Analog input 3/4 Source Select (0:line, 1:hi-z) */
 135 #define SCR_AIN34_SEL           GPIO_D6_CD
 136 /* Codec Power Down (0:power down, 1:normal) */
 137 #define SCR_CODEC_PDN           GPIO_D7_DD
 138
 139 #define SCR_AIN12_LINE          (0)
 140 #define SCR_AIN12_MIC           (SCR_AIN12_SEL0)
 141 #define SCR_AIN12_LOWCUT        (SCR_AIN12_SEL1 | SCR_AIN12_SEL0)
 142
 143 /* Monitor Control Register GPIO_MCR data bits */
 144 /* Input 1/2 to Monitor 1/2 (0:off, 1:on) */
 145 #define MCR_IN12_MON12          GPIO_D0
 146 /* Input 1/2 to Monitor 3/4 (0:off, 1:on) */
 147 #define MCR_IN12_MON34          GPIO_D1_JACKDTC0
 148 /* Input 3/4 to Monitor 1/2 (0:off, 1:on) */
 149 #define MCR_IN34_MON12          GPIO_D2_JACKDTC1
 150 /* Input 3/4 to Monitor 3/4 (0:off, 1:on) */
 151 #define MCR_IN34_MON34          GPIO_D3
 152 /* Output to Monitor 1/2 (0:off, 1:on) */
 153 #define MCR_OUT34_MON12         GPIO_D4_SPI_CDTO
 154 /* Output to Monitor 3/4 (0:off, 1:on) */
 155 #define MCR_OUT12_MON34         GPIO_D5_SPI_CCLK
 156
 157 /* CPLD Register DATA bits */
 158 /* Clock Rate Select */
 159 #define CPLD_CKS0               GPIO_D0
 160 #define CPLD_CKS1               GPIO_D1_JACKDTC0
 161 #define CPLD_CKS2               GPIO_D2_JACKDTC1
 162 /* Sync Source Select (0:Internal, 1:External) */
 163 #define CPLD_SYNC_SEL           GPIO_D3
 164 /* Word Clock FS Select (0:FS, 1:256FS) */
 165 #define CPLD_WORD_SEL           GPIO_D4_SPI_CDTO
 166 /* Coaxial Output Source (IS-Link) (0:SPDIF, 1:I2S) */
 167 #define CPLD_COAX_OUT           GPIO_D5_SPI_CCLK
 168 /* Input 1/2 Source Select (0:Analog12, 1:An34) */
 169 #define CPLD_IN12_SEL           GPIO_D6_CD
 170 /* Input 3/4 Source Select (0:Analog34, 1:Digital In) */
 171 #define CPLD_IN34_SEL           GPIO_D7_DD
 172
 173 /* internal clock (CPLD_SYNC_SEL = 0) options */
 174 #define CPLD_CKS_44100HZ        (0)
 175 #define CPLD_CKS_48000HZ        (CPLD_CKS0)
 176 #define CPLD_CKS_88200HZ        (CPLD_CKS1)
 177 #define CPLD_CKS_96000HZ        (CPLD_CKS1 | CPLD_CKS0)
 178 #define CPLD_CKS_176400HZ       (CPLD_CKS2)
 179 #define CPLD_CKS_192000HZ       (CPLD_CKS2 | CPLD_CKS0)
 180
 181 #define CPLD_CKS_MASK           (CPLD_CKS0 | CPLD_CKS1 | CPLD_CKS2)
 182
 183 /* external clock (CPLD_SYNC_SEL = 1) options */
 184 /* external clock - SPDIF */
 185 #define CPLD_EXT_SPDIF  (0 | CPLD_SYNC_SEL)
 186 /* external clock - WordClock 1xfs */
 187 #define CPLD_EXT_WORDCLOCK_1FS  (CPLD_CKS1 | CPLD_SYNC_SEL)
 188 /* external clock - WordClock 256xfs */
 189 #define CPLD_EXT_WORDCLOCK_256FS        (CPLD_CKS1 | CPLD_WORD_SEL |\
 190                 CPLD_SYNC_SEL)
 191
 192 #define EXT_SPDIF_TYPE                  0
 193 #define EXT_WORDCLOCK_1FS_TYPE          1
 194 #define EXT_WORDCLOCK_256FS_TYPE        2
 195
 196 #define AK4620_DFS0             (1<<0)
 197 #define AK4620_DFS1             (1<<1)
 198 #define AK4620_CKS0             (1<<2)
 199 #define AK4620_CKS1             (1<<3)
 200 /* Clock and Format Control register */
 201 #define AK4620_DFS_REG          0x02
 202
 203 /* Deem and Volume Control register */
 204 #define AK4620_DEEMVOL_REG      0x03
 205 #define AK4620_SMUTE            (1<<7)
 206
 207 /*
 208  * Conversion from int value to its binary form. Used for debugging.
 209  * The output buffer must be allocated prior to calling the function.
 210  */
 211 static char *get_binary(char *buffer, int value)
 212 {
 213         int i, j, pos;
 214         pos = 0;
 215         for (i = 0; i < 4; ++i) {
 216                 for (j = 0; j < 8; ++j) {
 217                         if (value & (1 << (31-(i*8 + j))))
 218                                 buffer[pos] = '1';
 219                         else
 220                                 buffer[pos] = '0';
 221                         pos++;
 222                 }
 223                 if (i < 3) {
 224                         buffer[pos] = ' ';
 225                         pos++;
 226                 }
 227         }
 228         buffer[pos] = '\0';
 229         return buffer;
 230 }
 231
 232 /*
 233  * Initial setup of the conversion array GPIO <-> rate
 234  */
 235 static const unsigned int qtet_rates[] = {
 236         44100, 48000, 88200,
 237         96000, 176400, 192000,
 238 };
 239
 240 static const unsigned int cks_vals[] = {
 241         CPLD_CKS_44100HZ, CPLD_CKS_48000HZ, CPLD_CKS_88200HZ,
 242         CPLD_CKS_96000HZ, CPLD_CKS_176400HZ, CPLD_CKS_192000HZ,
 243 };
 244
 245 static const struct snd_pcm_hw_constraint_list qtet_rates_info = {
 246         .count = ARRAY_SIZE(qtet_rates),
 247         .list = qtet_rates,
 248         .mask = 0,
 249 };
 250
 251 static void qtet_ak4113_write(void *private_data, unsigned char reg,
 252                 unsigned char val)
 253 {
 254         snd_vt1724_write_i2c((struct snd_ice1712 *)private_data, AK4113_ADDR,
 255                         reg, val);
 256 }
 257
 258 static unsigned char qtet_ak4113_read(void *private_data, unsigned char reg)
 259 {
 260         return snd_vt1724_read_i2c((struct snd_ice1712 *)private_data,
 261                         AK4113_ADDR, reg);
 262 }
 263
 264
 265 /*
 266  * AK4620 section
 267  */
 268
 269 /*
 270  * Write data to addr register of ak4620
 271  */
 272 static void qtet_akm_write(struct snd_akm4xxx *ak, int chip,
 273                 unsigned char addr, unsigned char data)
 274 {
 275         unsigned int tmp, orig_dir;
 276         int idx;
 277         unsigned int addrdata;
 278         struct snd_ice1712 *ice = ak->private_data[0];
 279
 280         if (snd_BUG_ON(chip < 0 || chip >= 4))
 281                 return;
 282         /*dev_dbg(ice->card->dev, "Writing to AK4620: chip=%d, addr=0x%x,
 283           data=0x%x\n", chip, addr, data);*/
 284         orig_dir = ice->gpio.get_dir(ice);
 285         ice->gpio.set_dir(ice, orig_dir | GPIO_SPI_ALL);
 286         /* set mask - only SPI bits */
 287         ice->gpio.set_mask(ice, ~GPIO_SPI_ALL);
 288
 289         tmp = ice->gpio.get_data(ice);
 290         /* high all */
 291         tmp |= GPIO_SPI_ALL;
 292         ice->gpio.set_data(ice, tmp);
 293         udelay(100);
 294         /* drop chip select */
 295         if (chip)
 296                 /* CODEC 1 */
 297                 tmp &= ~GPIO_SPI_CSN1;
 298         else
 299                 tmp &= ~GPIO_SPI_CSN0;
 300         ice->gpio.set_data(ice, tmp);
 301         udelay(100);
 302
 303         /* build I2C address + data byte */
 304         addrdata = (AK4620_ADDR << 6) | 0x20 | (addr & 0x1f);
 305         addrdata = (addrdata << 8) | data;
 306         for (idx = 15; idx >= 0; idx--) {
 307                 /* drop clock */
 308                 tmp &= ~GPIO_D5_SPI_CCLK;
 309                 ice->gpio.set_data(ice, tmp);
 310                 udelay(100);
 311                 /* set data */
 312                 if (addrdata & (1 << idx))
 313                         tmp |= GPIO_D4_SPI_CDTO;
 314                 else
 315                         tmp &= ~GPIO_D4_SPI_CDTO;
 316                 ice->gpio.set_data(ice, tmp);
 317                 udelay(100);
 318                 /* raise clock */
 319                 tmp |= GPIO_D5_SPI_CCLK;
 320                 ice->gpio.set_data(ice, tmp);
 321                 udelay(100);
 322         }
 323         /* all back to 1 */
 324         tmp |= GPIO_SPI_ALL;
 325         ice->gpio.set_data(ice, tmp);
 326         udelay(100);
 327
 328         /* return all gpios to non-writable */
 329         ice->gpio.set_mask(ice, 0xffffff);
 330         /* restore GPIOs direction */
 331         ice->gpio.set_dir(ice, orig_dir);
 332 }
 333
 334 static void qtet_akm_set_regs(struct snd_akm4xxx *ak, unsigned char addr,
 335                 unsigned char mask, unsigned char value)
 336 {
 337         unsigned char tmp;
 338         int chip;
 339         for (chip = 0; chip < ak->num_chips; chip++) {
 340                 tmp = snd_akm4xxx_get(ak, chip, addr);
 341                 /* clear the bits */
 342                 tmp &= ~mask;
 343                 /* set the new bits */
 344                 tmp |= value;
 345                 snd_akm4xxx_write(ak, chip, addr, tmp);
 346         }
 347 }
 348
 349 /*
 350  * change the rate of AK4620
 351  */
 352 static void qtet_akm_set_rate_val(struct snd_akm4xxx *ak, unsigned int rate)
 353 {
 354         unsigned char ak4620_dfs;
 355
 356         if (rate == 0)  /* no hint - S/PDIF input is master or the new spdif
 357                            input rate undetected, simply return */
 358                 return;
 359
 360         /* adjust DFS on codecs - see datasheet */
 361         if (rate > 108000)
 362                 ak4620_dfs = AK4620_DFS1 | AK4620_CKS1;
 363         else if (rate > 54000)
 364                 ak4620_dfs = AK4620_DFS0 | AK4620_CKS0;
 365         else
 366                 ak4620_dfs = 0;
 367
 368         /* set new value */
 369         qtet_akm_set_regs(ak, AK4620_DFS_REG, AK4620_DFS0 | AK4620_DFS1 |
 370                         AK4620_CKS0 | AK4620_CKS1, ak4620_dfs);
 371 }
 372
 373 #define AK_CONTROL(xname, xch)  { .name = xname, .num_channels = xch }
 374
 375 #define PCM_12_PLAYBACK_VOLUME  "PCM 1/2 Playback Volume"
 376 #define PCM_34_PLAYBACK_VOLUME  "PCM 3/4 Playback Volume"
 377 #define PCM_12_CAPTURE_VOLUME   "PCM 1/2 Capture Volume"
 378 #define PCM_34_CAPTURE_VOLUME   "PCM 3/4 Capture Volume"
 379
 380 static const struct snd_akm4xxx_dac_channel qtet_dac[] = {
 381         AK_CONTROL(PCM_12_PLAYBACK_VOLUME, 2),
 382         AK_CONTROL(PCM_34_PLAYBACK_VOLUME, 2),
 383 };
 384
 385 static const struct snd_akm4xxx_adc_channel qtet_adc[] = {
 386         AK_CONTROL(PCM_12_CAPTURE_VOLUME, 2),
 387         AK_CONTROL(PCM_34_CAPTURE_VOLUME, 2),
 388 };
 389
 390 static const struct snd_akm4xxx akm_qtet_dac = {
 391         .type = SND_AK4620,
 392         .num_dacs = 4,  /* DAC1 - Output 12
 393         */
 394         .num_adcs = 4,  /* ADC1 - Input 12
 395         */
 396         .ops = {
 397                 .write = qtet_akm_write,
 398                 .set_rate_val = qtet_akm_set_rate_val,
 399         },
 400         .dac_info = qtet_dac,
 401         .adc_info = qtet_adc,
 402 };
 403
 404 /* Communication routines with the CPLD */
 405
 406
 407 /* Writes data to external register reg, both reg and data are
 408  * GPIO representations */
 409 static void reg_write(struct snd_ice1712 *ice, unsigned int reg,
 410                 unsigned int data)
 411 {
 412         unsigned int tmp;
 413
 414         mutex_lock(&ice->gpio_mutex);
 415         /* set direction of used GPIOs*/
 416         /* all outputs */
 417         tmp = 0x00ffff;
 418         ice->gpio.set_dir(ice, tmp);
 419         /* mask - writable bits */
 420         ice->gpio.set_mask(ice, ~(tmp));
 421         /* write the data */
 422         tmp = ice->gpio.get_data(ice);
 423         tmp &= ~GPIO_DATA_MASK;
 424         tmp |= data;
 425         ice->gpio.set_data(ice, tmp);
 426         udelay(100);
 427         /* drop output enable */
 428         tmp &=  ~GPIO_EX_GPIOE;
 429         ice->gpio.set_data(ice, tmp);
 430         udelay(100);
 431         /* drop the register gpio */
 432         tmp &= ~reg;
 433         ice->gpio.set_data(ice, tmp);
 434         udelay(100);
 435         /* raise the register GPIO */
 436         tmp |= reg;
 437         ice->gpio.set_data(ice, tmp);
 438         udelay(100);
 439
 440         /* raise all data gpios */
 441         tmp |= GPIO_DATA_MASK;
 442         ice->gpio.set_data(ice, tmp);
 443         /* mask - immutable bits */
 444         ice->gpio.set_mask(ice, 0xffffff);
 445         /* outputs only 8-15 */
 446         ice->gpio.set_dir(ice, 0x00ff00);
 447         mutex_unlock(&ice->gpio_mutex);
 448 }
 449
 450 static unsigned int get_scr(struct snd_ice1712 *ice)
 451 {
 452         struct qtet_spec *spec = ice->spec;
 453         return spec->scr;
 454 }
 455
 456 static unsigned int get_mcr(struct snd_ice1712 *ice)
 457 {
 458         struct qtet_spec *spec = ice->spec;
 459         return spec->mcr;
 460 }
 461
 462 static unsigned int get_cpld(struct snd_ice1712 *ice)
 463 {
 464         struct qtet_spec *spec = ice->spec;
 465         return spec->cpld;
 466 }
 467
 468 static void set_scr(struct snd_ice1712 *ice, unsigned int val)
 469 {
 470         struct qtet_spec *spec = ice->spec;
 471         reg_write(ice, GPIO_SCR, val);
 472         spec->scr = val;
 473 }
 474
 475 static void set_mcr(struct snd_ice1712 *ice, unsigned int val)
 476 {
 477         struct qtet_spec *spec = ice->spec;
 478         reg_write(ice, GPIO_MCR, val);
 479         spec->mcr = val;
 480 }
 481
 482 static void set_cpld(struct snd_ice1712 *ice, unsigned int val)
 483 {
 484         struct qtet_spec *spec = ice->spec;
 485         reg_write(ice, GPIO_CPLD_CSN, val);
 486         spec->cpld = val;
 487 }
 488
 489 static void proc_regs_read(struct snd_info_entry *entry,
 490                 struct snd_info_buffer *buffer)
 491 {
 492         struct snd_ice1712 *ice = entry->private_data;
 493         char bin_buffer[36];
 494
 495         snd_iprintf(buffer, "SCR:       %s\n", get_binary(bin_buffer,
 496                                 get_scr(ice)));
 497         snd_iprintf(buffer, "MCR:       %s\n", get_binary(bin_buffer,
 498                                 get_mcr(ice)));
 499         snd_iprintf(buffer, "CPLD:      %s\n", get_binary(bin_buffer,
 500                                 get_cpld(ice)));
 501 }
 502
 503 static void proc_init(struct snd_ice1712 *ice)
 504 {
 505         snd_card_ro_proc_new(ice->card, "quartet", ice, proc_regs_read);
 506 }
 507
 508 static int qtet_mute_get(struct snd_kcontrol *kcontrol,
 509                 struct snd_ctl_elem_value *ucontrol)
 510 {
 511         struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
 512         unsigned int val;
 513         val = get_scr(ice) & SCR_MUTE;
 514         ucontrol->value.integer.value[0] = (val) ? 0 : 1;
 515         return 0;
 516 }
 517
 518 static int qtet_mute_put(struct snd_kcontrol *kcontrol,
 519                 struct snd_ctl_elem_value *ucontrol)
 520 {
 521         struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
 522         unsigned int old, new, smute;
 523         old = get_scr(ice) & SCR_MUTE;
 524         if (ucontrol->value.integer.value[0]) {
 525                 /* unmute */
 526                 new = 0;
 527                 /* un-smuting DAC */
 528                 smute = 0;
 529         } else {
 530                 /* mute */
 531                 new = SCR_MUTE;
 532                 /* smuting DAC */
 533                 smute = AK4620_SMUTE;
 534         }
 535         if (old != new) {
 536                 struct snd_akm4xxx *ak = ice->akm;
 537                 set_scr(ice, (get_scr(ice) & ~SCR_MUTE) | new);
 538                 /* set smute */
 539                 qtet_akm_set_regs(ak, AK4620_DEEMVOL_REG, AK4620_SMUTE, smute);
 540                 return 1;
 541         }
 542         /* no change */
 543         return 0;
 544 }
 545
 546 static int qtet_ain12_enum_info(struct snd_kcontrol *kcontrol,
 547                 struct snd_ctl_elem_info *uinfo)
 548 {
 549         static const char * const texts[3] =
 550                 {"Line In 1/2", "Mic", "Mic + Low-cut"};
 551         return snd_ctl_enum_info(uinfo, 1, ARRAY_SIZE(texts), texts);
 552 }
 553
 554 static int qtet_ain12_sw_get(struct snd_kcontrol *kcontrol,
 555                 struct snd_ctl_elem_value *ucontrol)
 556 {
 557         struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
 558         unsigned int val, result;
 559         val = get_scr(ice) & (SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
 560         switch (val) {
 561         case SCR_AIN12_LINE:
 562                 result = 0;
 563                 break;
 564         case SCR_AIN12_MIC:
 565                 result = 1;
 566                 break;
 567         case SCR_AIN12_LOWCUT:
 568                 result = 2;
 569                 break;
 570         default:
 571                 /* BUG - no other combinations allowed */
 572                 snd_BUG();
 573                 result = 0;
 574         }
 575         ucontrol->value.integer.value[0] = result;
 576         return 0;
 577 }
 578
 579 static int qtet_ain12_sw_put(struct snd_kcontrol *kcontrol,
 580                 struct snd_ctl_elem_value *ucontrol)
 581 {
 582         struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
 583         unsigned int old, new, tmp, masked_old;
 584         old = new = get_scr(ice);
 585         masked_old = old & (SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
 586         tmp = ucontrol->value.integer.value[0];
 587         if (tmp == 2)
 588                 tmp = 3;        /* binary 10 is not supported */
 589         tmp <<= 4;      /* shifting to SCR_AIN12_SEL0 */
 590         if (tmp != masked_old) {
 591                 /* change requested */
 592                 switch (tmp) {
 593                 case SCR_AIN12_LINE:
 594                         new = old & ~(SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
 595                         set_scr(ice, new);
 596                         /* turn off relay */
 597                         new &= ~SCR_RELAY;
 598                         set_scr(ice, new);
 599                         break;
 600                 case SCR_AIN12_MIC:
 601                         /* turn on relay */
 602                         new = old | SCR_RELAY;
 603                         set_scr(ice, new);
 604                         new = (new & ~SCR_AIN12_SEL1) | SCR_AIN12_SEL0;
 605                         set_scr(ice, new);
 606                         break;
 607                 case SCR_AIN12_LOWCUT:
 608                         /* turn on relay */
 609                         new = old | SCR_RELAY;
 610                         set_scr(ice, new);
 611                         new |= SCR_AIN12_SEL1 | SCR_AIN12_SEL0;
 612                         set_scr(ice, new);
 613                         break;
 614                 default:
 615                         snd_BUG();
 616                 }
 617                 return 1;
 618         }
 619         /* no change */
 620         return 0;
 621 }
 622
 623 static int qtet_php_get(struct snd_kcontrol *kcontrol,
 624                 struct snd_ctl_elem_value *ucontrol)
 625 {
 626         struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
 627         unsigned int val;
 628         /* if phantom voltage =48V, phantom on */
 629         val = get_scr(ice) & SCR_PHP_V;
 630         ucontrol->value.integer.value[0] = val ? 1 : 0;
 631         return 0;
 632 }
 633
 634 static int qtet_php_put(struct snd_kcontrol *kcontrol,
 635                 struct snd_ctl_elem_value *ucontrol)
 636 {
 637         struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
 638         unsigned int old, new;
 639         old = new = get_scr(ice);
 640         if (ucontrol->value.integer.value[0] /* phantom on requested */
 641                         && (~old & SCR_PHP_V)) /* 0 = voltage 5V */ {
 642                 /* is off, turn on */
 643                 /* turn voltage on first, = 1 */
 644                 new = old | SCR_PHP_V;
 645                 set_scr(ice, new);
 646                 /* turn phantom on, = 0 */
 647                 new &= ~SCR_PHP;
 648                 set_scr(ice, new);
 649         } else if (!ucontrol->value.integer.value[0] && (old & SCR_PHP_V)) {
 650                 /* phantom off requested and 1 = voltage 48V */
 651                 /* is on, turn off */
 652                 /* turn voltage off first, = 0 */
 653                 new = old & ~SCR_PHP_V;
 654                 set_scr(ice, new);
 655                 /* turn phantom off, = 1 */
 656                 new |= SCR_PHP;
 657                 set_scr(ice, new);
 658         }
 659         if (old != new)
 660                 return 1;
 661         /* no change */
 662         return 0;
 663 }
 664
 665 #define PRIV_SW(xid, xbit, xreg)        [xid] = {.bit = xbit,\
 666         .set_register = set_##xreg,\
 667         .get_register = get_##xreg, }
 668
 669
 670 #define PRIV_ENUM2(xid, xbit, xreg, xtext1, xtext2)     [xid] = {.bit = xbit,\
 671         .set_register = set_##xreg,\
 672         .get_register = get_##xreg,\
 673         .texts = {xtext1, xtext2} }
 674
 675 static struct qtet_kcontrol_private qtet_privates[] = {
 676         PRIV_ENUM2(IN12_SEL, CPLD_IN12_SEL, cpld, "An In 1/2", "An In 3/4"),
 677         PRIV_ENUM2(IN34_SEL, CPLD_IN34_SEL, cpld, "An In 3/4", "IEC958 In"),
 678         PRIV_ENUM2(AIN34_SEL, SCR_AIN34_SEL, scr, "Line In 3/4", "Hi-Z"),
 679         PRIV_ENUM2(COAX_OUT, CPLD_COAX_OUT, cpld, "IEC958", "I2S"),
 680         PRIV_SW(IN12_MON12, MCR_IN12_MON12, mcr),
 681         PRIV_SW(IN12_MON34, MCR_IN12_MON34, mcr),
 682         PRIV_SW(IN34_MON12, MCR_IN34_MON12, mcr),
 683         PRIV_SW(IN34_MON34, MCR_IN34_MON34, mcr),
 684         PRIV_SW(OUT12_MON34, MCR_OUT12_MON34, mcr),
 685         PRIV_SW(OUT34_MON12, MCR_OUT34_MON12, mcr),
 686 };
 687
 688 static int qtet_enum_info(struct snd_kcontrol *kcontrol,
 689                 struct snd_ctl_elem_info *uinfo)
 690 {
 691         struct qtet_kcontrol_private private =
 692                 qtet_privates[kcontrol->private_value];
 693         return snd_ctl_enum_info(uinfo, 1, ARRAY_SIZE(private.texts),
 694                                  private.texts);
 695 }
 696
 697 static int qtet_sw_get(struct snd_kcontrol *kcontrol,
 698                 struct snd_ctl_elem_value *ucontrol)
 699 {
 700         struct qtet_kcontrol_private private =
 701                 qtet_privates[kcontrol->private_value];
 702         struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
 703         ucontrol->value.integer.value[0] =
 704                 (private.get_register(ice) & private.bit) ? 1 : 0;
 705         return 0;
 706 }
 707
 708 static int qtet_sw_put(struct snd_kcontrol *kcontrol,
 709                 struct snd_ctl_elem_value *ucontrol)
 710 {
 711         struct qtet_kcontrol_private private =
 712                 qtet_privates[kcontrol->private_value];
 713         struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
 714         unsigned int old, new;
 715         old = private.get_register(ice);
 716         if (ucontrol->value.integer.value[0])
 717                 new = old | private.bit;
 718         else
 719                 new = old & ~private.bit;
 720         if (old != new) {
 721                 private.set_register(ice, new);
 722                 return 1;
 723         }
 724         /* no change */
 725         return 0;
 726 }
 727
 728 #define qtet_sw_info    snd_ctl_boolean_mono_info
 729
 730 #define QTET_CONTROL(xname, xtype, xpriv)       \
 731         {.iface = SNDRV_CTL_ELEM_IFACE_MIXER,\
 732         .name = xname,\
 733         .info = qtet_##xtype##_info,\
 734         .get = qtet_sw_get,\
 735         .put = qtet_sw_put,\
 736         .private_value = xpriv }
 737
 738 static struct snd_kcontrol_new qtet_controls[] = {
 739         {
 740                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
 741                 .name = "Master Playback Switch",
 742                 .info = qtet_sw_info,
 743                 .get = qtet_mute_get,
 744                 .put = qtet_mute_put,
 745                 .private_value = 0
 746         },
 747         {
 748                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
 749                 .name = "Phantom Power",
 750                 .info = qtet_sw_info,
 751                 .get = qtet_php_get,
 752                 .put = qtet_php_put,
 753                 .private_value = 0
 754         },
 755         {
 756                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
 757                 .name = "Analog In 1/2 Capture Switch",
 758                 .info = qtet_ain12_enum_info,
 759                 .get = qtet_ain12_sw_get,
 760                 .put = qtet_ain12_sw_put,
 761                 .private_value = 0
 762         },
 763         QTET_CONTROL("Analog In 3/4 Capture Switch", enum, AIN34_SEL),
 764         QTET_CONTROL("PCM In 1/2 Capture Switch", enum, IN12_SEL),
 765         QTET_CONTROL("PCM In 3/4 Capture Switch", enum, IN34_SEL),
 766         QTET_CONTROL("Coax Output Source", enum, COAX_OUT),
 767         QTET_CONTROL("Analog In 1/2 to Monitor 1/2", sw, IN12_MON12),
 768         QTET_CONTROL("Analog In 1/2 to Monitor 3/4", sw, IN12_MON34),
 769         QTET_CONTROL("Analog In 3/4 to Monitor 1/2", sw, IN34_MON12),
 770         QTET_CONTROL("Analog In 3/4 to Monitor 3/4", sw, IN34_MON34),
 771         QTET_CONTROL("Output 1/2 to Monitor 3/4", sw, OUT12_MON34),
 772         QTET_CONTROL("Output 3/4 to Monitor 1/2", sw, OUT34_MON12),
 773 };
 774
 775 static char *slave_vols[] = {
 776         PCM_12_PLAYBACK_VOLUME,
 777         PCM_34_PLAYBACK_VOLUME,
 778         NULL
 779 };
 780
 781 static
 782 DECLARE_TLV_DB_SCALE(qtet_master_db_scale, -6350, 50, 1);
 783
 784 static struct snd_kcontrol *ctl_find(struct snd_card *card,
 785                                      const char *name)
 786 {
 787         struct snd_ctl_elem_id sid = {0};
 788
 789         strlcpy(sid.name, name, sizeof(sid.name));
 790         sid.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
 791         return snd_ctl_find_id(card, &sid);
 792 }
 793
 794 static void add_slaves(struct snd_card *card,
 795                        struct snd_kcontrol *master, char * const *list)
 796 {
 797         for (; *list; list++) {
 798                 struct snd_kcontrol *slave = ctl_find(card, *list);
 799                 if (slave)
 800                         snd_ctl_add_slave(master, slave);
 801         }
 802 }
 803
 804 static int qtet_add_controls(struct snd_ice1712 *ice)
 805 {
 806         struct qtet_spec *spec = ice->spec;
 807         int err, i;
 808         struct snd_kcontrol *vmaster;
 809         err = snd_ice1712_akm4xxx_build_controls(ice);
 810         if (err < 0)
 811                 return err;
 812         for (i = 0; i < ARRAY_SIZE(qtet_controls); i++) {
 813                 err = snd_ctl_add(ice->card,
 814                                 snd_ctl_new1(&qtet_controls[i], ice));
 815                 if (err < 0)
 816                         return err;
 817         }
 818
 819         /* Create virtual master control */
 820         vmaster = snd_ctl_make_virtual_master("Master Playback Volume",
 821                         qtet_master_db_scale);
 822         if (!vmaster)
 823                 return -ENOMEM;
 824         add_slaves(ice->card, vmaster, slave_vols);
 825         err = snd_ctl_add(ice->card, vmaster);
 826         if (err < 0)
 827                 return err;
 828         /* only capture SPDIF over AK4113 */
 829         return snd_ak4113_build(spec->ak4113,
 830                         ice->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
 831 }
 832
 833 static inline int qtet_is_spdif_master(struct snd_ice1712 *ice)
 834 {
 835         /* CPLD_SYNC_SEL: 0 = internal, 1 = external (i.e. spdif master) */
 836         return (get_cpld(ice) & CPLD_SYNC_SEL) ? 1 : 0;
 837 }
 838
 839 static unsigned int qtet_get_rate(struct snd_ice1712 *ice)
 840 {
 841         int i;
 842         unsigned char result;
 843
 844         result =  get_cpld(ice) & CPLD_CKS_MASK;
 845         for (i = 0; i < ARRAY_SIZE(cks_vals); i++)
 846                 if (cks_vals[i] == result)
 847                         return qtet_rates[i];
 848         return 0;
 849 }
 850
 851 static int get_cks_val(int rate)
 852 {
 853         int i;
 854         for (i = 0; i < ARRAY_SIZE(qtet_rates); i++)
 855                 if (qtet_rates[i] == rate)
 856                         return cks_vals[i];
 857         return 0;
 858 }
 859
 860 /* setting new rate */
 861 static void qtet_set_rate(struct snd_ice1712 *ice, unsigned int rate)
 862 {
 863         unsigned int new;
 864         unsigned char val;
 865         /* switching ice1724 to external clock - supplied by ext. circuits */
 866         val = inb(ICEMT1724(ice, RATE));
 867         outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
 868
 869         new =  (get_cpld(ice) & ~CPLD_CKS_MASK) | get_cks_val(rate);
 870         /* switch to internal clock, drop CPLD_SYNC_SEL */
 871         new &= ~CPLD_SYNC_SEL;
 872         /* dev_dbg(ice->card->dev, "QT - set_rate: old %x, new %x\n",
 873            get_cpld(ice), new); */
 874         set_cpld(ice, new);
 875 }
 876
 877 static inline unsigned char qtet_set_mclk(struct snd_ice1712 *ice,
 878                 unsigned int rate)
 879 {
 880         /* no change in master clock */
 881         return 0;
 882 }
 883
 884 /* setting clock to external - SPDIF */
 885 static int qtet_set_spdif_clock(struct snd_ice1712 *ice, int type)
 886 {
 887         unsigned int old, new;
 888
 889         old = new = get_cpld(ice);
 890         new &= ~(CPLD_CKS_MASK | CPLD_WORD_SEL);
 891         switch (type) {
 892         case EXT_SPDIF_TYPE:
 893                 new |= CPLD_EXT_SPDIF;
 894                 break;
 895         case EXT_WORDCLOCK_1FS_TYPE:
 896                 new |= CPLD_EXT_WORDCLOCK_1FS;
 897                 break;
 898         case EXT_WORDCLOCK_256FS_TYPE:
 899                 new |= CPLD_EXT_WORDCLOCK_256FS;
 900                 break;
 901         default:
 902                 snd_BUG();
 903         }
 904         if (old != new) {
 905                 set_cpld(ice, new);
 906                 /* changed */
 907                 return 1;
 908         }
 909         return 0;
 910 }
 911
 912 static int qtet_get_spdif_master_type(struct snd_ice1712 *ice)
 913 {
 914         unsigned int val;
 915         int result;
 916         val = get_cpld(ice);
 917         /* checking only rate/clock-related bits */
 918         val &= (CPLD_CKS_MASK | CPLD_WORD_SEL | CPLD_SYNC_SEL);
 919         if (!(val & CPLD_SYNC_SEL)) {
 920                 /* switched to internal clock, is not any external type */
 921                 result = -1;
 922         } else {
 923                 switch (val) {
 924                 case (CPLD_EXT_SPDIF):
 925                         result = EXT_SPDIF_TYPE;
 926                         break;
 927                 case (CPLD_EXT_WORDCLOCK_1FS):
 928                         result = EXT_WORDCLOCK_1FS_TYPE;
 929                         break;
 930                 case (CPLD_EXT_WORDCLOCK_256FS):
 931                         result = EXT_WORDCLOCK_256FS_TYPE;
 932                         break;
 933                 default:
 934                         /* undefined combination of external clock setup */
 935                         snd_BUG();
 936                         result = 0;
 937                 }
 938         }
 939         return result;
 940 }
 941
 942 /* Called when ak4113 detects change in the input SPDIF stream */
 943 static void qtet_ak4113_change(struct ak4113 *ak4113, unsigned char c0,
 944                 unsigned char c1)
 945 {
 946         struct snd_ice1712 *ice = ak4113->change_callback_private;
 947         int rate;
 948         if ((qtet_get_spdif_master_type(ice) == EXT_SPDIF_TYPE) &&
 949                         c1) {
 950                 /* only for SPDIF master mode, rate was changed */
 951                 rate = snd_ak4113_external_rate(ak4113);
 952                 /* dev_dbg(ice->card->dev, "ak4113 - input rate changed to %d\n",
 953                    rate); */
 954                 qtet_akm_set_rate_val(ice->akm, rate);
 955         }
 956 }
 957
 958 /*
 959  * If clock slaved to SPDIF-IN, setting runtime rate
 960  * to the detected external rate
 961  */
 962 static void qtet_spdif_in_open(struct snd_ice1712 *ice,
 963                 struct snd_pcm_substream *substream)
 964 {
 965         struct qtet_spec *spec = ice->spec;
 966         struct snd_pcm_runtime *runtime = substream->runtime;
 967         int rate;
 968
 969         if (qtet_get_spdif_master_type(ice) != EXT_SPDIF_TYPE)
 970                 /* not external SPDIF, no rate limitation */
 971                 return;
 972         /* only external SPDIF can detect incoming sample rate */
 973         rate = snd_ak4113_external_rate(spec->ak4113);
 974         if (rate >= runtime->hw.rate_min && rate <= runtime->hw.rate_max) {
 975                 runtime->hw.rate_min = rate;
 976                 runtime->hw.rate_max = rate;
 977         }
 978 }
 979
 980 /*
 981  * initialize the chip
 982  */
 983 static int qtet_init(struct snd_ice1712 *ice)
 984 {
 985         static const unsigned char ak4113_init_vals[] = {
 986                 /* AK4113_REG_PWRDN */  AK4113_RST | AK4113_PWN |
 987                         AK4113_OCKS0 | AK4113_OCKS1,
 988                 /* AK4113_REQ_FORMAT */ AK4113_DIF_I24I2S | AK4113_VTX |
 989                         AK4113_DEM_OFF | AK4113_DEAU,
 990                 /* AK4113_REG_IO0 */    AK4113_OPS2 | AK4113_TXE |
 991                         AK4113_XTL_24_576M,
 992                 /* AK4113_REG_IO1 */    AK4113_EFH_1024LRCLK | AK4113_IPS(0),
 993                 /* AK4113_REG_INT0_MASK */      0,
 994                 /* AK4113_REG_INT1_MASK */      0,
 995                 /* AK4113_REG_DATDTS */         0,
 996         };
 997         int err;
 998         struct qtet_spec *spec;
 999         struct snd_akm4xxx *ak;
1000         unsigned char val;
1001
1002         /* switching ice1724 to external clock - supplied by ext. circuits */
1003         val = inb(ICEMT1724(ice, RATE));
1004         outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
1005
1006         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1007         if (!spec)
1008                 return -ENOMEM;
1009         /* qtet is clocked by Xilinx array */
1010         ice->hw_rates = &qtet_rates_info;
1011         ice->is_spdif_master = qtet_is_spdif_master;
1012         ice->get_rate = qtet_get_rate;
1013         ice->set_rate = qtet_set_rate;
1014         ice->set_mclk = qtet_set_mclk;
1015         ice->set_spdif_clock = qtet_set_spdif_clock;
1016         ice->get_spdif_master_type = qtet_get_spdif_master_type;
1017         ice->ext_clock_names = ext_clock_names;
1018         ice->ext_clock_count = ARRAY_SIZE(ext_clock_names);
1019         /* since Qtet can detect correct SPDIF-in rate, all streams can be
1020          * limited to this specific rate */
1021         ice->spdif.ops.open = ice->pro_open = qtet_spdif_in_open;
1022         ice->spec = spec;
1023
1024         /* Mute Off */
1025         /* SCR Initialize*/
1026         /* keep codec power down first */
1027         set_scr(ice, SCR_PHP);
1028         udelay(1);
1029         /* codec power up */
1030         set_scr(ice, SCR_PHP | SCR_CODEC_PDN);
1031
1032         /* MCR Initialize */
1033         set_mcr(ice, 0);
1034
1035         /* CPLD Initialize */
1036         set_cpld(ice, 0);
1037
1038
1039         ice->num_total_dacs = 2;
1040         ice->num_total_adcs = 2;
1041
1042         ice->akm = kcalloc(2, sizeof(struct snd_akm4xxx), GFP_KERNEL);
1043         ak = ice->akm;
1044         if (!ak)
1045                 return -ENOMEM;
1046         /* only one codec with two chips */
1047         ice->akm_codecs = 1;
1048         err = snd_ice1712_akm4xxx_init(ak, &akm_qtet_dac, NULL, ice);
1049         if (err < 0)
1050                 return err;
1051         err = snd_ak4113_create(ice->card,
1052                         qtet_ak4113_read,
1053                         qtet_ak4113_write,
1054                         ak4113_init_vals,
1055                         ice, &spec->ak4113);
1056         if (err < 0)
1057                 return err;
1058         /* callback for codecs rate setting */
1059         spec->ak4113->change_callback = qtet_ak4113_change;
1060         spec->ak4113->change_callback_private = ice;
1061         /* AK41143 in Quartet can detect external rate correctly
1062          * (i.e. check_flags = 0) */
1063         spec->ak4113->check_flags = 0;
1064
1065         proc_init(ice);
1066
1067         qtet_set_rate(ice, 44100);
1068         return 0;
1069 }
1070
1071 static unsigned char qtet_eeprom[] = {
1072         [ICE_EEP2_SYSCONF]     = 0x28,  /* clock 256(24MHz), mpu401, 1xADC,
1073                                            1xDACs, SPDIF in */
1074         [ICE_EEP2_ACLINK]      = 0x80,  /* I2S */
1075         [ICE_EEP2_I2S]         = 0x78,  /* 96k, 24bit, 192k */
1076         [ICE_EEP2_SPDIF]       = 0xc3,  /* out-en, out-int, in, out-ext */
1077         [ICE_EEP2_GPIO_DIR]    = 0x00,  /* 0-7 inputs, switched to output
1078                                            only during output operations */
1079         [ICE_EEP2_GPIO_DIR1]   = 0xff,  /* 8-15 outputs */
1080         [ICE_EEP2_GPIO_DIR2]   = 0x00,
1081         [ICE_EEP2_GPIO_MASK]   = 0xff,  /* changed only for OUT operations */
1082         [ICE_EEP2_GPIO_MASK1]  = 0x00,
1083         [ICE_EEP2_GPIO_MASK2]  = 0xff,
1084
1085         [ICE_EEP2_GPIO_STATE]  = 0x00, /* inputs */
1086         [ICE_EEP2_GPIO_STATE1] = 0x7d, /* all 1, but GPIO_CPLD_RW
1087                                           and GPIO15 always zero */
1088         [ICE_EEP2_GPIO_STATE2] = 0x00, /* inputs */
1089 };
1090
1091 /* entry point */
1092 struct snd_ice1712_card_info snd_vt1724_qtet_cards[] = {
1093         {
1094                 .subvendor = VT1724_SUBDEVICE_QTET,
1095                 .name = "Infrasonic Quartet",
1096                 .model = "quartet",
1097                 .chip_init = qtet_init,
1098                 .build_controls = qtet_add_controls,
1099                 .eeprom_size = sizeof(qtet_eeprom),
1100                 .eeprom_data = qtet_eeprom,
1101         },
1102         { } /* terminator */
1103 };