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1 /*
2 * ALSA driver for RME Hammerfall DSP audio interface(s)
3 *
4 * Copyright (c) 2002 Paul Davis
5 * Marcus Andersson
6 * Thomas Charbonnel
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/firmware.h>
29 #include <linux/module.h>
30 #include <linux/math64.h>
31 #include <linux/vmalloc.h>
32 #include <linux/io.h>
33 #include <linux/nospec.h>
34
35 #include <sound/core.h>
36 #include <sound/control.h>
37 #include <sound/pcm.h>
38 #include <sound/info.h>
39 #include <sound/asoundef.h>
40 #include <sound/rawmidi.h>
41 #include <sound/hwdep.h>
42 #include <sound/initval.h>
43 #include <sound/hdsp.h>
44
45 #include <asm/byteorder.h>
46 #include <asm/current.h>
47
48 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
49 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
50 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
51
52 module_param_array(index, int, NULL, 0444);
53 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
54 module_param_array(id, charp, NULL, 0444);
55 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
56 module_param_array(enable, bool, NULL, 0444);
57 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
58 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
59 MODULE_DESCRIPTION("RME Hammerfall DSP");
60 MODULE_LICENSE("GPL");
61 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
62 "{RME HDSP-9652},"
63 "{RME HDSP-9632}}");
64 MODULE_FIRMWARE("rpm_firmware.bin");
65 MODULE_FIRMWARE("multiface_firmware.bin");
66 MODULE_FIRMWARE("multiface_firmware_rev11.bin");
67 MODULE_FIRMWARE("digiface_firmware.bin");
68 MODULE_FIRMWARE("digiface_firmware_rev11.bin");
69
70 #define HDSP_MAX_CHANNELS 26
71 #define HDSP_MAX_DS_CHANNELS 14
72 #define HDSP_MAX_QS_CHANNELS 8
73 #define DIGIFACE_SS_CHANNELS 26
74 #define DIGIFACE_DS_CHANNELS 14
75 #define MULTIFACE_SS_CHANNELS 18
76 #define MULTIFACE_DS_CHANNELS 14
77 #define H9652_SS_CHANNELS 26
78 #define H9652_DS_CHANNELS 14
79 /* This does not include possible Analog Extension Boards
80 AEBs are detected at card initialization
81 */
82 #define H9632_SS_CHANNELS 12
83 #define H9632_DS_CHANNELS 8
84 #define H9632_QS_CHANNELS 4
85 #define RPM_CHANNELS 6
86
87 /* Write registers. These are defined as byte-offsets from the iobase value.
88 */
89 #define HDSP_resetPointer 0
90 #define HDSP_freqReg 0
91 #define HDSP_outputBufferAddress 32
92 #define HDSP_inputBufferAddress 36
93 #define HDSP_controlRegister 64
94 #define HDSP_interruptConfirmation 96
95 #define HDSP_outputEnable 128
96 #define HDSP_control2Reg 256
97 #define HDSP_midiDataOut0 352
98 #define HDSP_midiDataOut1 356
99 #define HDSP_fifoData 368
100 #define HDSP_inputEnable 384
101
102 /* Read registers. These are defined as byte-offsets from the iobase value
103 */
104
105 #define HDSP_statusRegister 0
106 #define HDSP_timecode 128
107 #define HDSP_status2Register 192
108 #define HDSP_midiDataIn0 360
109 #define HDSP_midiDataIn1 364
110 #define HDSP_midiStatusOut0 384
111 #define HDSP_midiStatusOut1 388
112 #define HDSP_midiStatusIn0 392
113 #define HDSP_midiStatusIn1 396
114 #define HDSP_fifoStatus 400
115
116 /* the meters are regular i/o-mapped registers, but offset
117 considerably from the rest. the peak registers are reset
118 when read; the least-significant 4 bits are full-scale counters;
119 the actual peak value is in the most-significant 24 bits.
120 */
121
122 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
123 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
124 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
125 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
126 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
127
128
129 /* This is for H9652 cards
130 Peak values are read downward from the base
131 Rms values are read upward
132 There are rms values for the outputs too
133 26*3 values are read in ss mode
134 14*3 in ds mode, with no gap between values
135 */
136 #define HDSP_9652_peakBase 7164
137 #define HDSP_9652_rmsBase 4096
138
139 /* c.f. the hdsp_9632_meters_t struct */
140 #define HDSP_9632_metersBase 4096
141
142 #define HDSP_IO_EXTENT 7168
143
144 /* control2 register bits */
145
146 #define HDSP_TMS 0x01
147 #define HDSP_TCK 0x02
148 #define HDSP_TDI 0x04
149 #define HDSP_JTAG 0x08
150 #define HDSP_PWDN 0x10
151 #define HDSP_PROGRAM 0x020
152 #define HDSP_CONFIG_MODE_0 0x040
153 #define HDSP_CONFIG_MODE_1 0x080
154 #define HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD)
155 #define HDSP_BIGENDIAN_MODE 0x200
156 #define HDSP_RD_MULTIPLE 0x400
157 #define HDSP_9652_ENABLE_MIXER 0x800
158 #define HDSP_S200 0x800
159 #define HDSP_S300 (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
160 #define HDSP_CYCLIC_MODE 0x1000
161 #define HDSP_TDO 0x10000000
162
163 #define HDSP_S_PROGRAM (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
164 #define HDSP_S_LOAD (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
165
166 /* Control Register bits */
167
168 #define HDSP_Start (1<<0) /* start engine */
169 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
170 #define HDSP_Latency1 (1<<2) /* [ see above ] */
171 #define HDSP_Latency2 (1<<3) /* [ see above ] */
172 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
173 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
174 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
175 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
176 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
177 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
178 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
179 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
180 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
181 #define HDSP_SyncRef2 (1<<13)
182 #define HDSP_SPDIFInputSelect0 (1<<14)
183 #define HDSP_SPDIFInputSelect1 (1<<15)
184 #define HDSP_SyncRef0 (1<<16)
185 #define HDSP_SyncRef1 (1<<17)
186 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
187 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
188 #define HDSP_Midi0InterruptEnable (1<<22)
189 #define HDSP_Midi1InterruptEnable (1<<23)
190 #define HDSP_LineOut (1<<24)
191 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
192 #define HDSP_ADGain1 (1<<26)
193 #define HDSP_DAGain0 (1<<27)
194 #define HDSP_DAGain1 (1<<28)
195 #define HDSP_PhoneGain0 (1<<29)
196 #define HDSP_PhoneGain1 (1<<30)
197 #define HDSP_QuadSpeed (1<<31)
198
199 /* RPM uses some of the registers for special purposes */
200 #define HDSP_RPM_Inp12 0x04A00
201 #define HDSP_RPM_Inp12_Phon_6dB 0x00800 /* Dolby */
202 #define HDSP_RPM_Inp12_Phon_0dB 0x00000 /* .. */
203 #define HDSP_RPM_Inp12_Phon_n6dB 0x04000 /* inp_0 */
204 #define HDSP_RPM_Inp12_Line_0dB 0x04200 /* Dolby+PRO */
205 #define HDSP_RPM_Inp12_Line_n6dB 0x00200 /* PRO */
206
207 #define HDSP_RPM_Inp34 0x32000
208 #define HDSP_RPM_Inp34_Phon_6dB 0x20000 /* SyncRef1 */
209 #define HDSP_RPM_Inp34_Phon_0dB 0x00000 /* .. */
210 #define HDSP_RPM_Inp34_Phon_n6dB 0x02000 /* SyncRef2 */
211 #define HDSP_RPM_Inp34_Line_0dB 0x30000 /* SyncRef1+SyncRef0 */
212 #define HDSP_RPM_Inp34_Line_n6dB 0x10000 /* SyncRef0 */
213
214 #define HDSP_RPM_Bypass 0x01000
215
216 #define HDSP_RPM_Disconnect 0x00001
217
218 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
219 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
220 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
221 #define HDSP_ADGainLowGain 0
222
223 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
224 #define HDSP_DAGainHighGain HDSP_DAGainMask
225 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
226 #define HDSP_DAGainMinus10dBV 0
227
228 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
229 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
230 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
231 #define HDSP_PhoneGainMinus12dB 0
232
233 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
234 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
235
236 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
237 #define HDSP_SPDIFInputADAT1 0
238 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
239 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
240 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
241
242 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
243 #define HDSP_SyncRef_ADAT1 0
244 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
245 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
246 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
247 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
248 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
249
250 /* Sample Clock Sources */
251
252 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
253 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
254 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
255 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
256 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
257 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
258 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
259 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
260 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
261 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
262
263 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
264
265 #define HDSP_SYNC_FROM_WORD 0
266 #define HDSP_SYNC_FROM_SPDIF 1
267 #define HDSP_SYNC_FROM_ADAT1 2
268 #define HDSP_SYNC_FROM_ADAT_SYNC 3
269 #define HDSP_SYNC_FROM_ADAT2 4
270 #define HDSP_SYNC_FROM_ADAT3 5
271
272 /* SyncCheck status */
273
274 #define HDSP_SYNC_CHECK_NO_LOCK 0
275 #define HDSP_SYNC_CHECK_LOCK 1
276 #define HDSP_SYNC_CHECK_SYNC 2
277
278 /* AutoSync references - used by "autosync_ref" control switch */
279
280 #define HDSP_AUTOSYNC_FROM_WORD 0
281 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
282 #define HDSP_AUTOSYNC_FROM_SPDIF 2
283 #define HDSP_AUTOSYNC_FROM_NONE 3
284 #define HDSP_AUTOSYNC_FROM_ADAT1 4
285 #define HDSP_AUTOSYNC_FROM_ADAT2 5
286 #define HDSP_AUTOSYNC_FROM_ADAT3 6
287
288 /* Possible sources of S/PDIF input */
289
290 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
291 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
292 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
293 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
294
295 #define HDSP_Frequency32KHz HDSP_Frequency0
296 #define HDSP_Frequency44_1KHz HDSP_Frequency1
297 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
298 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
299 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
300 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
301 /* For H9632 cards */
302 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
303 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
304 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
305 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
306 return 104857600000000 / rate; // 100 MHz
307 return 110100480000000 / rate; // 105 MHz
308 */
309 #define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */
310
311 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
312 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
313
314 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
315 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
316
317 /* Status Register bits */
318
319 #define HDSP_audioIRQPending (1<<0)
320 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
321 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
322 #define HDSP_Lock1 (1<<2)
323 #define HDSP_Lock0 (1<<3)
324 #define HDSP_SPDIFSync (1<<4)
325 #define HDSP_TimecodeLock (1<<5)
326 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
327 #define HDSP_Sync2 (1<<16)
328 #define HDSP_Sync1 (1<<17)
329 #define HDSP_Sync0 (1<<18)
330 #define HDSP_DoubleSpeedStatus (1<<19)
331 #define HDSP_ConfigError (1<<20)
332 #define HDSP_DllError (1<<21)
333 #define HDSP_spdifFrequency0 (1<<22)
334 #define HDSP_spdifFrequency1 (1<<23)
335 #define HDSP_spdifFrequency2 (1<<24)
336 #define HDSP_SPDIFErrorFlag (1<<25)
337 #define HDSP_BufferID (1<<26)
338 #define HDSP_TimecodeSync (1<<27)
339 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
340 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
341 #define HDSP_midi0IRQPending (1<<30)
342 #define HDSP_midi1IRQPending (1<<31)
343
344 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
345 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
346 HDSP_spdifFrequency1|\
347 HDSP_spdifFrequency2|\
348 HDSP_spdifFrequency3)
349
350 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
351 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
352 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
353
354 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
355 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
356 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
357
358 /* This is for H9632 cards */
359 #define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\
360 HDSP_spdifFrequency1|\
361 HDSP_spdifFrequency2)
362 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
363 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
364
365 /* Status2 Register bits */
366
367 #define HDSP_version0 (1<<0)
368 #define HDSP_version1 (1<<1)
369 #define HDSP_version2 (1<<2)
370 #define HDSP_wc_lock (1<<3)
371 #define HDSP_wc_sync (1<<4)
372 #define HDSP_inp_freq0 (1<<5)
373 #define HDSP_inp_freq1 (1<<6)
374 #define HDSP_inp_freq2 (1<<7)
375 #define HDSP_SelSyncRef0 (1<<8)
376 #define HDSP_SelSyncRef1 (1<<9)
377 #define HDSP_SelSyncRef2 (1<<10)
378
379 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
380
381 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
382 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
383 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
384 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
385 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
386 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
387 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
388 /* FIXME : more values for 9632 cards ? */
389
390 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
391 #define HDSP_SelSyncRef_ADAT1 0
392 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
393 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
394 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
395 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
396 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
397
398 /* Card state flags */
399
400 #define HDSP_InitializationComplete (1<<0)
401 #define HDSP_FirmwareLoaded (1<<1)
402 #define HDSP_FirmwareCached (1<<2)
403
404 /* FIFO wait times, defined in terms of 1/10ths of msecs */
405
406 #define HDSP_LONG_WAIT 5000
407 #define HDSP_SHORT_WAIT 30
408
409 #define UNITY_GAIN 32768
410 #define MINUS_INFINITY_GAIN 0
411
412 /* the size of a substream (1 mono data stream) */
413
414 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
415 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
416
417 /* the size of the area we need to allocate for DMA transfers. the
418 size is the same regardless of the number of channels - the
419 Multiface still uses the same memory area.
420
421 Note that we allocate 1 more channel than is apparently needed
422 because the h/w seems to write 1 byte beyond the end of the last
423 page. Sigh.
424 */
425
426 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
427 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
428
429 #define HDSP_FIRMWARE_SIZE (24413 * 4)
430
431 struct hdsp_9632_meters {
432 u32 input_peak[16];
433 u32 playback_peak[16];
434 u32 output_peak[16];
435 u32 xxx_peak[16];
436 u32 padding[64];
437 u32 input_rms_low[16];
438 u32 playback_rms_low[16];
439 u32 output_rms_low[16];
440 u32 xxx_rms_low[16];
441 u32 input_rms_high[16];
442 u32 playback_rms_high[16];
443 u32 output_rms_high[16];
444 u32 xxx_rms_high[16];
445 };
446
447 struct hdsp_midi {
448 struct hdsp *hdsp;
449 int id;
450 struct snd_rawmidi *rmidi;
451 struct snd_rawmidi_substream *input;
452 struct snd_rawmidi_substream *output;
453 char istimer; /* timer in use */
454 struct timer_list timer;
455 spinlock_t lock;
456 int pending;
457 };
458
459 struct hdsp {
460 spinlock_t lock;
461 struct snd_pcm_substream *capture_substream;
462 struct snd_pcm_substream *playback_substream;
463 struct hdsp_midi midi[2];
464 struct tasklet_struct midi_tasklet;
465 int use_midi_tasklet;
466 int precise_ptr;
467 u32 control_register; /* cached value */
468 u32 control2_register; /* cached value */
469 u32 creg_spdif;
470 u32 creg_spdif_stream;
471 int clock_source_locked;
472 char *card_name; /* digiface/multiface/rpm */
473 enum HDSP_IO_Type io_type; /* ditto, but for code use */
474 unsigned short firmware_rev;
475 unsigned short state; /* stores state bits */
476 const struct firmware *firmware;
477 u32 *fw_uploaded;
478 size_t period_bytes; /* guess what this is */
479 unsigned char max_channels;
480 unsigned char qs_in_channels; /* quad speed mode for H9632 */
481 unsigned char ds_in_channels;
482 unsigned char ss_in_channels; /* different for multiface/digiface */
483 unsigned char qs_out_channels;
484 unsigned char ds_out_channels;
485 unsigned char ss_out_channels;
486
487 struct snd_dma_buffer capture_dma_buf;
488 struct snd_dma_buffer playback_dma_buf;
489 unsigned char *capture_buffer; /* suitably aligned address */
490 unsigned char *playback_buffer; /* suitably aligned address */
491
492 pid_t capture_pid;
493 pid_t playback_pid;
494 int running;
495 int system_sample_rate;
496 char *channel_map;
497 int dev;
498 int irq;
499 unsigned long port;
500 void __iomem *iobase;
501 struct snd_card *card;
502 struct snd_pcm *pcm;
503 struct snd_hwdep *hwdep;
504 struct pci_dev *pci;
505 struct snd_kcontrol *spdif_ctl;
506 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
507 unsigned int dds_value; /* last value written to freq register */
508 };
509
510 /* These tables map the ALSA channels 1..N to the channels that we
511 need to use in order to find the relevant channel buffer. RME
512 refer to this kind of mapping as between "the ADAT channel and
513 the DMA channel." We index it using the logical audio channel,
514 and the value is the DMA channel (i.e. channel buffer number)
515 where the data for that channel can be read/written from/to.
516 */
517
518 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
519 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
520 18, 19, 20, 21, 22, 23, 24, 25
521 };
522
523 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
524 /* Analog */
525 0, 1, 2, 3, 4, 5, 6, 7,
526 /* ADAT 2 */
527 16, 17, 18, 19, 20, 21, 22, 23,
528 /* SPDIF */
529 24, 25,
530 -1, -1, -1, -1, -1, -1, -1, -1
531 };
532
533 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
534 /* ADAT channels are remapped */
535 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
536 /* channels 12 and 13 are S/PDIF */
537 24, 25,
538 /* others don't exist */
539 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
540 };
541
542 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
543 /* ADAT channels */
544 0, 1, 2, 3, 4, 5, 6, 7,
545 /* SPDIF */
546 8, 9,
547 /* Analog */
548 10, 11,
549 /* AO4S-192 and AI4S-192 extension boards */
550 12, 13, 14, 15,
551 /* others don't exist */
552 -1, -1, -1, -1, -1, -1, -1, -1,
553 -1, -1
554 };
555
556 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
557 /* ADAT */
558 1, 3, 5, 7,
559 /* SPDIF */
560 8, 9,
561 /* Analog */
562 10, 11,
563 /* AO4S-192 and AI4S-192 extension boards */
564 12, 13, 14, 15,
565 /* others don't exist */
566 -1, -1, -1, -1, -1, -1, -1, -1,
567 -1, -1, -1, -1, -1, -1
568 };
569
570 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
571 /* ADAT is disabled in this mode */
572 /* SPDIF */
573 8, 9,
574 /* Analog */
575 10, 11,
576 /* AO4S-192 and AI4S-192 extension boards */
577 12, 13, 14, 15,
578 /* others don't exist */
579 -1, -1, -1, -1, -1, -1, -1, -1,
580 -1, -1, -1, -1, -1, -1, -1, -1,
581 -1, -1
582 };
583
584 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
585 {
586 dmab->dev.type = SNDRV_DMA_TYPE_DEV;
587 dmab->dev.dev = snd_dma_pci_data(pci);
588 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
589 size, dmab) < 0)
590 return -ENOMEM;
591 return 0;
592 }
593
594 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
595 {
596 if (dmab->area)
597 snd_dma_free_pages(dmab);
598 }
599
600
601 static const struct pci_device_id snd_hdsp_ids[] = {
602 {
603 .vendor = PCI_VENDOR_ID_XILINX,
604 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
605 .subvendor = PCI_ANY_ID,
606 .subdevice = PCI_ANY_ID,
607 }, /* RME Hammerfall-DSP */
608 { 0, },
609 };
610
611 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
612
613 /* prototypes */
614 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
615 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
616 static int snd_hdsp_enable_io (struct hdsp *hdsp);
617 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
618 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
619 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
620 static int hdsp_autosync_ref(struct hdsp *hdsp);
621 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
622 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
623
624 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
625 {
626 switch (hdsp->io_type) {
627 case Multiface:
628 case Digiface:
629 case RPM:
630 default:
631 if (hdsp->firmware_rev == 0xa)
632 return (64 * out) + (32 + (in));
633 else
634 return (52 * out) + (26 + (in));
635 case H9632:
636 return (32 * out) + (16 + (in));
637 case H9652:
638 return (52 * out) + (26 + (in));
639 }
640 }
641
642 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
643 {
644 switch (hdsp->io_type) {
645 case Multiface:
646 case Digiface:
647 case RPM:
648 default:
649 if (hdsp->firmware_rev == 0xa)
650 return (64 * out) + in;
651 else
652 return (52 * out) + in;
653 case H9632:
654 return (32 * out) + in;
655 case H9652:
656 return (52 * out) + in;
657 }
658 }
659
660 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
661 {
662 writel(val, hdsp->iobase + reg);
663 }
664
665 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
666 {
667 return readl (hdsp->iobase + reg);
668 }
669
670 static int hdsp_check_for_iobox (struct hdsp *hdsp)
671 {
672 int i;
673
674 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
675 for (i = 0; i < 500; i++) {
676 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
677 HDSP_ConfigError)) {
678 if (i) {
679 dev_dbg(hdsp->card->dev,
680 "IO box found after %d ms\n",
681 (20 * i));
682 }
683 return 0;
684 }
685 msleep(20);
686 }
687 dev_err(hdsp->card->dev, "no IO box connected!\n");
688 hdsp->state &= ~HDSP_FirmwareLoaded;
689 return -EIO;
690 }
691
692 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
693 unsigned int delay)
694 {
695 unsigned int i;
696
697 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
698 return 0;
699
700 for (i = 0; i != loops; ++i) {
701 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
702 msleep(delay);
703 else {
704 dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
705 i * delay);
706 return 0;
707 }
708 }
709
710 dev_info(hdsp->card->dev, "no IO box connected!\n");
711 hdsp->state &= ~HDSP_FirmwareLoaded;
712 return -EIO;
713 }
714
715 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
716
717 int i;
718 unsigned long flags;
719 const u32 *cache;
720
721 if (hdsp->fw_uploaded)
722 cache = hdsp->fw_uploaded;
723 else {
724 if (!hdsp->firmware)
725 return -ENODEV;
726 cache = (u32 *)hdsp->firmware->data;
727 if (!cache)
728 return -ENODEV;
729 }
730
731 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
732
733 dev_info(hdsp->card->dev, "loading firmware\n");
734
735 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
736 hdsp_write (hdsp, HDSP_fifoData, 0);
737
738 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
739 dev_info(hdsp->card->dev,
740 "timeout waiting for download preparation\n");
741 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
742 return -EIO;
743 }
744
745 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
746
747 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
748 hdsp_write(hdsp, HDSP_fifoData, cache[i]);
749 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
750 dev_info(hdsp->card->dev,
751 "timeout during firmware loading\n");
752 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
753 return -EIO;
754 }
755 }
756
757 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
758 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
759
760 ssleep(3);
761 #ifdef SNDRV_BIG_ENDIAN
762 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
763 #else
764 hdsp->control2_register = 0;
765 #endif
766 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
767 dev_info(hdsp->card->dev, "finished firmware loading\n");
768
769 }
770 if (hdsp->state & HDSP_InitializationComplete) {
771 dev_info(hdsp->card->dev,
772 "firmware loaded from cache, restoring defaults\n");
773 spin_lock_irqsave(&hdsp->lock, flags);
774 snd_hdsp_set_defaults(hdsp);
775 spin_unlock_irqrestore(&hdsp->lock, flags);
776 }
777
778 hdsp->state |= HDSP_FirmwareLoaded;
779
780 return 0;
781 }
782
783 static int hdsp_get_iobox_version (struct hdsp *hdsp)
784 {
785 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
786
787 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
788 hdsp_write(hdsp, HDSP_fifoData, 0);
789
790 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
791 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
792 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
793 }
794
795 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
796 hdsp_write (hdsp, HDSP_fifoData, 0);
797 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
798 goto set_multi;
799
800 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
801 hdsp_write(hdsp, HDSP_fifoData, 0);
802 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
803 hdsp->io_type = Digiface;
804 dev_info(hdsp->card->dev, "Digiface found\n");
805 return 0;
806 }
807
808 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
809 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
810 hdsp_write(hdsp, HDSP_fifoData, 0);
811 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)
812 goto set_multi;
813
814 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
815 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
816 hdsp_write(hdsp, HDSP_fifoData, 0);
817 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
818 goto set_multi;
819
820 hdsp->io_type = RPM;
821 dev_info(hdsp->card->dev, "RPM found\n");
822 return 0;
823 } else {
824 /* firmware was already loaded, get iobox type */
825 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
826 hdsp->io_type = RPM;
827 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
828 hdsp->io_type = Multiface;
829 else
830 hdsp->io_type = Digiface;
831 }
832 return 0;
833
834 set_multi:
835 hdsp->io_type = Multiface;
836 dev_info(hdsp->card->dev, "Multiface found\n");
837 return 0;
838 }
839
840
841 static int hdsp_request_fw_loader(struct hdsp *hdsp);
842
843 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
844 {
845 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
846 return 0;
847 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
848 hdsp->state &= ~HDSP_FirmwareLoaded;
849 if (! load_on_demand)
850 return -EIO;
851 dev_err(hdsp->card->dev, "firmware not present.\n");
852 /* try to load firmware */
853 if (! (hdsp->state & HDSP_FirmwareCached)) {
854 if (! hdsp_request_fw_loader(hdsp))
855 return 0;
856 dev_err(hdsp->card->dev,
857 "No firmware loaded nor cached, please upload firmware.\n");
858 return -EIO;
859 }
860 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
861 dev_err(hdsp->card->dev,
862 "Firmware loading from cache failed, please upload manually.\n");
863 return -EIO;
864 }
865 }
866 return 0;
867 }
868
869
870 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
871 {
872 int i;
873
874 /* the fifoStatus registers reports on how many words
875 are available in the command FIFO.
876 */
877
878 for (i = 0; i < timeout; i++) {
879
880 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
881 return 0;
882
883 /* not very friendly, but we only do this during a firmware
884 load and changing the mixer, so we just put up with it.
885 */
886
887 udelay (100);
888 }
889
890 dev_warn(hdsp->card->dev,
891 "wait for FIFO status <= %d failed after %d iterations\n",
892 count, timeout);
893 return -1;
894 }
895
896 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
897 {
898 if (addr >= HDSP_MATRIX_MIXER_SIZE)
899 return 0;
900
901 return hdsp->mixer_matrix[addr];
902 }
903
904 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
905 {
906 unsigned int ad;
907
908 if (addr >= HDSP_MATRIX_MIXER_SIZE)
909 return -1;
910
911 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
912
913 /* from martin bjornsen:
914
915 "You can only write dwords to the
916 mixer memory which contain two
917 mixer values in the low and high
918 word. So if you want to change
919 value 0 you have to read value 1
920 from the cache and write both to
921 the first dword in the mixer
922 memory."
923 */
924
925 if (hdsp->io_type == H9632 && addr >= 512)
926 return 0;
927
928 if (hdsp->io_type == H9652 && addr >= 1352)
929 return 0;
930
931 hdsp->mixer_matrix[addr] = data;
932
933
934 /* `addr' addresses a 16-bit wide address, but
935 the address space accessed via hdsp_write
936 uses byte offsets. put another way, addr
937 varies from 0 to 1351, but to access the
938 corresponding memory location, we need
939 to access 0 to 2703 ...
940 */
941 ad = addr/2;
942
943 hdsp_write (hdsp, 4096 + (ad*4),
944 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
945 hdsp->mixer_matrix[addr&0x7fe]);
946
947 return 0;
948
949 } else {
950
951 ad = (addr << 16) + data;
952
953 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
954 return -1;
955
956 hdsp_write (hdsp, HDSP_fifoData, ad);
957 hdsp->mixer_matrix[addr] = data;
958
959 }
960
961 return 0;
962 }
963
964 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
965 {
966 unsigned long flags;
967 int ret = 1;
968
969 spin_lock_irqsave(&hdsp->lock, flags);
970 if ((hdsp->playback_pid != hdsp->capture_pid) &&
971 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
972 ret = 0;
973 spin_unlock_irqrestore(&hdsp->lock, flags);
974 return ret;
975 }
976
977 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
978 {
979 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
980 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
981
982 /* For the 9632, the mask is different */
983 if (hdsp->io_type == H9632)
984 rate_bits = (status & HDSP_spdifFrequencyMask_9632);
985
986 if (status & HDSP_SPDIFErrorFlag)
987 return 0;
988
989 switch (rate_bits) {
990 case HDSP_spdifFrequency32KHz: return 32000;
991 case HDSP_spdifFrequency44_1KHz: return 44100;
992 case HDSP_spdifFrequency48KHz: return 48000;
993 case HDSP_spdifFrequency64KHz: return 64000;
994 case HDSP_spdifFrequency88_2KHz: return 88200;
995 case HDSP_spdifFrequency96KHz: return 96000;
996 case HDSP_spdifFrequency128KHz:
997 if (hdsp->io_type == H9632) return 128000;
998 break;
999 case HDSP_spdifFrequency176_4KHz:
1000 if (hdsp->io_type == H9632) return 176400;
1001 break;
1002 case HDSP_spdifFrequency192KHz:
1003 if (hdsp->io_type == H9632) return 192000;
1004 break;
1005 default:
1006 break;
1007 }
1008 dev_warn(hdsp->card->dev,
1009 "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
1010 rate_bits, status);
1011 return 0;
1012 }
1013
1014 static int hdsp_external_sample_rate(struct hdsp *hdsp)
1015 {
1016 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
1017 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
1018
1019 /* For the 9632 card, there seems to be no bit for indicating external
1020 * sample rate greater than 96kHz. The card reports the corresponding
1021 * single speed. So the best means seems to get spdif rate when
1022 * autosync reference is spdif */
1023 if (hdsp->io_type == H9632 &&
1024 hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1025 return hdsp_spdif_sample_rate(hdsp);
1026
1027 switch (rate_bits) {
1028 case HDSP_systemFrequency32: return 32000;
1029 case HDSP_systemFrequency44_1: return 44100;
1030 case HDSP_systemFrequency48: return 48000;
1031 case HDSP_systemFrequency64: return 64000;
1032 case HDSP_systemFrequency88_2: return 88200;
1033 case HDSP_systemFrequency96: return 96000;
1034 default:
1035 return 0;
1036 }
1037 }
1038
1039 static void hdsp_compute_period_size(struct hdsp *hdsp)
1040 {
1041 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1042 }
1043
1044 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1045 {
1046 int position;
1047
1048 position = hdsp_read(hdsp, HDSP_statusRegister);
1049
1050 if (!hdsp->precise_ptr)
1051 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1052
1053 position &= HDSP_BufferPositionMask;
1054 position /= 4;
1055 position &= (hdsp->period_bytes/2) - 1;
1056 return position;
1057 }
1058
1059 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1060 {
1061 hdsp_write (hdsp, HDSP_resetPointer, 0);
1062 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1063 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1064 * requires (?) to write again DDS value after a reset pointer
1065 * (at least, it works like this) */
1066 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1067 }
1068
1069 static void hdsp_start_audio(struct hdsp *s)
1070 {
1071 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1072 hdsp_write(s, HDSP_controlRegister, s->control_register);
1073 }
1074
1075 static void hdsp_stop_audio(struct hdsp *s)
1076 {
1077 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1078 hdsp_write(s, HDSP_controlRegister, s->control_register);
1079 }
1080
1081 static void hdsp_silence_playback(struct hdsp *hdsp)
1082 {
1083 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1084 }
1085
1086 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1087 {
1088 int n;
1089
1090 spin_lock_irq(&s->lock);
1091
1092 frames >>= 7;
1093 n = 0;
1094 while (frames) {
1095 n++;
1096 frames >>= 1;
1097 }
1098
1099 s->control_register &= ~HDSP_LatencyMask;
1100 s->control_register |= hdsp_encode_latency(n);
1101
1102 hdsp_write(s, HDSP_controlRegister, s->control_register);
1103
1104 hdsp_compute_period_size(s);
1105
1106 spin_unlock_irq(&s->lock);
1107
1108 return 0;
1109 }
1110
1111 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1112 {
1113 u64 n;
1114
1115 if (rate >= 112000)
1116 rate /= 4;
1117 else if (rate >= 56000)
1118 rate /= 2;
1119
1120 n = DDS_NUMERATOR;
1121 n = div_u64(n, rate);
1122 /* n should be less than 2^32 for being written to FREQ register */
1123 snd_BUG_ON(n >> 32);
1124 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1125 value to write it after a reset */
1126 hdsp->dds_value = n;
1127 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1128 }
1129
1130 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1131 {
1132 int reject_if_open = 0;
1133 int current_rate;
1134 int rate_bits;
1135
1136 /* ASSUMPTION: hdsp->lock is either held, or
1137 there is no need for it (e.g. during module
1138 initialization).
1139 */
1140
1141 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1142 if (called_internally) {
1143 /* request from ctl or card initialization */
1144 dev_err(hdsp->card->dev,
1145 "device is not running as a clock master: cannot set sample rate.\n");
1146 return -1;
1147 } else {
1148 /* hw_param request while in AutoSync mode */
1149 int external_freq = hdsp_external_sample_rate(hdsp);
1150 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1151
1152 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1153 dev_info(hdsp->card->dev,
1154 "Detected ADAT in double speed mode\n");
1155 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1156 dev_info(hdsp->card->dev,
1157 "Detected ADAT in quad speed mode\n");
1158 else if (rate != external_freq) {
1159 dev_info(hdsp->card->dev,
1160 "No AutoSync source for requested rate\n");
1161 return -1;
1162 }
1163 }
1164 }
1165
1166 current_rate = hdsp->system_sample_rate;
1167
1168 /* Changing from a "single speed" to a "double speed" rate is
1169 not allowed if any substreams are open. This is because
1170 such a change causes a shift in the location of
1171 the DMA buffers and a reduction in the number of available
1172 buffers.
1173
1174 Note that a similar but essentially insoluble problem
1175 exists for externally-driven rate changes. All we can do
1176 is to flag rate changes in the read/write routines. */
1177
1178 if (rate > 96000 && hdsp->io_type != H9632)
1179 return -EINVAL;
1180
1181 switch (rate) {
1182 case 32000:
1183 if (current_rate > 48000)
1184 reject_if_open = 1;
1185 rate_bits = HDSP_Frequency32KHz;
1186 break;
1187 case 44100:
1188 if (current_rate > 48000)
1189 reject_if_open = 1;
1190 rate_bits = HDSP_Frequency44_1KHz;
1191 break;
1192 case 48000:
1193 if (current_rate > 48000)
1194 reject_if_open = 1;
1195 rate_bits = HDSP_Frequency48KHz;
1196 break;
1197 case 64000:
1198 if (current_rate <= 48000 || current_rate > 96000)
1199 reject_if_open = 1;
1200 rate_bits = HDSP_Frequency64KHz;
1201 break;
1202 case 88200:
1203 if (current_rate <= 48000 || current_rate > 96000)
1204 reject_if_open = 1;
1205 rate_bits = HDSP_Frequency88_2KHz;
1206 break;
1207 case 96000:
1208 if (current_rate <= 48000 || current_rate > 96000)
1209 reject_if_open = 1;
1210 rate_bits = HDSP_Frequency96KHz;
1211 break;
1212 case 128000:
1213 if (current_rate < 128000)
1214 reject_if_open = 1;
1215 rate_bits = HDSP_Frequency128KHz;
1216 break;
1217 case 176400:
1218 if (current_rate < 128000)
1219 reject_if_open = 1;
1220 rate_bits = HDSP_Frequency176_4KHz;
1221 break;
1222 case 192000:
1223 if (current_rate < 128000)
1224 reject_if_open = 1;
1225 rate_bits = HDSP_Frequency192KHz;
1226 break;
1227 default:
1228 return -EINVAL;
1229 }
1230
1231 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1232 dev_warn(hdsp->card->dev,
1233 "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1234 hdsp->capture_pid,
1235 hdsp->playback_pid);
1236 return -EBUSY;
1237 }
1238
1239 hdsp->control_register &= ~HDSP_FrequencyMask;
1240 hdsp->control_register |= rate_bits;
1241 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1242
1243 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1244 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1245 hdsp_set_dds_value(hdsp, rate);
1246
1247 if (rate >= 128000) {
1248 hdsp->channel_map = channel_map_H9632_qs;
1249 } else if (rate > 48000) {
1250 if (hdsp->io_type == H9632)
1251 hdsp->channel_map = channel_map_H9632_ds;
1252 else
1253 hdsp->channel_map = channel_map_ds;
1254 } else {
1255 switch (hdsp->io_type) {
1256 case RPM:
1257 case Multiface:
1258 hdsp->channel_map = channel_map_mf_ss;
1259 break;
1260 case Digiface:
1261 case H9652:
1262 hdsp->channel_map = channel_map_df_ss;
1263 break;
1264 case H9632:
1265 hdsp->channel_map = channel_map_H9632_ss;
1266 break;
1267 default:
1268 /* should never happen */
1269 break;
1270 }
1271 }
1272
1273 hdsp->system_sample_rate = rate;
1274
1275 return 0;
1276 }
1277
1278 /*----------------------------------------------------------------------------
1279 MIDI
1280 ----------------------------------------------------------------------------*/
1281
1282 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1283 {
1284 /* the hardware already does the relevant bit-mask with 0xff */
1285 if (id)
1286 return hdsp_read(hdsp, HDSP_midiDataIn1);
1287 else
1288 return hdsp_read(hdsp, HDSP_midiDataIn0);
1289 }
1290
1291 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1292 {
1293 /* the hardware already does the relevant bit-mask with 0xff */
1294 if (id)
1295 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1296 else
1297 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1298 }
1299
1300 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1301 {
1302 if (id)
1303 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1304 else
1305 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1306 }
1307
1308 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1309 {
1310 int fifo_bytes_used;
1311
1312 if (id)
1313 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1314 else
1315 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1316
1317 if (fifo_bytes_used < 128)
1318 return 128 - fifo_bytes_used;
1319 else
1320 return 0;
1321 }
1322
1323 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1324 {
1325 while (snd_hdsp_midi_input_available (hdsp, id))
1326 snd_hdsp_midi_read_byte (hdsp, id);
1327 }
1328
1329 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1330 {
1331 unsigned long flags;
1332 int n_pending;
1333 int to_write;
1334 int i;
1335 unsigned char buf[128];
1336
1337 /* Output is not interrupt driven */
1338
1339 spin_lock_irqsave (&hmidi->lock, flags);
1340 if (hmidi->output) {
1341 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1342 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1343 if (n_pending > (int)sizeof (buf))
1344 n_pending = sizeof (buf);
1345
1346 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1347 for (i = 0; i < to_write; ++i)
1348 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1349 }
1350 }
1351 }
1352 }
1353 spin_unlock_irqrestore (&hmidi->lock, flags);
1354 return 0;
1355 }
1356
1357 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1358 {
1359 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1360 unsigned long flags;
1361 int n_pending;
1362 int i;
1363
1364 spin_lock_irqsave (&hmidi->lock, flags);
1365 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1366 if (hmidi->input) {
1367 if (n_pending > (int)sizeof (buf))
1368 n_pending = sizeof (buf);
1369 for (i = 0; i < n_pending; ++i)
1370 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1371 if (n_pending)
1372 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1373 } else {
1374 /* flush the MIDI input FIFO */
1375 while (--n_pending)
1376 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1377 }
1378 }
1379 hmidi->pending = 0;
1380 if (hmidi->id)
1381 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1382 else
1383 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1384 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1385 spin_unlock_irqrestore (&hmidi->lock, flags);
1386 return snd_hdsp_midi_output_write (hmidi);
1387 }
1388
1389 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1390 {
1391 struct hdsp *hdsp;
1392 struct hdsp_midi *hmidi;
1393 unsigned long flags;
1394 u32 ie;
1395
1396 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1397 hdsp = hmidi->hdsp;
1398 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1399 spin_lock_irqsave (&hdsp->lock, flags);
1400 if (up) {
1401 if (!(hdsp->control_register & ie)) {
1402 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1403 hdsp->control_register |= ie;
1404 }
1405 } else {
1406 hdsp->control_register &= ~ie;
1407 tasklet_kill(&hdsp->midi_tasklet);
1408 }
1409
1410 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1411 spin_unlock_irqrestore (&hdsp->lock, flags);
1412 }
1413
1414 static void snd_hdsp_midi_output_timer(struct timer_list *t)
1415 {
1416 struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);
1417 unsigned long flags;
1418
1419 snd_hdsp_midi_output_write(hmidi);
1420 spin_lock_irqsave (&hmidi->lock, flags);
1421
1422 /* this does not bump hmidi->istimer, because the
1423 kernel automatically removed the timer when it
1424 expired, and we are now adding it back, thus
1425 leaving istimer wherever it was set before.
1426 */
1427
1428 if (hmidi->istimer)
1429 mod_timer(&hmidi->timer, 1 + jiffies);
1430
1431 spin_unlock_irqrestore (&hmidi->lock, flags);
1432 }
1433
1434 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1435 {
1436 struct hdsp_midi *hmidi;
1437 unsigned long flags;
1438
1439 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1440 spin_lock_irqsave (&hmidi->lock, flags);
1441 if (up) {
1442 if (!hmidi->istimer) {
1443 timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,
1444 0);
1445 mod_timer(&hmidi->timer, 1 + jiffies);
1446 hmidi->istimer++;
1447 }
1448 } else {
1449 if (hmidi->istimer && --hmidi->istimer <= 0)
1450 del_timer (&hmidi->timer);
1451 }
1452 spin_unlock_irqrestore (&hmidi->lock, flags);
1453 if (up)
1454 snd_hdsp_midi_output_write(hmidi);
1455 }
1456
1457 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1458 {
1459 struct hdsp_midi *hmidi;
1460
1461 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1462 spin_lock_irq (&hmidi->lock);
1463 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1464 hmidi->input = substream;
1465 spin_unlock_irq (&hmidi->lock);
1466
1467 return 0;
1468 }
1469
1470 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1471 {
1472 struct hdsp_midi *hmidi;
1473
1474 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1475 spin_lock_irq (&hmidi->lock);
1476 hmidi->output = substream;
1477 spin_unlock_irq (&hmidi->lock);
1478
1479 return 0;
1480 }
1481
1482 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1483 {
1484 struct hdsp_midi *hmidi;
1485
1486 snd_hdsp_midi_input_trigger (substream, 0);
1487
1488 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1489 spin_lock_irq (&hmidi->lock);
1490 hmidi->input = NULL;
1491 spin_unlock_irq (&hmidi->lock);
1492
1493 return 0;
1494 }
1495
1496 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1497 {
1498 struct hdsp_midi *hmidi;
1499
1500 snd_hdsp_midi_output_trigger (substream, 0);
1501
1502 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1503 spin_lock_irq (&hmidi->lock);
1504 hmidi->output = NULL;
1505 spin_unlock_irq (&hmidi->lock);
1506
1507 return 0;
1508 }
1509
1510 static const struct snd_rawmidi_ops snd_hdsp_midi_output =
1511 {
1512 .open = snd_hdsp_midi_output_open,
1513 .close = snd_hdsp_midi_output_close,
1514 .trigger = snd_hdsp_midi_output_trigger,
1515 };
1516
1517 static const struct snd_rawmidi_ops snd_hdsp_midi_input =
1518 {
1519 .open = snd_hdsp_midi_input_open,
1520 .close = snd_hdsp_midi_input_close,
1521 .trigger = snd_hdsp_midi_input_trigger,
1522 };
1523
1524 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1525 {
1526 char buf[40];
1527
1528 hdsp->midi[id].id = id;
1529 hdsp->midi[id].rmidi = NULL;
1530 hdsp->midi[id].input = NULL;
1531 hdsp->midi[id].output = NULL;
1532 hdsp->midi[id].hdsp = hdsp;
1533 hdsp->midi[id].istimer = 0;
1534 hdsp->midi[id].pending = 0;
1535 spin_lock_init (&hdsp->midi[id].lock);
1536
1537 snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1538 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1539 return -1;
1540
1541 sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1542 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1543
1544 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1545 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1546
1547 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1548 SNDRV_RAWMIDI_INFO_INPUT |
1549 SNDRV_RAWMIDI_INFO_DUPLEX;
1550
1551 return 0;
1552 }
1553
1554 /*-----------------------------------------------------------------------------
1555 Control Interface
1556 ----------------------------------------------------------------------------*/
1557
1558 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1559 {
1560 u32 val = 0;
1561 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1562 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1563 if (val & HDSP_SPDIFProfessional)
1564 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1565 else
1566 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1567 return val;
1568 }
1569
1570 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1571 {
1572 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1573 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1574 if (val & HDSP_SPDIFProfessional)
1575 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1576 else
1577 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1578 }
1579
1580 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1581 {
1582 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1583 uinfo->count = 1;
1584 return 0;
1585 }
1586
1587 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1588 {
1589 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1590
1591 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1592 return 0;
1593 }
1594
1595 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1596 {
1597 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1598 int change;
1599 u32 val;
1600
1601 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1602 spin_lock_irq(&hdsp->lock);
1603 change = val != hdsp->creg_spdif;
1604 hdsp->creg_spdif = val;
1605 spin_unlock_irq(&hdsp->lock);
1606 return change;
1607 }
1608
1609 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1610 {
1611 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1612 uinfo->count = 1;
1613 return 0;
1614 }
1615
1616 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1617 {
1618 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1619
1620 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1621 return 0;
1622 }
1623
1624 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1625 {
1626 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1627 int change;
1628 u32 val;
1629
1630 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1631 spin_lock_irq(&hdsp->lock);
1632 change = val != hdsp->creg_spdif_stream;
1633 hdsp->creg_spdif_stream = val;
1634 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1635 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1636 spin_unlock_irq(&hdsp->lock);
1637 return change;
1638 }
1639
1640 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1641 {
1642 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1643 uinfo->count = 1;
1644 return 0;
1645 }
1646
1647 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1648 {
1649 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1650 return 0;
1651 }
1652
1653 #define HDSP_SPDIF_IN(xname, xindex) \
1654 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1655 .name = xname, \
1656 .index = xindex, \
1657 .info = snd_hdsp_info_spdif_in, \
1658 .get = snd_hdsp_get_spdif_in, \
1659 .put = snd_hdsp_put_spdif_in }
1660
1661 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1662 {
1663 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1664 }
1665
1666 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1667 {
1668 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1669 hdsp->control_register |= hdsp_encode_spdif_in(in);
1670 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1671 return 0;
1672 }
1673
1674 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1675 {
1676 static const char * const texts[4] = {
1677 "Optical", "Coaxial", "Internal", "AES"
1678 };
1679 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1680
1681 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1682 texts);
1683 }
1684
1685 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1686 {
1687 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1688
1689 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1690 return 0;
1691 }
1692
1693 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1694 {
1695 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1696 int change;
1697 unsigned int val;
1698
1699 if (!snd_hdsp_use_is_exclusive(hdsp))
1700 return -EBUSY;
1701 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1702 spin_lock_irq(&hdsp->lock);
1703 change = val != hdsp_spdif_in(hdsp);
1704 if (change)
1705 hdsp_set_spdif_input(hdsp, val);
1706 spin_unlock_irq(&hdsp->lock);
1707 return change;
1708 }
1709
1710 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1711 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1712 .name = xname, \
1713 .private_value = xindex, \
1714 .info = snd_hdsp_info_toggle_setting, \
1715 .get = snd_hdsp_get_toggle_setting, \
1716 .put = snd_hdsp_put_toggle_setting \
1717 }
1718
1719 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1720 {
1721 return (hdsp->control_register & regmask) ? 1 : 0;
1722 }
1723
1724 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1725 {
1726 if (out)
1727 hdsp->control_register |= regmask;
1728 else
1729 hdsp->control_register &= ~regmask;
1730 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1731
1732 return 0;
1733 }
1734
1735 #define snd_hdsp_info_toggle_setting snd_ctl_boolean_mono_info
1736
1737 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1738 struct snd_ctl_elem_value *ucontrol)
1739 {
1740 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1741 u32 regmask = kcontrol->private_value;
1742
1743 spin_lock_irq(&hdsp->lock);
1744 ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1745 spin_unlock_irq(&hdsp->lock);
1746 return 0;
1747 }
1748
1749 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1750 struct snd_ctl_elem_value *ucontrol)
1751 {
1752 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1753 u32 regmask = kcontrol->private_value;
1754 int change;
1755 unsigned int val;
1756
1757 if (!snd_hdsp_use_is_exclusive(hdsp))
1758 return -EBUSY;
1759 val = ucontrol->value.integer.value[0] & 1;
1760 spin_lock_irq(&hdsp->lock);
1761 change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1762 if (change)
1763 hdsp_set_toggle_setting(hdsp, regmask, val);
1764 spin_unlock_irq(&hdsp->lock);
1765 return change;
1766 }
1767
1768 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1769 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1770 .name = xname, \
1771 .index = xindex, \
1772 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1773 .info = snd_hdsp_info_spdif_sample_rate, \
1774 .get = snd_hdsp_get_spdif_sample_rate \
1775 }
1776
1777 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1778 {
1779 static const char * const texts[] = {
1780 "32000", "44100", "48000", "64000", "88200", "96000",
1781 "None", "128000", "176400", "192000"
1782 };
1783 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1784
1785 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1786 texts);
1787 }
1788
1789 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1790 {
1791 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1792
1793 switch (hdsp_spdif_sample_rate(hdsp)) {
1794 case 32000:
1795 ucontrol->value.enumerated.item[0] = 0;
1796 break;
1797 case 44100:
1798 ucontrol->value.enumerated.item[0] = 1;
1799 break;
1800 case 48000:
1801 ucontrol->value.enumerated.item[0] = 2;
1802 break;
1803 case 64000:
1804 ucontrol->value.enumerated.item[0] = 3;
1805 break;
1806 case 88200:
1807 ucontrol->value.enumerated.item[0] = 4;
1808 break;
1809 case 96000:
1810 ucontrol->value.enumerated.item[0] = 5;
1811 break;
1812 case 128000:
1813 ucontrol->value.enumerated.item[0] = 7;
1814 break;
1815 case 176400:
1816 ucontrol->value.enumerated.item[0] = 8;
1817 break;
1818 case 192000:
1819 ucontrol->value.enumerated.item[0] = 9;
1820 break;
1821 default:
1822 ucontrol->value.enumerated.item[0] = 6;
1823 }
1824 return 0;
1825 }
1826
1827 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1828 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1829 .name = xname, \
1830 .index = xindex, \
1831 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1832 .info = snd_hdsp_info_system_sample_rate, \
1833 .get = snd_hdsp_get_system_sample_rate \
1834 }
1835
1836 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1837 {
1838 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1839 uinfo->count = 1;
1840 return 0;
1841 }
1842
1843 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1844 {
1845 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1846
1847 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1848 return 0;
1849 }
1850
1851 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1852 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1853 .name = xname, \
1854 .index = xindex, \
1855 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1856 .info = snd_hdsp_info_autosync_sample_rate, \
1857 .get = snd_hdsp_get_autosync_sample_rate \
1858 }
1859
1860 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1861 {
1862 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1863 static const char * const texts[] = {
1864 "32000", "44100", "48000", "64000", "88200", "96000",
1865 "None", "128000", "176400", "192000"
1866 };
1867
1868 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1869 texts);
1870 }
1871
1872 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1873 {
1874 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1875
1876 switch (hdsp_external_sample_rate(hdsp)) {
1877 case 32000:
1878 ucontrol->value.enumerated.item[0] = 0;
1879 break;
1880 case 44100:
1881 ucontrol->value.enumerated.item[0] = 1;
1882 break;
1883 case 48000:
1884 ucontrol->value.enumerated.item[0] = 2;
1885 break;
1886 case 64000:
1887 ucontrol->value.enumerated.item[0] = 3;
1888 break;
1889 case 88200:
1890 ucontrol->value.enumerated.item[0] = 4;
1891 break;
1892 case 96000:
1893 ucontrol->value.enumerated.item[0] = 5;
1894 break;
1895 case 128000:
1896 ucontrol->value.enumerated.item[0] = 7;
1897 break;
1898 case 176400:
1899 ucontrol->value.enumerated.item[0] = 8;
1900 break;
1901 case 192000:
1902 ucontrol->value.enumerated.item[0] = 9;
1903 break;
1904 default:
1905 ucontrol->value.enumerated.item[0] = 6;
1906 }
1907 return 0;
1908 }
1909
1910 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1911 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1912 .name = xname, \
1913 .index = xindex, \
1914 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1915 .info = snd_hdsp_info_system_clock_mode, \
1916 .get = snd_hdsp_get_system_clock_mode \
1917 }
1918
1919 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1920 {
1921 if (hdsp->control_register & HDSP_ClockModeMaster)
1922 return 0;
1923 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1924 return 0;
1925 return 1;
1926 }
1927
1928 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1929 {
1930 static const char * const texts[] = {"Master", "Slave" };
1931
1932 return snd_ctl_enum_info(uinfo, 1, 2, texts);
1933 }
1934
1935 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1936 {
1937 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1938
1939 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1940 return 0;
1941 }
1942
1943 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1944 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1945 .name = xname, \
1946 .index = xindex, \
1947 .info = snd_hdsp_info_clock_source, \
1948 .get = snd_hdsp_get_clock_source, \
1949 .put = snd_hdsp_put_clock_source \
1950 }
1951
1952 static int hdsp_clock_source(struct hdsp *hdsp)
1953 {
1954 if (hdsp->control_register & HDSP_ClockModeMaster) {
1955 switch (hdsp->system_sample_rate) {
1956 case 32000:
1957 return 1;
1958 case 44100:
1959 return 2;
1960 case 48000:
1961 return 3;
1962 case 64000:
1963 return 4;
1964 case 88200:
1965 return 5;
1966 case 96000:
1967 return 6;
1968 case 128000:
1969 return 7;
1970 case 176400:
1971 return 8;
1972 case 192000:
1973 return 9;
1974 default:
1975 return 3;
1976 }
1977 } else {
1978 return 0;
1979 }
1980 }
1981
1982 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1983 {
1984 int rate;
1985 switch (mode) {
1986 case HDSP_CLOCK_SOURCE_AUTOSYNC:
1987 if (hdsp_external_sample_rate(hdsp) != 0) {
1988 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1989 hdsp->control_register &= ~HDSP_ClockModeMaster;
1990 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1991 return 0;
1992 }
1993 }
1994 return -1;
1995 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1996 rate = 32000;
1997 break;
1998 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1999 rate = 44100;
2000 break;
2001 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2002 rate = 48000;
2003 break;
2004 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2005 rate = 64000;
2006 break;
2007 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2008 rate = 88200;
2009 break;
2010 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2011 rate = 96000;
2012 break;
2013 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2014 rate = 128000;
2015 break;
2016 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2017 rate = 176400;
2018 break;
2019 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2020 rate = 192000;
2021 break;
2022 default:
2023 rate = 48000;
2024 }
2025 hdsp->control_register |= HDSP_ClockModeMaster;
2026 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2027 hdsp_set_rate(hdsp, rate, 1);
2028 return 0;
2029 }
2030
2031 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2032 {
2033 static const char * const texts[] = {
2034 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2035 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2036 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2037 "Internal 192.0 KHz"
2038 };
2039 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2040
2041 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2042 texts);
2043 }
2044
2045 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2046 {
2047 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2048
2049 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2050 return 0;
2051 }
2052
2053 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2054 {
2055 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2056 int change;
2057 int val;
2058
2059 if (!snd_hdsp_use_is_exclusive(hdsp))
2060 return -EBUSY;
2061 val = ucontrol->value.enumerated.item[0];
2062 if (val < 0) val = 0;
2063 if (hdsp->io_type == H9632) {
2064 if (val > 9)
2065 val = 9;
2066 } else {
2067 if (val > 6)
2068 val = 6;
2069 }
2070 spin_lock_irq(&hdsp->lock);
2071 if (val != hdsp_clock_source(hdsp))
2072 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2073 else
2074 change = 0;
2075 spin_unlock_irq(&hdsp->lock);
2076 return change;
2077 }
2078
2079 #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
2080
2081 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2082 {
2083 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2084
2085 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2086 return 0;
2087 }
2088
2089 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2090 {
2091 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2092 int change;
2093
2094 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2095 if (change)
2096 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2097 return change;
2098 }
2099
2100 #define HDSP_DA_GAIN(xname, xindex) \
2101 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2102 .name = xname, \
2103 .index = xindex, \
2104 .info = snd_hdsp_info_da_gain, \
2105 .get = snd_hdsp_get_da_gain, \
2106 .put = snd_hdsp_put_da_gain \
2107 }
2108
2109 static int hdsp_da_gain(struct hdsp *hdsp)
2110 {
2111 switch (hdsp->control_register & HDSP_DAGainMask) {
2112 case HDSP_DAGainHighGain:
2113 return 0;
2114 case HDSP_DAGainPlus4dBu:
2115 return 1;
2116 case HDSP_DAGainMinus10dBV:
2117 return 2;
2118 default:
2119 return 1;
2120 }
2121 }
2122
2123 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2124 {
2125 hdsp->control_register &= ~HDSP_DAGainMask;
2126 switch (mode) {
2127 case 0:
2128 hdsp->control_register |= HDSP_DAGainHighGain;
2129 break;
2130 case 1:
2131 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2132 break;
2133 case 2:
2134 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2135 break;
2136 default:
2137 return -1;
2138
2139 }
2140 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2141 return 0;
2142 }
2143
2144 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2145 {
2146 static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2147
2148 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2149 }
2150
2151 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2152 {
2153 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2154
2155 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2156 return 0;
2157 }
2158
2159 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2160 {
2161 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2162 int change;
2163 int val;
2164
2165 if (!snd_hdsp_use_is_exclusive(hdsp))
2166 return -EBUSY;
2167 val = ucontrol->value.enumerated.item[0];
2168 if (val < 0) val = 0;
2169 if (val > 2) val = 2;
2170 spin_lock_irq(&hdsp->lock);
2171 if (val != hdsp_da_gain(hdsp))
2172 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2173 else
2174 change = 0;
2175 spin_unlock_irq(&hdsp->lock);
2176 return change;
2177 }
2178
2179 #define HDSP_AD_GAIN(xname, xindex) \
2180 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2181 .name = xname, \
2182 .index = xindex, \
2183 .info = snd_hdsp_info_ad_gain, \
2184 .get = snd_hdsp_get_ad_gain, \
2185 .put = snd_hdsp_put_ad_gain \
2186 }
2187
2188 static int hdsp_ad_gain(struct hdsp *hdsp)
2189 {
2190 switch (hdsp->control_register & HDSP_ADGainMask) {
2191 case HDSP_ADGainMinus10dBV:
2192 return 0;
2193 case HDSP_ADGainPlus4dBu:
2194 return 1;
2195 case HDSP_ADGainLowGain:
2196 return 2;
2197 default:
2198 return 1;
2199 }
2200 }
2201
2202 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2203 {
2204 hdsp->control_register &= ~HDSP_ADGainMask;
2205 switch (mode) {
2206 case 0:
2207 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2208 break;
2209 case 1:
2210 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2211 break;
2212 case 2:
2213 hdsp->control_register |= HDSP_ADGainLowGain;
2214 break;
2215 default:
2216 return -1;
2217
2218 }
2219 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2220 return 0;
2221 }
2222
2223 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2224 {
2225 static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2226
2227 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2228 }
2229
2230 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2231 {
2232 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2233
2234 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2235 return 0;
2236 }
2237
2238 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2239 {
2240 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2241 int change;
2242 int val;
2243
2244 if (!snd_hdsp_use_is_exclusive(hdsp))
2245 return -EBUSY;
2246 val = ucontrol->value.enumerated.item[0];
2247 if (val < 0) val = 0;
2248 if (val > 2) val = 2;
2249 spin_lock_irq(&hdsp->lock);
2250 if (val != hdsp_ad_gain(hdsp))
2251 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2252 else
2253 change = 0;
2254 spin_unlock_irq(&hdsp->lock);
2255 return change;
2256 }
2257
2258 #define HDSP_PHONE_GAIN(xname, xindex) \
2259 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2260 .name = xname, \
2261 .index = xindex, \
2262 .info = snd_hdsp_info_phone_gain, \
2263 .get = snd_hdsp_get_phone_gain, \
2264 .put = snd_hdsp_put_phone_gain \
2265 }
2266
2267 static int hdsp_phone_gain(struct hdsp *hdsp)
2268 {
2269 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2270 case HDSP_PhoneGain0dB:
2271 return 0;
2272 case HDSP_PhoneGainMinus6dB:
2273 return 1;
2274 case HDSP_PhoneGainMinus12dB:
2275 return 2;
2276 default:
2277 return 0;
2278 }
2279 }
2280
2281 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2282 {
2283 hdsp->control_register &= ~HDSP_PhoneGainMask;
2284 switch (mode) {
2285 case 0:
2286 hdsp->control_register |= HDSP_PhoneGain0dB;
2287 break;
2288 case 1:
2289 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2290 break;
2291 case 2:
2292 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2293 break;
2294 default:
2295 return -1;
2296
2297 }
2298 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2299 return 0;
2300 }
2301
2302 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2303 {
2304 static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2305
2306 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2307 }
2308
2309 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2310 {
2311 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2312
2313 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2314 return 0;
2315 }
2316
2317 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2318 {
2319 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2320 int change;
2321 int val;
2322
2323 if (!snd_hdsp_use_is_exclusive(hdsp))
2324 return -EBUSY;
2325 val = ucontrol->value.enumerated.item[0];
2326 if (val < 0) val = 0;
2327 if (val > 2) val = 2;
2328 spin_lock_irq(&hdsp->lock);
2329 if (val != hdsp_phone_gain(hdsp))
2330 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2331 else
2332 change = 0;
2333 spin_unlock_irq(&hdsp->lock);
2334 return change;
2335 }
2336
2337 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2338 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2339 .name = xname, \
2340 .index = xindex, \
2341 .info = snd_hdsp_info_pref_sync_ref, \
2342 .get = snd_hdsp_get_pref_sync_ref, \
2343 .put = snd_hdsp_put_pref_sync_ref \
2344 }
2345
2346 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2347 {
2348 /* Notice that this looks at the requested sync source,
2349 not the one actually in use.
2350 */
2351
2352 switch (hdsp->control_register & HDSP_SyncRefMask) {
2353 case HDSP_SyncRef_ADAT1:
2354 return HDSP_SYNC_FROM_ADAT1;
2355 case HDSP_SyncRef_ADAT2:
2356 return HDSP_SYNC_FROM_ADAT2;
2357 case HDSP_SyncRef_ADAT3:
2358 return HDSP_SYNC_FROM_ADAT3;
2359 case HDSP_SyncRef_SPDIF:
2360 return HDSP_SYNC_FROM_SPDIF;
2361 case HDSP_SyncRef_WORD:
2362 return HDSP_SYNC_FROM_WORD;
2363 case HDSP_SyncRef_ADAT_SYNC:
2364 return HDSP_SYNC_FROM_ADAT_SYNC;
2365 default:
2366 return HDSP_SYNC_FROM_WORD;
2367 }
2368 return 0;
2369 }
2370
2371 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2372 {
2373 hdsp->control_register &= ~HDSP_SyncRefMask;
2374 switch (pref) {
2375 case HDSP_SYNC_FROM_ADAT1:
2376 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2377 break;
2378 case HDSP_SYNC_FROM_ADAT2:
2379 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2380 break;
2381 case HDSP_SYNC_FROM_ADAT3:
2382 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2383 break;
2384 case HDSP_SYNC_FROM_SPDIF:
2385 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2386 break;
2387 case HDSP_SYNC_FROM_WORD:
2388 hdsp->control_register |= HDSP_SyncRef_WORD;
2389 break;
2390 case HDSP_SYNC_FROM_ADAT_SYNC:
2391 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2392 break;
2393 default:
2394 return -1;
2395 }
2396 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2397 return 0;
2398 }
2399
2400 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2401 {
2402 static const char * const texts[] = {
2403 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2404 };
2405 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2406 int num_items;
2407
2408 switch (hdsp->io_type) {
2409 case Digiface:
2410 case H9652:
2411 num_items = 6;
2412 break;
2413 case Multiface:
2414 num_items = 4;
2415 break;
2416 case H9632:
2417 num_items = 3;
2418 break;
2419 default:
2420 return -EINVAL;
2421 }
2422
2423 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2424 }
2425
2426 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2427 {
2428 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2429
2430 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2431 return 0;
2432 }
2433
2434 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2435 {
2436 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2437 int change, max;
2438 unsigned int val;
2439
2440 if (!snd_hdsp_use_is_exclusive(hdsp))
2441 return -EBUSY;
2442
2443 switch (hdsp->io_type) {
2444 case Digiface:
2445 case H9652:
2446 max = 6;
2447 break;
2448 case Multiface:
2449 max = 4;
2450 break;
2451 case H9632:
2452 max = 3;
2453 break;
2454 default:
2455 return -EIO;
2456 }
2457
2458 val = ucontrol->value.enumerated.item[0] % max;
2459 spin_lock_irq(&hdsp->lock);
2460 change = (int)val != hdsp_pref_sync_ref(hdsp);
2461 hdsp_set_pref_sync_ref(hdsp, val);
2462 spin_unlock_irq(&hdsp->lock);
2463 return change;
2464 }
2465
2466 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2467 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2468 .name = xname, \
2469 .index = xindex, \
2470 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2471 .info = snd_hdsp_info_autosync_ref, \
2472 .get = snd_hdsp_get_autosync_ref, \
2473 }
2474
2475 static int hdsp_autosync_ref(struct hdsp *hdsp)
2476 {
2477 /* This looks at the autosync selected sync reference */
2478 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2479
2480 switch (status2 & HDSP_SelSyncRefMask) {
2481 case HDSP_SelSyncRef_WORD:
2482 return HDSP_AUTOSYNC_FROM_WORD;
2483 case HDSP_SelSyncRef_ADAT_SYNC:
2484 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2485 case HDSP_SelSyncRef_SPDIF:
2486 return HDSP_AUTOSYNC_FROM_SPDIF;
2487 case HDSP_SelSyncRefMask:
2488 return HDSP_AUTOSYNC_FROM_NONE;
2489 case HDSP_SelSyncRef_ADAT1:
2490 return HDSP_AUTOSYNC_FROM_ADAT1;
2491 case HDSP_SelSyncRef_ADAT2:
2492 return HDSP_AUTOSYNC_FROM_ADAT2;
2493 case HDSP_SelSyncRef_ADAT3:
2494 return HDSP_AUTOSYNC_FROM_ADAT3;
2495 default:
2496 return HDSP_AUTOSYNC_FROM_WORD;
2497 }
2498 return 0;
2499 }
2500
2501 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2502 {
2503 static const char * const texts[] = {
2504 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2505 };
2506
2507 return snd_ctl_enum_info(uinfo, 1, 7, texts);
2508 }
2509
2510 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2511 {
2512 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2513
2514 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2515 return 0;
2516 }
2517
2518 #define HDSP_PRECISE_POINTER(xname, xindex) \
2519 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2520 .name = xname, \
2521 .index = xindex, \
2522 .info = snd_hdsp_info_precise_pointer, \
2523 .get = snd_hdsp_get_precise_pointer, \
2524 .put = snd_hdsp_put_precise_pointer \
2525 }
2526
2527 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2528 {
2529 if (precise)
2530 hdsp->precise_ptr = 1;
2531 else
2532 hdsp->precise_ptr = 0;
2533 return 0;
2534 }
2535
2536 #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
2537
2538 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2539 {
2540 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2541
2542 spin_lock_irq(&hdsp->lock);
2543 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2544 spin_unlock_irq(&hdsp->lock);
2545 return 0;
2546 }
2547
2548 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2549 {
2550 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2551 int change;
2552 unsigned int val;
2553
2554 if (!snd_hdsp_use_is_exclusive(hdsp))
2555 return -EBUSY;
2556 val = ucontrol->value.integer.value[0] & 1;
2557 spin_lock_irq(&hdsp->lock);
2558 change = (int)val != hdsp->precise_ptr;
2559 hdsp_set_precise_pointer(hdsp, val);
2560 spin_unlock_irq(&hdsp->lock);
2561 return change;
2562 }
2563
2564 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2565 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2566 .name = xname, \
2567 .index = xindex, \
2568 .info = snd_hdsp_info_use_midi_tasklet, \
2569 .get = snd_hdsp_get_use_midi_tasklet, \
2570 .put = snd_hdsp_put_use_midi_tasklet \
2571 }
2572
2573 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2574 {
2575 if (use_tasklet)
2576 hdsp->use_midi_tasklet = 1;
2577 else
2578 hdsp->use_midi_tasklet = 0;
2579 return 0;
2580 }
2581
2582 #define snd_hdsp_info_use_midi_tasklet snd_ctl_boolean_mono_info
2583
2584 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2585 {
2586 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2587
2588 spin_lock_irq(&hdsp->lock);
2589 ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2590 spin_unlock_irq(&hdsp->lock);
2591 return 0;
2592 }
2593
2594 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2595 {
2596 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2597 int change;
2598 unsigned int val;
2599
2600 if (!snd_hdsp_use_is_exclusive(hdsp))
2601 return -EBUSY;
2602 val = ucontrol->value.integer.value[0] & 1;
2603 spin_lock_irq(&hdsp->lock);
2604 change = (int)val != hdsp->use_midi_tasklet;
2605 hdsp_set_use_midi_tasklet(hdsp, val);
2606 spin_unlock_irq(&hdsp->lock);
2607 return change;
2608 }
2609
2610 #define HDSP_MIXER(xname, xindex) \
2611 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2612 .name = xname, \
2613 .index = xindex, \
2614 .device = 0, \
2615 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2616 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2617 .info = snd_hdsp_info_mixer, \
2618 .get = snd_hdsp_get_mixer, \
2619 .put = snd_hdsp_put_mixer \
2620 }
2621
2622 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2623 {
2624 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2625 uinfo->count = 3;
2626 uinfo->value.integer.min = 0;
2627 uinfo->value.integer.max = 65536;
2628 uinfo->value.integer.step = 1;
2629 return 0;
2630 }
2631
2632 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2633 {
2634 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2635 int source;
2636 int destination;
2637 int addr;
2638
2639 source = ucontrol->value.integer.value[0];
2640 destination = ucontrol->value.integer.value[1];
2641
2642 if (source >= hdsp->max_channels)
2643 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2644 else
2645 addr = hdsp_input_to_output_key(hdsp,source, destination);
2646
2647 spin_lock_irq(&hdsp->lock);
2648 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2649 spin_unlock_irq(&hdsp->lock);
2650 return 0;
2651 }
2652
2653 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2654 {
2655 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2656 int change;
2657 int source;
2658 int destination;
2659 int gain;
2660 int addr;
2661
2662 if (!snd_hdsp_use_is_exclusive(hdsp))
2663 return -EBUSY;
2664
2665 source = ucontrol->value.integer.value[0];
2666 destination = ucontrol->value.integer.value[1];
2667
2668 if (source >= hdsp->max_channels)
2669 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2670 else
2671 addr = hdsp_input_to_output_key(hdsp,source, destination);
2672
2673 gain = ucontrol->value.integer.value[2];
2674
2675 spin_lock_irq(&hdsp->lock);
2676 change = gain != hdsp_read_gain(hdsp, addr);
2677 if (change)
2678 hdsp_write_gain(hdsp, addr, gain);
2679 spin_unlock_irq(&hdsp->lock);
2680 return change;
2681 }
2682
2683 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2684 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2685 .name = xname, \
2686 .index = xindex, \
2687 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2688 .info = snd_hdsp_info_sync_check, \
2689 .get = snd_hdsp_get_wc_sync_check \
2690 }
2691
2692 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2693 {
2694 static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2695
2696 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2697 }
2698
2699 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2700 {
2701 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2702 if (status2 & HDSP_wc_lock) {
2703 if (status2 & HDSP_wc_sync)
2704 return 2;
2705 else
2706 return 1;
2707 } else
2708 return 0;
2709 return 0;
2710 }
2711
2712 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2713 {
2714 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2715
2716 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2717 return 0;
2718 }
2719
2720 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2721 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2722 .name = xname, \
2723 .index = xindex, \
2724 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2725 .info = snd_hdsp_info_sync_check, \
2726 .get = snd_hdsp_get_spdif_sync_check \
2727 }
2728
2729 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2730 {
2731 int status = hdsp_read(hdsp, HDSP_statusRegister);
2732 if (status & HDSP_SPDIFErrorFlag)
2733 return 0;
2734 else {
2735 if (status & HDSP_SPDIFSync)
2736 return 2;
2737 else
2738 return 1;
2739 }
2740 return 0;
2741 }
2742
2743 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2744 {
2745 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2746
2747 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2748 return 0;
2749 }
2750
2751 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2752 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2753 .name = xname, \
2754 .index = xindex, \
2755 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2756 .info = snd_hdsp_info_sync_check, \
2757 .get = snd_hdsp_get_adatsync_sync_check \
2758 }
2759
2760 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2761 {
2762 int status = hdsp_read(hdsp, HDSP_statusRegister);
2763 if (status & HDSP_TimecodeLock) {
2764 if (status & HDSP_TimecodeSync)
2765 return 2;
2766 else
2767 return 1;
2768 } else
2769 return 0;
2770 }
2771
2772 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2773 {
2774 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2775
2776 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2777 return 0;
2778 }
2779
2780 #define HDSP_ADAT_SYNC_CHECK \
2781 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2782 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2783 .info = snd_hdsp_info_sync_check, \
2784 .get = snd_hdsp_get_adat_sync_check \
2785 }
2786
2787 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2788 {
2789 int status = hdsp_read(hdsp, HDSP_statusRegister);
2790
2791 if (status & (HDSP_Lock0>>idx)) {
2792 if (status & (HDSP_Sync0>>idx))
2793 return 2;
2794 else
2795 return 1;
2796 } else
2797 return 0;
2798 }
2799
2800 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2801 {
2802 int offset;
2803 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2804
2805 offset = ucontrol->id.index - 1;
2806 if (snd_BUG_ON(offset < 0))
2807 return -EINVAL;
2808
2809 switch (hdsp->io_type) {
2810 case Digiface:
2811 case H9652:
2812 if (offset >= 3)
2813 return -EINVAL;
2814 break;
2815 case Multiface:
2816 case H9632:
2817 if (offset >= 1)
2818 return -EINVAL;
2819 break;
2820 default:
2821 return -EIO;
2822 }
2823
2824 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2825 return 0;
2826 }
2827
2828 #define HDSP_DDS_OFFSET(xname, xindex) \
2829 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2830 .name = xname, \
2831 .index = xindex, \
2832 .info = snd_hdsp_info_dds_offset, \
2833 .get = snd_hdsp_get_dds_offset, \
2834 .put = snd_hdsp_put_dds_offset \
2835 }
2836
2837 static int hdsp_dds_offset(struct hdsp *hdsp)
2838 {
2839 u64 n;
2840 unsigned int dds_value = hdsp->dds_value;
2841 int system_sample_rate = hdsp->system_sample_rate;
2842
2843 if (!dds_value)
2844 return 0;
2845
2846 n = DDS_NUMERATOR;
2847 /*
2848 * dds_value = n / rate
2849 * rate = n / dds_value
2850 */
2851 n = div_u64(n, dds_value);
2852 if (system_sample_rate >= 112000)
2853 n *= 4;
2854 else if (system_sample_rate >= 56000)
2855 n *= 2;
2856 return ((int)n) - system_sample_rate;
2857 }
2858
2859 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2860 {
2861 int rate = hdsp->system_sample_rate + offset_hz;
2862 hdsp_set_dds_value(hdsp, rate);
2863 return 0;
2864 }
2865
2866 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2867 {
2868 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2869 uinfo->count = 1;
2870 uinfo->value.integer.min = -5000;
2871 uinfo->value.integer.max = 5000;
2872 return 0;
2873 }
2874
2875 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2876 {
2877 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2878
2879 ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2880 return 0;
2881 }
2882
2883 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2884 {
2885 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2886 int change;
2887 int val;
2888
2889 if (!snd_hdsp_use_is_exclusive(hdsp))
2890 return -EBUSY;
2891 val = ucontrol->value.integer.value[0];
2892 spin_lock_irq(&hdsp->lock);
2893 if (val != hdsp_dds_offset(hdsp))
2894 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2895 else
2896 change = 0;
2897 spin_unlock_irq(&hdsp->lock);
2898 return change;
2899 }
2900
2901 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2902 HDSP_DA_GAIN("DA Gain", 0),
2903 HDSP_AD_GAIN("AD Gain", 0),
2904 HDSP_PHONE_GAIN("Phones Gain", 0),
2905 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2906 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2907 };
2908
2909 static struct snd_kcontrol_new snd_hdsp_controls[] = {
2910 {
2911 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2912 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2913 .info = snd_hdsp_control_spdif_info,
2914 .get = snd_hdsp_control_spdif_get,
2915 .put = snd_hdsp_control_spdif_put,
2916 },
2917 {
2918 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2919 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2920 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2921 .info = snd_hdsp_control_spdif_stream_info,
2922 .get = snd_hdsp_control_spdif_stream_get,
2923 .put = snd_hdsp_control_spdif_stream_put,
2924 },
2925 {
2926 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2927 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2928 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2929 .info = snd_hdsp_control_spdif_mask_info,
2930 .get = snd_hdsp_control_spdif_mask_get,
2931 .private_value = IEC958_AES0_NONAUDIO |
2932 IEC958_AES0_PROFESSIONAL |
2933 IEC958_AES0_CON_EMPHASIS,
2934 },
2935 {
2936 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2937 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2938 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2939 .info = snd_hdsp_control_spdif_mask_info,
2940 .get = snd_hdsp_control_spdif_mask_get,
2941 .private_value = IEC958_AES0_NONAUDIO |
2942 IEC958_AES0_PROFESSIONAL |
2943 IEC958_AES0_PRO_EMPHASIS,
2944 },
2945 HDSP_MIXER("Mixer", 0),
2946 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2947 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2948 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2949 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2950 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2951 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2952 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2953 {
2954 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2955 .name = "Sample Clock Source Locking",
2956 .info = snd_hdsp_info_clock_source_lock,
2957 .get = snd_hdsp_get_clock_source_lock,
2958 .put = snd_hdsp_put_clock_source_lock,
2959 },
2960 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2961 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2962 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2963 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2964 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2965 /* 'External Rate' complies with the alsa control naming scheme */
2966 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2967 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2968 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2969 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2970 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2971 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2972 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
2973 };
2974
2975
2976 static int hdsp_rpm_input12(struct hdsp *hdsp)
2977 {
2978 switch (hdsp->control_register & HDSP_RPM_Inp12) {
2979 case HDSP_RPM_Inp12_Phon_6dB:
2980 return 0;
2981 case HDSP_RPM_Inp12_Phon_n6dB:
2982 return 2;
2983 case HDSP_RPM_Inp12_Line_0dB:
2984 return 3;
2985 case HDSP_RPM_Inp12_Line_n6dB:
2986 return 4;
2987 }
2988 return 1;
2989 }
2990
2991
2992 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2993 {
2994 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2995
2996 ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2997 return 0;
2998 }
2999
3000
3001 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
3002 {
3003 hdsp->control_register &= ~HDSP_RPM_Inp12;
3004 switch (mode) {
3005 case 0:
3006 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
3007 break;
3008 case 1:
3009 break;
3010 case 2:
3011 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
3012 break;
3013 case 3:
3014 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
3015 break;
3016 case 4:
3017 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
3018 break;
3019 default:
3020 return -1;
3021 }
3022
3023 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3024 return 0;
3025 }
3026
3027
3028 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3029 {
3030 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3031 int change;
3032 int val;
3033
3034 if (!snd_hdsp_use_is_exclusive(hdsp))
3035 return -EBUSY;
3036 val = ucontrol->value.enumerated.item[0];
3037 if (val < 0)
3038 val = 0;
3039 if (val > 4)
3040 val = 4;
3041 spin_lock_irq(&hdsp->lock);
3042 if (val != hdsp_rpm_input12(hdsp))
3043 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3044 else
3045 change = 0;
3046 spin_unlock_irq(&hdsp->lock);
3047 return change;
3048 }
3049
3050
3051 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3052 {
3053 static const char * const texts[] = {
3054 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3055 };
3056
3057 return snd_ctl_enum_info(uinfo, 1, 5, texts);
3058 }
3059
3060
3061 static int hdsp_rpm_input34(struct hdsp *hdsp)
3062 {
3063 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3064 case HDSP_RPM_Inp34_Phon_6dB:
3065 return 0;
3066 case HDSP_RPM_Inp34_Phon_n6dB:
3067 return 2;
3068 case HDSP_RPM_Inp34_Line_0dB:
3069 return 3;
3070 case HDSP_RPM_Inp34_Line_n6dB:
3071 return 4;
3072 }
3073 return 1;
3074 }
3075
3076
3077 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3078 {
3079 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3080
3081 ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3082 return 0;
3083 }
3084
3085
3086 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3087 {
3088 hdsp->control_register &= ~HDSP_RPM_Inp34;
3089 switch (mode) {
3090 case 0:
3091 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3092 break;
3093 case 1:
3094 break;
3095 case 2:
3096 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3097 break;
3098 case 3:
3099 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3100 break;
3101 case 4:
3102 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3103 break;
3104 default:
3105 return -1;
3106 }
3107
3108 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3109 return 0;
3110 }
3111
3112
3113 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3114 {
3115 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3116 int change;
3117 int val;
3118
3119 if (!snd_hdsp_use_is_exclusive(hdsp))
3120 return -EBUSY;
3121 val = ucontrol->value.enumerated.item[0];
3122 if (val < 0)
3123 val = 0;
3124 if (val > 4)
3125 val = 4;
3126 spin_lock_irq(&hdsp->lock);
3127 if (val != hdsp_rpm_input34(hdsp))
3128 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3129 else
3130 change = 0;
3131 spin_unlock_irq(&hdsp->lock);
3132 return change;
3133 }
3134
3135
3136 /* RPM Bypass switch */
3137 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3138 {
3139 return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3140 }
3141
3142
3143 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3144 {
3145 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3146
3147 ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3148 return 0;
3149 }
3150
3151
3152 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3153 {
3154 if (on)
3155 hdsp->control_register |= HDSP_RPM_Bypass;
3156 else
3157 hdsp->control_register &= ~HDSP_RPM_Bypass;
3158 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3159 return 0;
3160 }
3161
3162
3163 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3164 {
3165 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3166 int change;
3167 unsigned int val;
3168
3169 if (!snd_hdsp_use_is_exclusive(hdsp))
3170 return -EBUSY;
3171 val = ucontrol->value.integer.value[0] & 1;
3172 spin_lock_irq(&hdsp->lock);
3173 change = (int)val != hdsp_rpm_bypass(hdsp);
3174 hdsp_set_rpm_bypass(hdsp, val);
3175 spin_unlock_irq(&hdsp->lock);
3176 return change;
3177 }
3178
3179
3180 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3181 {
3182 static const char * const texts[] = {"On", "Off"};
3183
3184 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3185 }
3186
3187
3188 /* RPM Disconnect switch */
3189 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3190 {
3191 return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3192 }
3193
3194
3195 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3196 {
3197 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3198
3199 ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3200 return 0;
3201 }
3202
3203
3204 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3205 {
3206 if (on)
3207 hdsp->control_register |= HDSP_RPM_Disconnect;
3208 else
3209 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3210 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3211 return 0;
3212 }
3213
3214
3215 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3216 {
3217 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3218 int change;
3219 unsigned int val;
3220
3221 if (!snd_hdsp_use_is_exclusive(hdsp))
3222 return -EBUSY;
3223 val = ucontrol->value.integer.value[0] & 1;
3224 spin_lock_irq(&hdsp->lock);
3225 change = (int)val != hdsp_rpm_disconnect(hdsp);
3226 hdsp_set_rpm_disconnect(hdsp, val);
3227 spin_unlock_irq(&hdsp->lock);
3228 return change;
3229 }
3230
3231 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3232 {
3233 static const char * const texts[] = {"On", "Off"};
3234
3235 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3236 }
3237
3238 static struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3239 {
3240 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3241 .name = "RPM Bypass",
3242 .get = snd_hdsp_get_rpm_bypass,
3243 .put = snd_hdsp_put_rpm_bypass,
3244 .info = snd_hdsp_info_rpm_bypass
3245 },
3246 {
3247 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3248 .name = "RPM Disconnect",
3249 .get = snd_hdsp_get_rpm_disconnect,
3250 .put = snd_hdsp_put_rpm_disconnect,
3251 .info = snd_hdsp_info_rpm_disconnect
3252 },
3253 {
3254 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3255 .name = "Input 1/2",
3256 .get = snd_hdsp_get_rpm_input12,
3257 .put = snd_hdsp_put_rpm_input12,
3258 .info = snd_hdsp_info_rpm_input
3259 },
3260 {
3261 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3262 .name = "Input 3/4",
3263 .get = snd_hdsp_get_rpm_input34,
3264 .put = snd_hdsp_put_rpm_input34,
3265 .info = snd_hdsp_info_rpm_input
3266 },
3267 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3268 HDSP_MIXER("Mixer", 0)
3269 };
3270
3271 static struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3272 HDSP_TOGGLE_SETTING("Analog Extension Board",
3273 HDSP_AnalogExtensionBoard);
3274 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3275
3276 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3277 {
3278 unsigned int idx;
3279 int err;
3280 struct snd_kcontrol *kctl;
3281
3282 if (hdsp->io_type == RPM) {
3283 /* RPM Bypass, Disconnect and Input switches */
3284 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3285 err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3286 if (err < 0)
3287 return err;
3288 }
3289 return 0;
3290 }
3291
3292 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3293 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3294 return err;
3295 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3296 hdsp->spdif_ctl = kctl;
3297 }
3298
3299 /* ADAT SyncCheck status */
3300 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3301 snd_hdsp_adat_sync_check.index = 1;
3302 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3303 return err;
3304 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3305 for (idx = 1; idx < 3; ++idx) {
3306 snd_hdsp_adat_sync_check.index = idx+1;
3307 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3308 return err;
3309 }
3310 }
3311
3312 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3313 if (hdsp->io_type == H9632) {
3314 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3315 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3316 return err;
3317 }
3318 }
3319
3320 /* AEB control for H96xx card */
3321 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3322 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3323 return err;
3324 }
3325
3326 return 0;
3327 }
3328
3329 /*------------------------------------------------------------
3330 /proc interface
3331 ------------------------------------------------------------*/
3332
3333 static void
3334 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3335 {
3336 struct hdsp *hdsp = entry->private_data;
3337 unsigned int status;
3338 unsigned int status2;
3339 char *pref_sync_ref;
3340 char *autosync_ref;
3341 char *system_clock_mode;
3342 char *clock_source;
3343 int x;
3344
3345 status = hdsp_read(hdsp, HDSP_statusRegister);
3346 status2 = hdsp_read(hdsp, HDSP_status2Register);
3347
3348 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3349 hdsp->card->number + 1);
3350 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3351 hdsp->capture_buffer, hdsp->playback_buffer);
3352 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3353 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3354 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3355 snd_iprintf(buffer, "Control2 register: 0x%x\n",
3356 hdsp->control2_register);
3357 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3358 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3359
3360 if (hdsp_check_for_iobox(hdsp)) {
3361 snd_iprintf(buffer, "No I/O box connected.\n"
3362 "Please connect one and upload firmware.\n");
3363 return;
3364 }
3365
3366 if (hdsp_check_for_firmware(hdsp, 0)) {
3367 if (hdsp->state & HDSP_FirmwareCached) {
3368 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3369 snd_iprintf(buffer, "Firmware loading from "
3370 "cache failed, "
3371 "please upload manually.\n");
3372 return;
3373 }
3374 } else {
3375 int err = -EINVAL;
3376 err = hdsp_request_fw_loader(hdsp);
3377 if (err < 0) {
3378 snd_iprintf(buffer,
3379 "No firmware loaded nor cached, "
3380 "please upload firmware.\n");
3381 return;
3382 }
3383 }
3384 }
3385
3386 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3387 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3388 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3389 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3390 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3391 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3392
3393 snd_iprintf(buffer, "\n");
3394
3395 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3396
3397 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3398 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3399 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3400 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3401
3402 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3403
3404 snd_iprintf(buffer, "\n");
3405
3406 switch (hdsp_clock_source(hdsp)) {
3407 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3408 clock_source = "AutoSync";
3409 break;
3410 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3411 clock_source = "Internal 32 kHz";
3412 break;
3413 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3414 clock_source = "Internal 44.1 kHz";
3415 break;
3416 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3417 clock_source = "Internal 48 kHz";
3418 break;
3419 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3420 clock_source = "Internal 64 kHz";
3421 break;
3422 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3423 clock_source = "Internal 88.2 kHz";
3424 break;
3425 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3426 clock_source = "Internal 96 kHz";
3427 break;
3428 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3429 clock_source = "Internal 128 kHz";
3430 break;
3431 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3432 clock_source = "Internal 176.4 kHz";
3433 break;
3434 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3435 clock_source = "Internal 192 kHz";
3436 break;
3437 default:
3438 clock_source = "Error";
3439 }
3440 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3441
3442 if (hdsp_system_clock_mode(hdsp))
3443 system_clock_mode = "Slave";
3444 else
3445 system_clock_mode = "Master";
3446
3447 switch (hdsp_pref_sync_ref (hdsp)) {
3448 case HDSP_SYNC_FROM_WORD:
3449 pref_sync_ref = "Word Clock";
3450 break;
3451 case HDSP_SYNC_FROM_ADAT_SYNC:
3452 pref_sync_ref = "ADAT Sync";
3453 break;
3454 case HDSP_SYNC_FROM_SPDIF:
3455 pref_sync_ref = "SPDIF";
3456 break;
3457 case HDSP_SYNC_FROM_ADAT1:
3458 pref_sync_ref = "ADAT1";
3459 break;
3460 case HDSP_SYNC_FROM_ADAT2:
3461 pref_sync_ref = "ADAT2";
3462 break;
3463 case HDSP_SYNC_FROM_ADAT3:
3464 pref_sync_ref = "ADAT3";
3465 break;
3466 default:
3467 pref_sync_ref = "Word Clock";
3468 break;
3469 }
3470 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3471
3472 switch (hdsp_autosync_ref (hdsp)) {
3473 case HDSP_AUTOSYNC_FROM_WORD:
3474 autosync_ref = "Word Clock";
3475 break;
3476 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3477 autosync_ref = "ADAT Sync";
3478 break;
3479 case HDSP_AUTOSYNC_FROM_SPDIF:
3480 autosync_ref = "SPDIF";
3481 break;
3482 case HDSP_AUTOSYNC_FROM_NONE:
3483 autosync_ref = "None";
3484 break;
3485 case HDSP_AUTOSYNC_FROM_ADAT1:
3486 autosync_ref = "ADAT1";
3487 break;
3488 case HDSP_AUTOSYNC_FROM_ADAT2:
3489 autosync_ref = "ADAT2";
3490 break;
3491 case HDSP_AUTOSYNC_FROM_ADAT3:
3492 autosync_ref = "ADAT3";
3493 break;
3494 default:
3495 autosync_ref = "---";
3496 break;
3497 }
3498 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3499
3500 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3501
3502 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3503
3504 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3505 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3506
3507 snd_iprintf(buffer, "\n");
3508
3509 if (hdsp->io_type != RPM) {
3510 switch (hdsp_spdif_in(hdsp)) {
3511 case HDSP_SPDIFIN_OPTICAL:
3512 snd_iprintf(buffer, "IEC958 input: Optical\n");
3513 break;
3514 case HDSP_SPDIFIN_COAXIAL:
3515 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3516 break;
3517 case HDSP_SPDIFIN_INTERNAL:
3518 snd_iprintf(buffer, "IEC958 input: Internal\n");
3519 break;
3520 case HDSP_SPDIFIN_AES:
3521 snd_iprintf(buffer, "IEC958 input: AES\n");
3522 break;
3523 default:
3524 snd_iprintf(buffer, "IEC958 input: ???\n");
3525 break;
3526 }
3527 }
3528
3529 if (RPM == hdsp->io_type) {
3530 if (hdsp->control_register & HDSP_RPM_Bypass)
3531 snd_iprintf(buffer, "RPM Bypass: disabled\n");
3532 else
3533 snd_iprintf(buffer, "RPM Bypass: enabled\n");
3534 if (hdsp->control_register & HDSP_RPM_Disconnect)
3535 snd_iprintf(buffer, "RPM disconnected\n");
3536 else
3537 snd_iprintf(buffer, "RPM connected\n");
3538
3539 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3540 case HDSP_RPM_Inp12_Phon_6dB:
3541 snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3542 break;
3543 case HDSP_RPM_Inp12_Phon_0dB:
3544 snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3545 break;
3546 case HDSP_RPM_Inp12_Phon_n6dB:
3547 snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3548 break;
3549 case HDSP_RPM_Inp12_Line_0dB:
3550 snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3551 break;
3552 case HDSP_RPM_Inp12_Line_n6dB:
3553 snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3554 break;
3555 default:
3556 snd_iprintf(buffer, "Input 1/2: ???\n");
3557 }
3558
3559 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3560 case HDSP_RPM_Inp34_Phon_6dB:
3561 snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3562 break;
3563 case HDSP_RPM_Inp34_Phon_0dB:
3564 snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3565 break;
3566 case HDSP_RPM_Inp34_Phon_n6dB:
3567 snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3568 break;
3569 case HDSP_RPM_Inp34_Line_0dB:
3570 snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3571 break;
3572 case HDSP_RPM_Inp34_Line_n6dB:
3573 snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3574 break;
3575 default:
3576 snd_iprintf(buffer, "Input 3/4: ???\n");
3577 }
3578
3579 } else {
3580 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3581 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3582 else
3583 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3584
3585 if (hdsp->control_register & HDSP_SPDIFProfessional)
3586 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3587 else
3588 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3589
3590 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3591 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3592 else
3593 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3594
3595 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3596 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3597 else
3598 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3599 x = hdsp_spdif_sample_rate(hdsp);
3600 if (x != 0)
3601 snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3602 else
3603 snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3604 }
3605 snd_iprintf(buffer, "\n");
3606
3607 /* Sync Check */
3608 x = status & HDSP_Sync0;
3609 if (status & HDSP_Lock0)
3610 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3611 else
3612 snd_iprintf(buffer, "ADAT1: No Lock\n");
3613
3614 switch (hdsp->io_type) {
3615 case Digiface:
3616 case H9652:
3617 x = status & HDSP_Sync1;
3618 if (status & HDSP_Lock1)
3619 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3620 else
3621 snd_iprintf(buffer, "ADAT2: No Lock\n");
3622 x = status & HDSP_Sync2;
3623 if (status & HDSP_Lock2)
3624 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3625 else
3626 snd_iprintf(buffer, "ADAT3: No Lock\n");
3627 break;
3628 default:
3629 /* relax */
3630 break;
3631 }
3632
3633 x = status & HDSP_SPDIFSync;
3634 if (status & HDSP_SPDIFErrorFlag)
3635 snd_iprintf (buffer, "SPDIF: No Lock\n");
3636 else
3637 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3638
3639 x = status2 & HDSP_wc_sync;
3640 if (status2 & HDSP_wc_lock)
3641 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3642 else
3643 snd_iprintf (buffer, "Word Clock: No Lock\n");
3644
3645 x = status & HDSP_TimecodeSync;
3646 if (status & HDSP_TimecodeLock)
3647 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3648 else
3649 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3650
3651 snd_iprintf(buffer, "\n");
3652
3653 /* Informations about H9632 specific controls */
3654 if (hdsp->io_type == H9632) {
3655 char *tmp;
3656
3657 switch (hdsp_ad_gain(hdsp)) {
3658 case 0:
3659 tmp = "-10 dBV";
3660 break;
3661 case 1:
3662 tmp = "+4 dBu";
3663 break;
3664 default:
3665 tmp = "Lo Gain";
3666 break;
3667 }
3668 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3669
3670 switch (hdsp_da_gain(hdsp)) {
3671 case 0:
3672 tmp = "Hi Gain";
3673 break;
3674 case 1:
3675 tmp = "+4 dBu";
3676 break;
3677 default:
3678 tmp = "-10 dBV";
3679 break;
3680 }
3681 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3682
3683 switch (hdsp_phone_gain(hdsp)) {
3684 case 0:
3685 tmp = "0 dB";
3686 break;
3687 case 1:
3688 tmp = "-6 dB";
3689 break;
3690 default:
3691 tmp = "-12 dB";
3692 break;
3693 }
3694 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3695
3696 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3697 hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3698 "yes" : "no");
3699
3700 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3701 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3702 else
3703 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3704 snd_iprintf(buffer, "\n");
3705 }
3706
3707 }
3708
3709 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3710 {
3711 snd_card_ro_proc_new(hdsp->card, "hdsp", hdsp, snd_hdsp_proc_read);
3712 }
3713
3714 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3715 {
3716 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3717 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3718 }
3719
3720 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3721 {
3722 unsigned long pb_bus, cb_bus;
3723
3724 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3725 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3726 if (hdsp->capture_dma_buf.area)
3727 snd_dma_free_pages(&hdsp->capture_dma_buf);
3728 dev_err(hdsp->card->dev,
3729 "%s: no buffers available\n", hdsp->card_name);
3730 return -ENOMEM;
3731 }
3732
3733 /* Align to bus-space 64K boundary */
3734
3735 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3736 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3737
3738 /* Tell the card where it is */
3739
3740 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3741 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3742
3743 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3744 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3745
3746 return 0;
3747 }
3748
3749 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3750 {
3751 unsigned int i;
3752
3753 /* ASSUMPTION: hdsp->lock is either held, or
3754 there is no need to hold it (e.g. during module
3755 initialization).
3756 */
3757
3758 /* set defaults:
3759
3760 SPDIF Input via Coax
3761 Master clock mode
3762 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3763 which implies 2 4096 sample, 32Kbyte periods).
3764 Enable line out.
3765 */
3766
3767 hdsp->control_register = HDSP_ClockModeMaster |
3768 HDSP_SPDIFInputCoaxial |
3769 hdsp_encode_latency(7) |
3770 HDSP_LineOut;
3771
3772
3773 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3774
3775 #ifdef SNDRV_BIG_ENDIAN
3776 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3777 #else
3778 hdsp->control2_register = 0;
3779 #endif
3780 if (hdsp->io_type == H9652)
3781 snd_hdsp_9652_enable_mixer (hdsp);
3782 else
3783 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3784
3785 hdsp_reset_hw_pointer(hdsp);
3786 hdsp_compute_period_size(hdsp);
3787
3788 /* silence everything */
3789
3790 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3791 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3792
3793 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3794 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3795 return -EIO;
3796 }
3797
3798 /* H9632 specific defaults */
3799 if (hdsp->io_type == H9632) {
3800 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3801 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3802 }
3803
3804 /* set a default rate so that the channel map is set up.
3805 */
3806
3807 hdsp_set_rate(hdsp, 48000, 1);
3808
3809 return 0;
3810 }
3811
3812 static void hdsp_midi_tasklet(unsigned long arg)
3813 {
3814 struct hdsp *hdsp = (struct hdsp *)arg;
3815
3816 if (hdsp->midi[0].pending)
3817 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3818 if (hdsp->midi[1].pending)
3819 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3820 }
3821
3822 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3823 {
3824 struct hdsp *hdsp = (struct hdsp *) dev_id;
3825 unsigned int status;
3826 int audio;
3827 int midi0;
3828 int midi1;
3829 unsigned int midi0status;
3830 unsigned int midi1status;
3831 int schedule = 0;
3832
3833 status = hdsp_read(hdsp, HDSP_statusRegister);
3834
3835 audio = status & HDSP_audioIRQPending;
3836 midi0 = status & HDSP_midi0IRQPending;
3837 midi1 = status & HDSP_midi1IRQPending;
3838
3839 if (!audio && !midi0 && !midi1)
3840 return IRQ_NONE;
3841
3842 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3843
3844 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3845 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3846
3847 if (!(hdsp->state & HDSP_InitializationComplete))
3848 return IRQ_HANDLED;
3849
3850 if (audio) {
3851 if (hdsp->capture_substream)
3852 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3853
3854 if (hdsp->playback_substream)
3855 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3856 }
3857
3858 if (midi0 && midi0status) {
3859 if (hdsp->use_midi_tasklet) {
3860 /* we disable interrupts for this input until processing is done */
3861 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3862 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3863 hdsp->midi[0].pending = 1;
3864 schedule = 1;
3865 } else {
3866 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3867 }
3868 }
3869 if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3870 if (hdsp->use_midi_tasklet) {
3871 /* we disable interrupts for this input until processing is done */
3872 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3873 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3874 hdsp->midi[1].pending = 1;
3875 schedule = 1;
3876 } else {
3877 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3878 }
3879 }
3880 if (hdsp->use_midi_tasklet && schedule)
3881 tasklet_schedule(&hdsp->midi_tasklet);
3882 return IRQ_HANDLED;
3883 }
3884
3885 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3886 {
3887 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3888 return hdsp_hw_pointer(hdsp);
3889 }
3890
3891 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3892 int stream,
3893 int channel)
3894
3895 {
3896 int mapped_channel;
3897
3898 if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3899 return NULL;
3900
3901 if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3902 return NULL;
3903
3904 if (stream == SNDRV_PCM_STREAM_CAPTURE)
3905 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3906 else
3907 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3908 }
3909
3910 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream,
3911 int channel, unsigned long pos,
3912 void __user *src, unsigned long count)
3913 {
3914 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3915 char *channel_buf;
3916
3917 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3918 return -EINVAL;
3919
3920 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3921 if (snd_BUG_ON(!channel_buf))
3922 return -EIO;
3923 if (copy_from_user(channel_buf + pos, src, count))
3924 return -EFAULT;
3925 return 0;
3926 }
3927
3928 static int snd_hdsp_playback_copy_kernel(struct snd_pcm_substream *substream,
3929 int channel, unsigned long pos,
3930 void *src, unsigned long count)
3931 {
3932 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3933 char *channel_buf;
3934
3935 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3936 if (snd_BUG_ON(!channel_buf))
3937 return -EIO;
3938 memcpy(channel_buf + pos, src, count);
3939 return 0;
3940 }
3941
3942 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream,
3943 int channel, unsigned long pos,
3944 void __user *dst, unsigned long count)
3945 {
3946 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3947 char *channel_buf;
3948
3949 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3950 return -EINVAL;
3951
3952 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3953 if (snd_BUG_ON(!channel_buf))
3954 return -EIO;
3955 if (copy_to_user(dst, channel_buf + pos, count))
3956 return -EFAULT;
3957 return 0;
3958 }
3959
3960 static int snd_hdsp_capture_copy_kernel(struct snd_pcm_substream *substream,
3961 int channel, unsigned long pos,
3962 void *dst, unsigned long count)
3963 {
3964 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3965 char *channel_buf;
3966
3967 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3968 if (snd_BUG_ON(!channel_buf))
3969 return -EIO;
3970 memcpy(dst, channel_buf + pos, count);
3971 return 0;
3972 }
3973
3974 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream,
3975 int channel, unsigned long pos,
3976 unsigned long count)
3977 {
3978 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3979 char *channel_buf;
3980
3981 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3982 if (snd_BUG_ON(!channel_buf))
3983 return -EIO;
3984 memset(channel_buf + pos, 0, count);
3985 return 0;
3986 }
3987
3988 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3989 {
3990 struct snd_pcm_runtime *runtime = substream->runtime;
3991 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3992 struct snd_pcm_substream *other;
3993 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3994 other = hdsp->capture_substream;
3995 else
3996 other = hdsp->playback_substream;
3997 if (hdsp->running)
3998 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3999 else
4000 runtime->status->hw_ptr = 0;
4001 if (other) {
4002 struct snd_pcm_substream *s;
4003 struct snd_pcm_runtime *oruntime = other->runtime;
4004 snd_pcm_group_for_each_entry(s, substream) {
4005 if (s == other) {
4006 oruntime->status->hw_ptr = runtime->status->hw_ptr;
4007 break;
4008 }
4009 }
4010 }
4011 return 0;
4012 }
4013
4014 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
4015 struct snd_pcm_hw_params *params)
4016 {
4017 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4018 int err;
4019 pid_t this_pid;
4020 pid_t other_pid;
4021
4022 if (hdsp_check_for_iobox (hdsp))
4023 return -EIO;
4024
4025 if (hdsp_check_for_firmware(hdsp, 1))
4026 return -EIO;
4027
4028 spin_lock_irq(&hdsp->lock);
4029
4030 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4031 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4032 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4033 this_pid = hdsp->playback_pid;
4034 other_pid = hdsp->capture_pid;
4035 } else {
4036 this_pid = hdsp->capture_pid;
4037 other_pid = hdsp->playback_pid;
4038 }
4039
4040 if ((other_pid > 0) && (this_pid != other_pid)) {
4041
4042 /* The other stream is open, and not by the same
4043 task as this one. Make sure that the parameters
4044 that matter are the same.
4045 */
4046
4047 if (params_rate(params) != hdsp->system_sample_rate) {
4048 spin_unlock_irq(&hdsp->lock);
4049 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4050 return -EBUSY;
4051 }
4052
4053 if (params_period_size(params) != hdsp->period_bytes / 4) {
4054 spin_unlock_irq(&hdsp->lock);
4055 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4056 return -EBUSY;
4057 }
4058
4059 /* We're fine. */
4060
4061 spin_unlock_irq(&hdsp->lock);
4062 return 0;
4063
4064 } else {
4065 spin_unlock_irq(&hdsp->lock);
4066 }
4067
4068 /* how to make sure that the rate matches an externally-set one ?
4069 */
4070
4071 spin_lock_irq(&hdsp->lock);
4072 if (! hdsp->clock_source_locked) {
4073 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4074 spin_unlock_irq(&hdsp->lock);
4075 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4076 return err;
4077 }
4078 }
4079 spin_unlock_irq(&hdsp->lock);
4080
4081 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4082 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4083 return err;
4084 }
4085
4086 return 0;
4087 }
4088
4089 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4090 struct snd_pcm_channel_info *info)
4091 {
4092 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4093 unsigned int channel = info->channel;
4094
4095 if (snd_BUG_ON(channel >= hdsp->max_channels))
4096 return -EINVAL;
4097 channel = array_index_nospec(channel, hdsp->max_channels);
4098
4099 if (hdsp->channel_map[channel] < 0)
4100 return -EINVAL;
4101
4102 info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;
4103 info->first = 0;
4104 info->step = 32;
4105 return 0;
4106 }
4107
4108 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4109 unsigned int cmd, void *arg)
4110 {
4111 switch (cmd) {
4112 case SNDRV_PCM_IOCTL1_RESET:
4113 return snd_hdsp_reset(substream);
4114 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4115 return snd_hdsp_channel_info(substream, arg);
4116 default:
4117 break;
4118 }
4119
4120 return snd_pcm_lib_ioctl(substream, cmd, arg);
4121 }
4122
4123 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4124 {
4125 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4126 struct snd_pcm_substream *other;
4127 int running;
4128
4129 if (hdsp_check_for_iobox (hdsp))
4130 return -EIO;
4131
4132 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4133 return -EIO;
4134
4135 spin_lock(&hdsp->lock);
4136 running = hdsp->running;
4137 switch (cmd) {
4138 case SNDRV_PCM_TRIGGER_START:
4139 running |= 1 << substream->stream;
4140 break;
4141 case SNDRV_PCM_TRIGGER_STOP:
4142 running &= ~(1 << substream->stream);
4143 break;
4144 default:
4145 snd_BUG();
4146 spin_unlock(&hdsp->lock);
4147 return -EINVAL;
4148 }
4149 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4150 other = hdsp->capture_substream;
4151 else
4152 other = hdsp->playback_substream;
4153
4154 if (other) {
4155 struct snd_pcm_substream *s;
4156 snd_pcm_group_for_each_entry(s, substream) {
4157 if (s == other) {
4158 snd_pcm_trigger_done(s, substream);
4159 if (cmd == SNDRV_PCM_TRIGGER_START)
4160 running |= 1 << s->stream;
4161 else
4162 running &= ~(1 << s->stream);
4163 goto _ok;
4164 }
4165 }
4166 if (cmd == SNDRV_PCM_TRIGGER_START) {
4167 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4168 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4169 hdsp_silence_playback(hdsp);
4170 } else {
4171 if (running &&
4172 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4173 hdsp_silence_playback(hdsp);
4174 }
4175 } else {
4176 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4177 hdsp_silence_playback(hdsp);
4178 }
4179 _ok:
4180 snd_pcm_trigger_done(substream, substream);
4181 if (!hdsp->running && running)
4182 hdsp_start_audio(hdsp);
4183 else if (hdsp->running && !running)
4184 hdsp_stop_audio(hdsp);
4185 hdsp->running = running;
4186 spin_unlock(&hdsp->lock);
4187
4188 return 0;
4189 }
4190
4191 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4192 {
4193 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4194 int result = 0;
4195
4196 if (hdsp_check_for_iobox (hdsp))
4197 return -EIO;
4198
4199 if (hdsp_check_for_firmware(hdsp, 1))
4200 return -EIO;
4201
4202 spin_lock_irq(&hdsp->lock);
4203 if (!hdsp->running)
4204 hdsp_reset_hw_pointer(hdsp);
4205 spin_unlock_irq(&hdsp->lock);
4206 return result;
4207 }
4208
4209 static const struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4210 {
4211 .info = (SNDRV_PCM_INFO_MMAP |
4212 SNDRV_PCM_INFO_MMAP_VALID |
4213 SNDRV_PCM_INFO_NONINTERLEAVED |
4214 SNDRV_PCM_INFO_SYNC_START |
4215 SNDRV_PCM_INFO_DOUBLE),
4216 #ifdef SNDRV_BIG_ENDIAN
4217 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4218 #else
4219 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4220 #endif
4221 .rates = (SNDRV_PCM_RATE_32000 |
4222 SNDRV_PCM_RATE_44100 |
4223 SNDRV_PCM_RATE_48000 |
4224 SNDRV_PCM_RATE_64000 |
4225 SNDRV_PCM_RATE_88200 |
4226 SNDRV_PCM_RATE_96000),
4227 .rate_min = 32000,
4228 .rate_max = 96000,
4229 .channels_min = 6,
4230 .channels_max = HDSP_MAX_CHANNELS,
4231 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4232 .period_bytes_min = (64 * 4) * 10,
4233 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4234 .periods_min = 2,
4235 .periods_max = 2,
4236 .fifo_size = 0
4237 };
4238
4239 static const struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4240 {
4241 .info = (SNDRV_PCM_INFO_MMAP |
4242 SNDRV_PCM_INFO_MMAP_VALID |
4243 SNDRV_PCM_INFO_NONINTERLEAVED |
4244 SNDRV_PCM_INFO_SYNC_START),
4245 #ifdef SNDRV_BIG_ENDIAN
4246 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4247 #else
4248 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4249 #endif
4250 .rates = (SNDRV_PCM_RATE_32000 |
4251 SNDRV_PCM_RATE_44100 |
4252 SNDRV_PCM_RATE_48000 |
4253 SNDRV_PCM_RATE_64000 |
4254 SNDRV_PCM_RATE_88200 |
4255 SNDRV_PCM_RATE_96000),
4256 .rate_min = 32000,
4257 .rate_max = 96000,
4258 .channels_min = 5,
4259 .channels_max = HDSP_MAX_CHANNELS,
4260 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4261 .period_bytes_min = (64 * 4) * 10,
4262 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4263 .periods_min = 2,
4264 .periods_max = 2,
4265 .fifo_size = 0
4266 };
4267
4268 static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4269
4270 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4271 .count = ARRAY_SIZE(hdsp_period_sizes),
4272 .list = hdsp_period_sizes,
4273 .mask = 0
4274 };
4275
4276 static const unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4277
4278 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4279 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4280 .list = hdsp_9632_sample_rates,
4281 .mask = 0
4282 };
4283
4284 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4285 struct snd_pcm_hw_rule *rule)
4286 {
4287 struct hdsp *hdsp = rule->private;
4288 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4289 if (hdsp->io_type == H9632) {
4290 unsigned int list[3];
4291 list[0] = hdsp->qs_in_channels;
4292 list[1] = hdsp->ds_in_channels;
4293 list[2] = hdsp->ss_in_channels;
4294 return snd_interval_list(c, 3, list, 0);
4295 } else {
4296 unsigned int list[2];
4297 list[0] = hdsp->ds_in_channels;
4298 list[1] = hdsp->ss_in_channels;
4299 return snd_interval_list(c, 2, list, 0);
4300 }
4301 }
4302
4303 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4304 struct snd_pcm_hw_rule *rule)
4305 {
4306 unsigned int list[3];
4307 struct hdsp *hdsp = rule->private;
4308 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4309 if (hdsp->io_type == H9632) {
4310 list[0] = hdsp->qs_out_channels;
4311 list[1] = hdsp->ds_out_channels;
4312 list[2] = hdsp->ss_out_channels;
4313 return snd_interval_list(c, 3, list, 0);
4314 } else {
4315 list[0] = hdsp->ds_out_channels;
4316 list[1] = hdsp->ss_out_channels;
4317 }
4318 return snd_interval_list(c, 2, list, 0);
4319 }
4320
4321 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4322 struct snd_pcm_hw_rule *rule)
4323 {
4324 struct hdsp *hdsp = rule->private;
4325 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4326 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4327 if (r->min > 96000 && hdsp->io_type == H9632) {
4328 struct snd_interval t = {
4329 .min = hdsp->qs_in_channels,
4330 .max = hdsp->qs_in_channels,
4331 .integer = 1,
4332 };
4333 return snd_interval_refine(c, &t);
4334 } else if (r->min > 48000 && r->max <= 96000) {
4335 struct snd_interval t = {
4336 .min = hdsp->ds_in_channels,
4337 .max = hdsp->ds_in_channels,
4338 .integer = 1,
4339 };
4340 return snd_interval_refine(c, &t);
4341 } else if (r->max < 64000) {
4342 struct snd_interval t = {
4343 .min = hdsp->ss_in_channels,
4344 .max = hdsp->ss_in_channels,
4345 .integer = 1,
4346 };
4347 return snd_interval_refine(c, &t);
4348 }
4349 return 0;
4350 }
4351
4352 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4353 struct snd_pcm_hw_rule *rule)
4354 {
4355 struct hdsp *hdsp = rule->private;
4356 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4357 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4358 if (r->min > 96000 && hdsp->io_type == H9632) {
4359 struct snd_interval t = {
4360 .min = hdsp->qs_out_channels,
4361 .max = hdsp->qs_out_channels,
4362 .integer = 1,
4363 };
4364 return snd_interval_refine(c, &t);
4365 } else if (r->min > 48000 && r->max <= 96000) {
4366 struct snd_interval t = {
4367 .min = hdsp->ds_out_channels,
4368 .max = hdsp->ds_out_channels,
4369 .integer = 1,
4370 };
4371 return snd_interval_refine(c, &t);
4372 } else if (r->max < 64000) {
4373 struct snd_interval t = {
4374 .min = hdsp->ss_out_channels,
4375 .max = hdsp->ss_out_channels,
4376 .integer = 1,
4377 };
4378 return snd_interval_refine(c, &t);
4379 }
4380 return 0;
4381 }
4382
4383 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4384 struct snd_pcm_hw_rule *rule)
4385 {
4386 struct hdsp *hdsp = rule->private;
4387 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4388 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4389 if (c->min >= hdsp->ss_out_channels) {
4390 struct snd_interval t = {
4391 .min = 32000,
4392 .max = 48000,
4393 .integer = 1,
4394 };
4395 return snd_interval_refine(r, &t);
4396 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4397 struct snd_interval t = {
4398 .min = 128000,
4399 .max = 192000,
4400 .integer = 1,
4401 };
4402 return snd_interval_refine(r, &t);
4403 } else if (c->max <= hdsp->ds_out_channels) {
4404 struct snd_interval t = {
4405 .min = 64000,
4406 .max = 96000,
4407 .integer = 1,
4408 };
4409 return snd_interval_refine(r, &t);
4410 }
4411 return 0;
4412 }
4413
4414 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4415 struct snd_pcm_hw_rule *rule)
4416 {
4417 struct hdsp *hdsp = rule->private;
4418 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4419 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4420 if (c->min >= hdsp->ss_in_channels) {
4421 struct snd_interval t = {
4422 .min = 32000,
4423 .max = 48000,
4424 .integer = 1,
4425 };
4426 return snd_interval_refine(r, &t);
4427 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4428 struct snd_interval t = {
4429 .min = 128000,
4430 .max = 192000,
4431 .integer = 1,
4432 };
4433 return snd_interval_refine(r, &t);
4434 } else if (c->max <= hdsp->ds_in_channels) {
4435 struct snd_interval t = {
4436 .min = 64000,
4437 .max = 96000,
4438 .integer = 1,
4439 };
4440 return snd_interval_refine(r, &t);
4441 }
4442 return 0;
4443 }
4444
4445 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4446 {
4447 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4448 struct snd_pcm_runtime *runtime = substream->runtime;
4449
4450 if (hdsp_check_for_iobox (hdsp))
4451 return -EIO;
4452
4453 if (hdsp_check_for_firmware(hdsp, 1))
4454 return -EIO;
4455
4456 spin_lock_irq(&hdsp->lock);
4457
4458 snd_pcm_set_sync(substream);
4459
4460 runtime->hw = snd_hdsp_playback_subinfo;
4461 runtime->dma_area = hdsp->playback_buffer;
4462 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4463
4464 hdsp->playback_pid = current->pid;
4465 hdsp->playback_substream = substream;
4466
4467 spin_unlock_irq(&hdsp->lock);
4468
4469 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4470 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4471 if (hdsp->clock_source_locked) {
4472 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4473 } else if (hdsp->io_type == H9632) {
4474 runtime->hw.rate_max = 192000;
4475 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4476 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4477 }
4478 if (hdsp->io_type == H9632) {
4479 runtime->hw.channels_min = hdsp->qs_out_channels;
4480 runtime->hw.channels_max = hdsp->ss_out_channels;
4481 }
4482
4483 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4484 snd_hdsp_hw_rule_out_channels, hdsp,
4485 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4486 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4487 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4488 SNDRV_PCM_HW_PARAM_RATE, -1);
4489 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4490 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4491 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4492
4493 if (RPM != hdsp->io_type) {
4494 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4495 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4496 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4497 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4498 }
4499 return 0;
4500 }
4501
4502 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4503 {
4504 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4505
4506 spin_lock_irq(&hdsp->lock);
4507
4508 hdsp->playback_pid = -1;
4509 hdsp->playback_substream = NULL;
4510
4511 spin_unlock_irq(&hdsp->lock);
4512
4513 if (RPM != hdsp->io_type) {
4514 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4515 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4516 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4517 }
4518 return 0;
4519 }
4520
4521
4522 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4523 {
4524 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4525 struct snd_pcm_runtime *runtime = substream->runtime;
4526
4527 if (hdsp_check_for_iobox (hdsp))
4528 return -EIO;
4529
4530 if (hdsp_check_for_firmware(hdsp, 1))
4531 return -EIO;
4532
4533 spin_lock_irq(&hdsp->lock);
4534
4535 snd_pcm_set_sync(substream);
4536
4537 runtime->hw = snd_hdsp_capture_subinfo;
4538 runtime->dma_area = hdsp->capture_buffer;
4539 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4540
4541 hdsp->capture_pid = current->pid;
4542 hdsp->capture_substream = substream;
4543
4544 spin_unlock_irq(&hdsp->lock);
4545
4546 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4547 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4548 if (hdsp->io_type == H9632) {
4549 runtime->hw.channels_min = hdsp->qs_in_channels;
4550 runtime->hw.channels_max = hdsp->ss_in_channels;
4551 runtime->hw.rate_max = 192000;
4552 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4553 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4554 }
4555 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4556 snd_hdsp_hw_rule_in_channels, hdsp,
4557 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4558 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4559 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4560 SNDRV_PCM_HW_PARAM_RATE, -1);
4561 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4562 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4563 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4564 return 0;
4565 }
4566
4567 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4568 {
4569 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4570
4571 spin_lock_irq(&hdsp->lock);
4572
4573 hdsp->capture_pid = -1;
4574 hdsp->capture_substream = NULL;
4575
4576 spin_unlock_irq(&hdsp->lock);
4577 return 0;
4578 }
4579
4580 /* helper functions for copying meter values */
4581 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4582 {
4583 u32 val = readl(src);
4584 return copy_to_user(dest, &val, 4);
4585 }
4586
4587 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4588 {
4589 u32 rms_low, rms_high;
4590 u64 rms;
4591 rms_low = readl(src_low);
4592 rms_high = readl(src_high);
4593 rms = ((u64)rms_high << 32) | rms_low;
4594 return copy_to_user(dest, &rms, 8);
4595 }
4596
4597 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4598 {
4599 u32 rms_low, rms_high;
4600 u64 rms;
4601 rms_low = readl(src_low) & 0xffffff00;
4602 rms_high = readl(src_high) & 0xffffff00;
4603 rms = ((u64)rms_high << 32) | rms_low;
4604 return copy_to_user(dest, &rms, 8);
4605 }
4606
4607 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4608 {
4609 int doublespeed = 0;
4610 int i, j, channels, ofs;
4611
4612 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4613 doublespeed = 1;
4614 channels = doublespeed ? 14 : 26;
4615 for (i = 0, j = 0; i < 26; ++i) {
4616 if (doublespeed && (i & 4))
4617 continue;
4618 ofs = HDSP_9652_peakBase - j * 4;
4619 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4620 return -EFAULT;
4621 ofs -= channels * 4;
4622 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4623 return -EFAULT;
4624 ofs -= channels * 4;
4625 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4626 return -EFAULT;
4627 ofs = HDSP_9652_rmsBase + j * 8;
4628 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4629 hdsp->iobase + ofs + 4))
4630 return -EFAULT;
4631 ofs += channels * 8;
4632 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4633 hdsp->iobase + ofs + 4))
4634 return -EFAULT;
4635 ofs += channels * 8;
4636 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4637 hdsp->iobase + ofs + 4))
4638 return -EFAULT;
4639 j++;
4640 }
4641 return 0;
4642 }
4643
4644 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4645 {
4646 int i, j;
4647 struct hdsp_9632_meters __iomem *m;
4648 int doublespeed = 0;
4649
4650 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4651 doublespeed = 1;
4652 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4653 for (i = 0, j = 0; i < 16; ++i, ++j) {
4654 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4655 return -EFAULT;
4656 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4657 return -EFAULT;
4658 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4659 return -EFAULT;
4660 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4661 &m->input_rms_high[j]))
4662 return -EFAULT;
4663 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4664 &m->playback_rms_high[j]))
4665 return -EFAULT;
4666 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4667 &m->output_rms_high[j]))
4668 return -EFAULT;
4669 if (doublespeed && i == 3) i += 4;
4670 }
4671 return 0;
4672 }
4673
4674 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4675 {
4676 int i;
4677
4678 for (i = 0; i < 26; i++) {
4679 if (copy_u32_le(&peak_rms->playback_peaks[i],
4680 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4681 return -EFAULT;
4682 if (copy_u32_le(&peak_rms->input_peaks[i],
4683 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4684 return -EFAULT;
4685 }
4686 for (i = 0; i < 28; i++) {
4687 if (copy_u32_le(&peak_rms->output_peaks[i],
4688 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4689 return -EFAULT;
4690 }
4691 for (i = 0; i < 26; ++i) {
4692 if (copy_u64_le(&peak_rms->playback_rms[i],
4693 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4694 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4695 return -EFAULT;
4696 if (copy_u64_le(&peak_rms->input_rms[i],
4697 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4698 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4699 return -EFAULT;
4700 }
4701 return 0;
4702 }
4703
4704 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4705 {
4706 struct hdsp *hdsp = hw->private_data;
4707 void __user *argp = (void __user *)arg;
4708 int err;
4709
4710 switch (cmd) {
4711 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4712 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4713
4714 err = hdsp_check_for_iobox(hdsp);
4715 if (err < 0)
4716 return err;
4717
4718 err = hdsp_check_for_firmware(hdsp, 1);
4719 if (err < 0)
4720 return err;
4721
4722 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4723 dev_err(hdsp->card->dev,
4724 "firmware needs to be uploaded to the card.\n");
4725 return -EINVAL;
4726 }
4727
4728 switch (hdsp->io_type) {
4729 case H9652:
4730 return hdsp_9652_get_peak(hdsp, peak_rms);
4731 case H9632:
4732 return hdsp_9632_get_peak(hdsp, peak_rms);
4733 default:
4734 return hdsp_get_peak(hdsp, peak_rms);
4735 }
4736 }
4737 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4738 struct hdsp_config_info info;
4739 unsigned long flags;
4740 int i;
4741
4742 err = hdsp_check_for_iobox(hdsp);
4743 if (err < 0)
4744 return err;
4745
4746 err = hdsp_check_for_firmware(hdsp, 1);
4747 if (err < 0)
4748 return err;
4749
4750 memset(&info, 0, sizeof(info));
4751 spin_lock_irqsave(&hdsp->lock, flags);
4752 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4753 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4754 if (hdsp->io_type != H9632)
4755 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4756 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4757 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4758 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4759 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4760 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4761 HDSP_SPDIFOpticalOut);
4762 info.spdif_professional = (unsigned char)
4763 hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4764 info.spdif_emphasis = (unsigned char)
4765 hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4766 info.spdif_nonaudio = (unsigned char)
4767 hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4768 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4769 info.system_sample_rate = hdsp->system_sample_rate;
4770 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4771 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4772 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4773 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4774 info.line_out = (unsigned char)
4775 hdsp_toggle_setting(hdsp, HDSP_LineOut);
4776 if (hdsp->io_type == H9632) {
4777 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4778 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4779 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4780 info.xlr_breakout_cable =
4781 (unsigned char)hdsp_toggle_setting(hdsp,
4782 HDSP_XLRBreakoutCable);
4783
4784 } else if (hdsp->io_type == RPM) {
4785 info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4786 info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4787 }
4788 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4789 info.analog_extension_board =
4790 (unsigned char)hdsp_toggle_setting(hdsp,
4791 HDSP_AnalogExtensionBoard);
4792 spin_unlock_irqrestore(&hdsp->lock, flags);
4793 if (copy_to_user(argp, &info, sizeof(info)))
4794 return -EFAULT;
4795 break;
4796 }
4797 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4798 struct hdsp_9632_aeb h9632_aeb;
4799
4800 if (hdsp->io_type != H9632) return -EINVAL;
4801 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4802 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4803 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4804 return -EFAULT;
4805 break;
4806 }
4807 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4808 struct hdsp_version hdsp_version;
4809 int err;
4810
4811 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4812 if (hdsp->io_type == Undefined) {
4813 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4814 return err;
4815 }
4816 memset(&hdsp_version, 0, sizeof(hdsp_version));
4817 hdsp_version.io_type = hdsp->io_type;
4818 hdsp_version.firmware_rev = hdsp->firmware_rev;
4819 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4820 return -EFAULT;
4821 break;
4822 }
4823 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4824 struct hdsp_firmware __user *firmware;
4825 u32 __user *firmware_data;
4826 int err;
4827
4828 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4829 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4830 if (hdsp->io_type == Undefined) return -EINVAL;
4831
4832 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4833 return -EBUSY;
4834
4835 dev_info(hdsp->card->dev,
4836 "initializing firmware upload\n");
4837 firmware = (struct hdsp_firmware __user *)argp;
4838
4839 if (get_user(firmware_data, &firmware->firmware_data))
4840 return -EFAULT;
4841
4842 if (hdsp_check_for_iobox (hdsp))
4843 return -EIO;
4844
4845 if (!hdsp->fw_uploaded) {
4846 hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4847 if (!hdsp->fw_uploaded)
4848 return -ENOMEM;
4849 }
4850
4851 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4852 HDSP_FIRMWARE_SIZE)) {
4853 vfree(hdsp->fw_uploaded);
4854 hdsp->fw_uploaded = NULL;
4855 return -EFAULT;
4856 }
4857
4858 hdsp->state |= HDSP_FirmwareCached;
4859
4860 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4861 return err;
4862
4863 if (!(hdsp->state & HDSP_InitializationComplete)) {
4864 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4865 return err;
4866
4867 snd_hdsp_initialize_channels(hdsp);
4868 snd_hdsp_initialize_midi_flush(hdsp);
4869
4870 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4871 dev_err(hdsp->card->dev,
4872 "error creating alsa devices\n");
4873 return err;
4874 }
4875 }
4876 break;
4877 }
4878 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4879 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4880 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4881 return -EFAULT;
4882 break;
4883 }
4884 default:
4885 return -EINVAL;
4886 }
4887 return 0;
4888 }
4889
4890 static const struct snd_pcm_ops snd_hdsp_playback_ops = {
4891 .open = snd_hdsp_playback_open,
4892 .close = snd_hdsp_playback_release,
4893 .ioctl = snd_hdsp_ioctl,
4894 .hw_params = snd_hdsp_hw_params,
4895 .prepare = snd_hdsp_prepare,
4896 .trigger = snd_hdsp_trigger,
4897 .pointer = snd_hdsp_hw_pointer,
4898 .copy_user = snd_hdsp_playback_copy,
4899 .copy_kernel = snd_hdsp_playback_copy_kernel,
4900 .fill_silence = snd_hdsp_hw_silence,
4901 };
4902
4903 static const struct snd_pcm_ops snd_hdsp_capture_ops = {
4904 .open = snd_hdsp_capture_open,
4905 .close = snd_hdsp_capture_release,
4906 .ioctl = snd_hdsp_ioctl,
4907 .hw_params = snd_hdsp_hw_params,
4908 .prepare = snd_hdsp_prepare,
4909 .trigger = snd_hdsp_trigger,
4910 .pointer = snd_hdsp_hw_pointer,
4911 .copy_user = snd_hdsp_capture_copy,
4912 .copy_kernel = snd_hdsp_capture_copy_kernel,
4913 };
4914
4915 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4916 {
4917 struct snd_hwdep *hw;
4918 int err;
4919
4920 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4921 return err;
4922
4923 hdsp->hwdep = hw;
4924 hw->private_data = hdsp;
4925 strcpy(hw->name, "HDSP hwdep interface");
4926
4927 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4928 hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4929
4930 return 0;
4931 }
4932
4933 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4934 {
4935 struct snd_pcm *pcm;
4936 int err;
4937
4938 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4939 return err;
4940
4941 hdsp->pcm = pcm;
4942 pcm->private_data = hdsp;
4943 strcpy(pcm->name, hdsp->card_name);
4944
4945 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4946 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4947
4948 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4949
4950 return 0;
4951 }
4952
4953 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4954 {
4955 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4956 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4957 }
4958
4959 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4960 {
4961 int i;
4962
4963 if (hdsp_fifo_wait (hdsp, 0, 100)) {
4964 dev_err(hdsp->card->dev,
4965 "enable_io fifo_wait failed\n");
4966 return -EIO;
4967 }
4968
4969 for (i = 0; i < hdsp->max_channels; ++i) {
4970 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4971 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4972 }
4973
4974 return 0;
4975 }
4976
4977 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4978 {
4979 int status, aebi_channels, aebo_channels;
4980
4981 switch (hdsp->io_type) {
4982 case Digiface:
4983 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4984 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4985 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4986 break;
4987
4988 case H9652:
4989 hdsp->card_name = "RME Hammerfall HDSP 9652";
4990 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4991 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4992 break;
4993
4994 case H9632:
4995 status = hdsp_read(hdsp, HDSP_statusRegister);
4996 /* HDSP_AEBx bits are low when AEB are connected */
4997 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4998 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4999 hdsp->card_name = "RME Hammerfall HDSP 9632";
5000 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
5001 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
5002 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
5003 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
5004 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
5005 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
5006 break;
5007
5008 case Multiface:
5009 hdsp->card_name = "RME Hammerfall DSP + Multiface";
5010 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
5011 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
5012 break;
5013
5014 case RPM:
5015 hdsp->card_name = "RME Hammerfall DSP + RPM";
5016 hdsp->ss_in_channels = RPM_CHANNELS-1;
5017 hdsp->ss_out_channels = RPM_CHANNELS;
5018 hdsp->ds_in_channels = RPM_CHANNELS-1;
5019 hdsp->ds_out_channels = RPM_CHANNELS;
5020 break;
5021
5022 default:
5023 /* should never get here */
5024 break;
5025 }
5026 }
5027
5028 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5029 {
5030 snd_hdsp_flush_midi_input (hdsp, 0);
5031 snd_hdsp_flush_midi_input (hdsp, 1);
5032 }
5033
5034 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5035 {
5036 int err;
5037
5038 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5039 dev_err(card->dev,
5040 "Error creating pcm interface\n");
5041 return err;
5042 }
5043
5044
5045 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5046 dev_err(card->dev,
5047 "Error creating first midi interface\n");
5048 return err;
5049 }
5050
5051 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5052 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5053 dev_err(card->dev,
5054 "Error creating second midi interface\n");
5055 return err;
5056 }
5057 }
5058
5059 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5060 dev_err(card->dev,
5061 "Error creating ctl interface\n");
5062 return err;
5063 }
5064
5065 snd_hdsp_proc_init(hdsp);
5066
5067 hdsp->system_sample_rate = -1;
5068 hdsp->playback_pid = -1;
5069 hdsp->capture_pid = -1;
5070 hdsp->capture_substream = NULL;
5071 hdsp->playback_substream = NULL;
5072
5073 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5074 dev_err(card->dev,
5075 "Error setting default values\n");
5076 return err;
5077 }
5078
5079 if (!(hdsp->state & HDSP_InitializationComplete)) {
5080 strcpy(card->shortname, "Hammerfall DSP");
5081 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5082 hdsp->port, hdsp->irq);
5083
5084 if ((err = snd_card_register(card)) < 0) {
5085 dev_err(card->dev,
5086 "error registering card\n");
5087 return err;
5088 }
5089 hdsp->state |= HDSP_InitializationComplete;
5090 }
5091
5092 return 0;
5093 }
5094
5095 /* load firmware via hotplug fw loader */
5096 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5097 {
5098 const char *fwfile;
5099 const struct firmware *fw;
5100 int err;
5101
5102 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5103 return 0;
5104 if (hdsp->io_type == Undefined) {
5105 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5106 return err;
5107 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5108 return 0;
5109 }
5110
5111 /* caution: max length of firmware filename is 30! */
5112 switch (hdsp->io_type) {
5113 case RPM:
5114 fwfile = "rpm_firmware.bin";
5115 break;
5116 case Multiface:
5117 if (hdsp->firmware_rev == 0xa)
5118 fwfile = "multiface_firmware.bin";
5119 else
5120 fwfile = "multiface_firmware_rev11.bin";
5121 break;
5122 case Digiface:
5123 if (hdsp->firmware_rev == 0xa)
5124 fwfile = "digiface_firmware.bin";
5125 else
5126 fwfile = "digiface_firmware_rev11.bin";
5127 break;
5128 default:
5129 dev_err(hdsp->card->dev,
5130 "invalid io_type %d\n", hdsp->io_type);
5131 return -EINVAL;
5132 }
5133
5134 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5135 dev_err(hdsp->card->dev,
5136 "cannot load firmware %s\n", fwfile);
5137 return -ENOENT;
5138 }
5139 if (fw->size < HDSP_FIRMWARE_SIZE) {
5140 dev_err(hdsp->card->dev,
5141 "too short firmware size %d (expected %d)\n",
5142 (int)fw->size, HDSP_FIRMWARE_SIZE);
5143 release_firmware(fw);
5144 return -EINVAL;
5145 }
5146
5147 hdsp->firmware = fw;
5148
5149 hdsp->state |= HDSP_FirmwareCached;
5150
5151 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5152 return err;
5153
5154 if (!(hdsp->state & HDSP_InitializationComplete)) {
5155 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5156 return err;
5157
5158 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5159 dev_err(hdsp->card->dev,
5160 "error creating hwdep device\n");
5161 return err;
5162 }
5163 snd_hdsp_initialize_channels(hdsp);
5164 snd_hdsp_initialize_midi_flush(hdsp);
5165 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5166 dev_err(hdsp->card->dev,
5167 "error creating alsa devices\n");
5168 return err;
5169 }
5170 }
5171 return 0;
5172 }
5173
5174 static int snd_hdsp_create(struct snd_card *card,
5175 struct hdsp *hdsp)
5176 {
5177 struct pci_dev *pci = hdsp->pci;
5178 int err;
5179 int is_9652 = 0;
5180 int is_9632 = 0;
5181
5182 hdsp->irq = -1;
5183 hdsp->state = 0;
5184 hdsp->midi[0].rmidi = NULL;
5185 hdsp->midi[1].rmidi = NULL;
5186 hdsp->midi[0].input = NULL;
5187 hdsp->midi[1].input = NULL;
5188 hdsp->midi[0].output = NULL;
5189 hdsp->midi[1].output = NULL;
5190 hdsp->midi[0].pending = 0;
5191 hdsp->midi[1].pending = 0;
5192 spin_lock_init(&hdsp->midi[0].lock);
5193 spin_lock_init(&hdsp->midi[1].lock);
5194 hdsp->iobase = NULL;
5195 hdsp->control_register = 0;
5196 hdsp->control2_register = 0;
5197 hdsp->io_type = Undefined;
5198 hdsp->max_channels = 26;
5199
5200 hdsp->card = card;
5201
5202 spin_lock_init(&hdsp->lock);
5203
5204 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5205
5206 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5207 hdsp->firmware_rev &= 0xff;
5208
5209 /* From Martin Bjoernsen :
5210 "It is important that the card's latency timer register in
5211 the PCI configuration space is set to a value much larger
5212 than 0 by the computer's BIOS or the driver.
5213 The windows driver always sets this 8 bit register [...]
5214 to its maximum 255 to avoid problems with some computers."
5215 */
5216 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5217
5218 strcpy(card->driver, "H-DSP");
5219 strcpy(card->mixername, "Xilinx FPGA");
5220
5221 if (hdsp->firmware_rev < 0xa)
5222 return -ENODEV;
5223 else if (hdsp->firmware_rev < 0x64)
5224 hdsp->card_name = "RME Hammerfall DSP";
5225 else if (hdsp->firmware_rev < 0x96) {
5226 hdsp->card_name = "RME HDSP 9652";
5227 is_9652 = 1;
5228 } else {
5229 hdsp->card_name = "RME HDSP 9632";
5230 hdsp->max_channels = 16;
5231 is_9632 = 1;
5232 }
5233
5234 if ((err = pci_enable_device(pci)) < 0)
5235 return err;
5236
5237 pci_set_master(hdsp->pci);
5238
5239 if ((err = pci_request_regions(pci, "hdsp")) < 0)
5240 return err;
5241 hdsp->port = pci_resource_start(pci, 0);
5242 if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5243 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5244 hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5245 return -EBUSY;
5246 }
5247
5248 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5249 KBUILD_MODNAME, hdsp)) {
5250 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5251 return -EBUSY;
5252 }
5253
5254 hdsp->irq = pci->irq;
5255 hdsp->precise_ptr = 0;
5256 hdsp->use_midi_tasklet = 1;
5257 hdsp->dds_value = 0;
5258
5259 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5260 return err;
5261
5262 if (!is_9652 && !is_9632) {
5263 /* we wait a maximum of 10 seconds to let freshly
5264 * inserted cardbus cards do their hardware init */
5265 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5266
5267 if (err < 0)
5268 return err;
5269
5270 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5271 if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5272 /* we don't fail as this can happen
5273 if userspace is not ready for
5274 firmware upload
5275 */
5276 dev_err(hdsp->card->dev,
5277 "couldn't get firmware from userspace. try using hdsploader\n");
5278 else
5279 /* init is complete, we return */
5280 return 0;
5281 /* we defer initialization */
5282 dev_info(hdsp->card->dev,
5283 "card initialization pending : waiting for firmware\n");
5284 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5285 return err;
5286 return 0;
5287 } else {
5288 dev_info(hdsp->card->dev,
5289 "Firmware already present, initializing card.\n");
5290 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5291 hdsp->io_type = RPM;
5292 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5293 hdsp->io_type = Multiface;
5294 else
5295 hdsp->io_type = Digiface;
5296 }
5297 }
5298
5299 if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5300 return err;
5301
5302 if (is_9652)
5303 hdsp->io_type = H9652;
5304
5305 if (is_9632)
5306 hdsp->io_type = H9632;
5307
5308 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5309 return err;
5310
5311 snd_hdsp_initialize_channels(hdsp);
5312 snd_hdsp_initialize_midi_flush(hdsp);
5313
5314 hdsp->state |= HDSP_FirmwareLoaded;
5315
5316 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5317 return err;
5318
5319 return 0;
5320 }
5321
5322 static int snd_hdsp_free(struct hdsp *hdsp)
5323 {
5324 if (hdsp->port) {
5325 /* stop the audio, and cancel all interrupts */
5326 tasklet_kill(&hdsp->midi_tasklet);
5327 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5328 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5329 }
5330
5331 if (hdsp->irq >= 0)
5332 free_irq(hdsp->irq, (void *)hdsp);
5333
5334 snd_hdsp_free_buffers(hdsp);
5335
5336 release_firmware(hdsp->firmware);
5337 vfree(hdsp->fw_uploaded);
5338 iounmap(hdsp->iobase);
5339
5340 if (hdsp->port)
5341 pci_release_regions(hdsp->pci);
5342
5343 pci_disable_device(hdsp->pci);
5344 return 0;
5345 }
5346
5347 static void snd_hdsp_card_free(struct snd_card *card)
5348 {
5349 struct hdsp *hdsp = card->private_data;
5350
5351 if (hdsp)
5352 snd_hdsp_free(hdsp);
5353 }
5354
5355 static int snd_hdsp_probe(struct pci_dev *pci,
5356 const struct pci_device_id *pci_id)
5357 {
5358 static int dev;
5359 struct hdsp *hdsp;
5360 struct snd_card *card;
5361 int err;
5362
5363 if (dev >= SNDRV_CARDS)
5364 return -ENODEV;
5365 if (!enable[dev]) {
5366 dev++;
5367 return -ENOENT;
5368 }
5369
5370 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5371 sizeof(struct hdsp), &card);
5372 if (err < 0)
5373 return err;
5374
5375 hdsp = card->private_data;
5376 card->private_free = snd_hdsp_card_free;
5377 hdsp->dev = dev;
5378 hdsp->pci = pci;
5379 err = snd_hdsp_create(card, hdsp);
5380 if (err)
5381 goto free_card;
5382
5383 strcpy(card->shortname, "Hammerfall DSP");
5384 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5385 hdsp->port, hdsp->irq);
5386 err = snd_card_register(card);
5387 if (err) {
5388 free_card:
5389 snd_card_free(card);
5390 return err;
5391 }
5392 pci_set_drvdata(pci, card);
5393 dev++;
5394 return 0;
5395 }
5396
5397 static void snd_hdsp_remove(struct pci_dev *pci)
5398 {
5399 snd_card_free(pci_get_drvdata(pci));
5400 }
5401
5402 static struct pci_driver hdsp_driver = {
5403 .name = KBUILD_MODNAME,
5404 .id_table = snd_hdsp_ids,
5405 .probe = snd_hdsp_probe,
5406 .remove = snd_hdsp_remove,
5407 };
5408
5409 module_pci_driver(hdsp_driver);