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Merge branches 'misc', 'sa1100-for-next' and 'spectre' into for-linus
[thirdparty/linux.git] / sound / soc / codecs / nau8810.c
1 /*
2 * nau8810.c -- NAU8810 ALSA Soc Audio driver
3 *
4 * Copyright 2016 Nuvoton Technology Corp.
5 *
6 * Author: David Lin <ctlin0@nuvoton.com>
7 *
8 * Based on WM8974.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/pm.h>
21 #include <linux/i2c.h>
22 #include <linux/regmap.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30
31 #include "nau8810.h"
32
33 #define NAU_PLL_FREQ_MAX 100000000
34 #define NAU_PLL_FREQ_MIN 90000000
35 #define NAU_PLL_REF_MAX 33000000
36 #define NAU_PLL_REF_MIN 8000000
37 #define NAU_PLL_OPTOP_MIN 6
38
39
40 static const int nau8810_mclk_scaler[] = { 10, 15, 20, 30, 40, 60, 80, 120 };
41
42 static const struct reg_default nau8810_reg_defaults[] = {
43 { NAU8810_REG_POWER1, 0x0000 },
44 { NAU8810_REG_POWER2, 0x0000 },
45 { NAU8810_REG_POWER3, 0x0000 },
46 { NAU8810_REG_IFACE, 0x0050 },
47 { NAU8810_REG_COMP, 0x0000 },
48 { NAU8810_REG_CLOCK, 0x0140 },
49 { NAU8810_REG_SMPLR, 0x0000 },
50 { NAU8810_REG_DAC, 0x0000 },
51 { NAU8810_REG_DACGAIN, 0x00FF },
52 { NAU8810_REG_ADC, 0x0100 },
53 { NAU8810_REG_ADCGAIN, 0x00FF },
54 { NAU8810_REG_EQ1, 0x012C },
55 { NAU8810_REG_EQ2, 0x002C },
56 { NAU8810_REG_EQ3, 0x002C },
57 { NAU8810_REG_EQ4, 0x002C },
58 { NAU8810_REG_EQ5, 0x002C },
59 { NAU8810_REG_DACLIM1, 0x0032 },
60 { NAU8810_REG_DACLIM2, 0x0000 },
61 { NAU8810_REG_NOTCH1, 0x0000 },
62 { NAU8810_REG_NOTCH2, 0x0000 },
63 { NAU8810_REG_NOTCH3, 0x0000 },
64 { NAU8810_REG_NOTCH4, 0x0000 },
65 { NAU8810_REG_ALC1, 0x0038 },
66 { NAU8810_REG_ALC2, 0x000B },
67 { NAU8810_REG_ALC3, 0x0032 },
68 { NAU8810_REG_NOISEGATE, 0x0000 },
69 { NAU8810_REG_PLLN, 0x0008 },
70 { NAU8810_REG_PLLK1, 0x000C },
71 { NAU8810_REG_PLLK2, 0x0093 },
72 { NAU8810_REG_PLLK3, 0x00E9 },
73 { NAU8810_REG_ATTEN, 0x0000 },
74 { NAU8810_REG_INPUT_SIGNAL, 0x0003 },
75 { NAU8810_REG_PGAGAIN, 0x0010 },
76 { NAU8810_REG_ADCBOOST, 0x0100 },
77 { NAU8810_REG_OUTPUT, 0x0002 },
78 { NAU8810_REG_SPKMIX, 0x0001 },
79 { NAU8810_REG_SPKGAIN, 0x0039 },
80 { NAU8810_REG_MONOMIX, 0x0001 },
81 { NAU8810_REG_POWER4, 0x0000 },
82 { NAU8810_REG_TSLOTCTL1, 0x0000 },
83 { NAU8810_REG_TSLOTCTL2, 0x0020 },
84 { NAU8810_REG_DEVICE_REVID, 0x0000 },
85 { NAU8810_REG_I2C_DEVICEID, 0x001A },
86 { NAU8810_REG_ADDITIONID, 0x00CA },
87 { NAU8810_REG_RESERVE, 0x0124 },
88 { NAU8810_REG_OUTCTL, 0x0001 },
89 { NAU8810_REG_ALC1ENHAN1, 0x0010 },
90 { NAU8810_REG_ALC1ENHAN2, 0x0000 },
91 { NAU8810_REG_MISCCTL, 0x0000 },
92 { NAU8810_REG_OUTTIEOFF, 0x0000 },
93 { NAU8810_REG_AGCP2POUT, 0x0000 },
94 { NAU8810_REG_AGCPOUT, 0x0000 },
95 { NAU8810_REG_AMTCTL, 0x0000 },
96 { NAU8810_REG_OUTTIEOFFMAN, 0x0000 },
97 };
98
99 static bool nau8810_readable_reg(struct device *dev, unsigned int reg)
100 {
101 switch (reg) {
102 case NAU8810_REG_RESET ... NAU8810_REG_SMPLR:
103 case NAU8810_REG_DAC ... NAU8810_REG_DACGAIN:
104 case NAU8810_REG_ADC ... NAU8810_REG_ADCGAIN:
105 case NAU8810_REG_EQ1 ... NAU8810_REG_EQ5:
106 case NAU8810_REG_DACLIM1 ... NAU8810_REG_DACLIM2:
107 case NAU8810_REG_NOTCH1 ... NAU8810_REG_NOTCH4:
108 case NAU8810_REG_ALC1 ... NAU8810_REG_ATTEN:
109 case NAU8810_REG_INPUT_SIGNAL ... NAU8810_REG_PGAGAIN:
110 case NAU8810_REG_ADCBOOST:
111 case NAU8810_REG_OUTPUT ... NAU8810_REG_SPKMIX:
112 case NAU8810_REG_SPKGAIN:
113 case NAU8810_REG_MONOMIX:
114 case NAU8810_REG_POWER4 ... NAU8810_REG_TSLOTCTL2:
115 case NAU8810_REG_DEVICE_REVID ... NAU8810_REG_RESERVE:
116 case NAU8810_REG_OUTCTL ... NAU8810_REG_ALC1ENHAN2:
117 case NAU8810_REG_MISCCTL:
118 case NAU8810_REG_OUTTIEOFF ... NAU8810_REG_OUTTIEOFFMAN:
119 return true;
120 default:
121 return false;
122 }
123 }
124
125 static bool nau8810_writeable_reg(struct device *dev, unsigned int reg)
126 {
127 switch (reg) {
128 case NAU8810_REG_RESET ... NAU8810_REG_SMPLR:
129 case NAU8810_REG_DAC ... NAU8810_REG_DACGAIN:
130 case NAU8810_REG_ADC ... NAU8810_REG_ADCGAIN:
131 case NAU8810_REG_EQ1 ... NAU8810_REG_EQ5:
132 case NAU8810_REG_DACLIM1 ... NAU8810_REG_DACLIM2:
133 case NAU8810_REG_NOTCH1 ... NAU8810_REG_NOTCH4:
134 case NAU8810_REG_ALC1 ... NAU8810_REG_ATTEN:
135 case NAU8810_REG_INPUT_SIGNAL ... NAU8810_REG_PGAGAIN:
136 case NAU8810_REG_ADCBOOST:
137 case NAU8810_REG_OUTPUT ... NAU8810_REG_SPKMIX:
138 case NAU8810_REG_SPKGAIN:
139 case NAU8810_REG_MONOMIX:
140 case NAU8810_REG_POWER4 ... NAU8810_REG_TSLOTCTL2:
141 case NAU8810_REG_OUTCTL ... NAU8810_REG_ALC1ENHAN2:
142 case NAU8810_REG_MISCCTL:
143 case NAU8810_REG_OUTTIEOFF ... NAU8810_REG_OUTTIEOFFMAN:
144 return true;
145 default:
146 return false;
147 }
148 }
149
150 static bool nau8810_volatile_reg(struct device *dev, unsigned int reg)
151 {
152 switch (reg) {
153 case NAU8810_REG_RESET:
154 case NAU8810_REG_DEVICE_REVID ... NAU8810_REG_RESERVE:
155 return true;
156 default:
157 return false;
158 }
159 }
160
161 /* The EQ parameters get function is to get the 5 band equalizer control.
162 * The regmap raw read can't work here because regmap doesn't provide
163 * value format for value width of 9 bits. Therefore, the driver reads data
164 * from cache and makes value format according to the endianness of
165 * bytes type control element.
166 */
167 static int nau8810_eq_get(struct snd_kcontrol *kcontrol,
168 struct snd_ctl_elem_value *ucontrol)
169 {
170 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
171 struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
172 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
173 int i, reg, reg_val;
174 u16 *val;
175
176 val = (u16 *)ucontrol->value.bytes.data;
177 reg = NAU8810_REG_EQ1;
178 for (i = 0; i < params->max / sizeof(u16); i++) {
179 regmap_read(nau8810->regmap, reg + i, &reg_val);
180 /* conversion of 16-bit integers between native CPU format
181 * and big endian format
182 */
183 reg_val = cpu_to_be16(reg_val);
184 memcpy(val + i, &reg_val, sizeof(reg_val));
185 }
186
187 return 0;
188 }
189
190 /* The EQ parameters put function is to make configuration of 5 band equalizer
191 * control. These configuration includes central frequency, equalizer gain,
192 * cut-off frequency, bandwidth control, and equalizer path.
193 * The regmap raw write can't work here because regmap doesn't provide
194 * register and value format for register with address 7 bits and value 9 bits.
195 * Therefore, the driver makes value format according to the endianness of
196 * bytes type control element and writes data to codec.
197 */
198 static int nau8810_eq_put(struct snd_kcontrol *kcontrol,
199 struct snd_ctl_elem_value *ucontrol)
200 {
201 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
202 struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
203 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
204 void *data;
205 u16 *val, value;
206 int i, reg, ret;
207
208 data = kmemdup(ucontrol->value.bytes.data,
209 params->max, GFP_KERNEL | GFP_DMA);
210 if (!data)
211 return -ENOMEM;
212
213 val = (u16 *)data;
214 reg = NAU8810_REG_EQ1;
215 for (i = 0; i < params->max / sizeof(u16); i++) {
216 /* conversion of 16-bit integers between native CPU format
217 * and big endian format
218 */
219 value = be16_to_cpu(*(val + i));
220 ret = regmap_write(nau8810->regmap, reg + i, value);
221 if (ret) {
222 dev_err(component->dev, "EQ configuration fail, register: %x ret: %d\n",
223 reg + i, ret);
224 kfree(data);
225 return ret;
226 }
227 }
228 kfree(data);
229
230 return 0;
231 }
232
233 static const char * const nau8810_companding[] = {
234 "Off", "NC", "u-law", "A-law" };
235
236 static const struct soc_enum nau8810_companding_adc_enum =
237 SOC_ENUM_SINGLE(NAU8810_REG_COMP, NAU8810_ADCCM_SFT,
238 ARRAY_SIZE(nau8810_companding), nau8810_companding);
239
240 static const struct soc_enum nau8810_companding_dac_enum =
241 SOC_ENUM_SINGLE(NAU8810_REG_COMP, NAU8810_DACCM_SFT,
242 ARRAY_SIZE(nau8810_companding), nau8810_companding);
243
244 static const char * const nau8810_deemp[] = {
245 "None", "32kHz", "44.1kHz", "48kHz" };
246
247 static const struct soc_enum nau8810_deemp_enum =
248 SOC_ENUM_SINGLE(NAU8810_REG_DAC, NAU8810_DEEMP_SFT,
249 ARRAY_SIZE(nau8810_deemp), nau8810_deemp);
250
251 static const char * const nau8810_eqmode[] = {"Capture", "Playback" };
252
253 static const struct soc_enum nau8810_eqmode_enum =
254 SOC_ENUM_SINGLE(NAU8810_REG_EQ1, NAU8810_EQM_SFT,
255 ARRAY_SIZE(nau8810_eqmode), nau8810_eqmode);
256
257 static const char * const nau8810_alc[] = {"Normal", "Limiter" };
258
259 static const struct soc_enum nau8810_alc_enum =
260 SOC_ENUM_SINGLE(NAU8810_REG_ALC3, NAU8810_ALCM_SFT,
261 ARRAY_SIZE(nau8810_alc), nau8810_alc);
262
263 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
264 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
265 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
266 static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
267
268 static const struct snd_kcontrol_new nau8810_snd_controls[] = {
269 SOC_ENUM("ADC Companding", nau8810_companding_adc_enum),
270 SOC_ENUM("DAC Companding", nau8810_companding_dac_enum),
271 SOC_ENUM("DAC De-emphasis", nau8810_deemp_enum),
272
273 SOC_ENUM("EQ Function", nau8810_eqmode_enum),
274 SND_SOC_BYTES_EXT("EQ Parameters", 10,
275 nau8810_eq_get, nau8810_eq_put),
276
277 SOC_SINGLE("DAC Inversion Switch", NAU8810_REG_DAC,
278 NAU8810_DACPL_SFT, 1, 0),
279 SOC_SINGLE_TLV("Playback Volume", NAU8810_REG_DACGAIN,
280 NAU8810_DACGAIN_SFT, 0xff, 0, digital_tlv),
281
282 SOC_SINGLE("High Pass Filter Switch", NAU8810_REG_ADC,
283 NAU8810_HPFEN_SFT, 1, 0),
284 SOC_SINGLE("High Pass Cut Off", NAU8810_REG_ADC,
285 NAU8810_HPF_SFT, 0x7, 0),
286
287 SOC_SINGLE("ADC Inversion Switch", NAU8810_REG_ADC,
288 NAU8810_ADCPL_SFT, 1, 0),
289 SOC_SINGLE_TLV("Capture Volume", NAU8810_REG_ADCGAIN,
290 NAU8810_ADCGAIN_SFT, 0xff, 0, digital_tlv),
291
292 SOC_SINGLE_TLV("EQ1 Volume", NAU8810_REG_EQ1,
293 NAU8810_EQ1GC_SFT, 0x18, 1, eq_tlv),
294 SOC_SINGLE_TLV("EQ2 Volume", NAU8810_REG_EQ2,
295 NAU8810_EQ2GC_SFT, 0x18, 1, eq_tlv),
296 SOC_SINGLE_TLV("EQ3 Volume", NAU8810_REG_EQ3,
297 NAU8810_EQ3GC_SFT, 0x18, 1, eq_tlv),
298 SOC_SINGLE_TLV("EQ4 Volume", NAU8810_REG_EQ4,
299 NAU8810_EQ4GC_SFT, 0x18, 1, eq_tlv),
300 SOC_SINGLE_TLV("EQ5 Volume", NAU8810_REG_EQ5,
301 NAU8810_EQ5GC_SFT, 0x18, 1, eq_tlv),
302
303 SOC_SINGLE("DAC Limiter Switch", NAU8810_REG_DACLIM1,
304 NAU8810_DACLIMEN_SFT, 1, 0),
305 SOC_SINGLE("DAC Limiter Decay", NAU8810_REG_DACLIM1,
306 NAU8810_DACLIMDCY_SFT, 0xf, 0),
307 SOC_SINGLE("DAC Limiter Attack", NAU8810_REG_DACLIM1,
308 NAU8810_DACLIMATK_SFT, 0xf, 0),
309 SOC_SINGLE("DAC Limiter Threshold", NAU8810_REG_DACLIM2,
310 NAU8810_DACLIMTHL_SFT, 0x7, 0),
311 SOC_SINGLE("DAC Limiter Boost", NAU8810_REG_DACLIM2,
312 NAU8810_DACLIMBST_SFT, 0xf, 0),
313
314 SOC_ENUM("ALC Mode", nau8810_alc_enum),
315 SOC_SINGLE("ALC Enable Switch", NAU8810_REG_ALC1,
316 NAU8810_ALCEN_SFT, 1, 0),
317 SOC_SINGLE("ALC Max Volume", NAU8810_REG_ALC1,
318 NAU8810_ALCMXGAIN_SFT, 0x7, 0),
319 SOC_SINGLE("ALC Min Volume", NAU8810_REG_ALC1,
320 NAU8810_ALCMINGAIN_SFT, 0x7, 0),
321 SOC_SINGLE("ALC ZC Switch", NAU8810_REG_ALC2,
322 NAU8810_ALCZC_SFT, 1, 0),
323 SOC_SINGLE("ALC Hold", NAU8810_REG_ALC2,
324 NAU8810_ALCHT_SFT, 0xf, 0),
325 SOC_SINGLE("ALC Target", NAU8810_REG_ALC2,
326 NAU8810_ALCSL_SFT, 0xf, 0),
327 SOC_SINGLE("ALC Decay", NAU8810_REG_ALC3,
328 NAU8810_ALCDCY_SFT, 0xf, 0),
329 SOC_SINGLE("ALC Attack", NAU8810_REG_ALC3,
330 NAU8810_ALCATK_SFT, 0xf, 0),
331 SOC_SINGLE("ALC Noise Gate Switch", NAU8810_REG_NOISEGATE,
332 NAU8810_ALCNEN_SFT, 1, 0),
333 SOC_SINGLE("ALC Noise Gate Threshold", NAU8810_REG_NOISEGATE,
334 NAU8810_ALCNTH_SFT, 0x7, 0),
335
336 SOC_SINGLE("PGA ZC Switch", NAU8810_REG_PGAGAIN,
337 NAU8810_PGAZC_SFT, 1, 0),
338 SOC_SINGLE_TLV("PGA Volume", NAU8810_REG_PGAGAIN,
339 NAU8810_PGAGAIN_SFT, 0x3f, 0, inpga_tlv),
340
341 SOC_SINGLE("Speaker ZC Switch", NAU8810_REG_SPKGAIN,
342 NAU8810_SPKZC_SFT, 1, 0),
343 SOC_SINGLE("Speaker Mute Switch", NAU8810_REG_SPKGAIN,
344 NAU8810_SPKMT_SFT, 1, 0),
345 SOC_SINGLE_TLV("Speaker Volume", NAU8810_REG_SPKGAIN,
346 NAU8810_SPKGAIN_SFT, 0x3f, 0, spk_tlv),
347
348 SOC_SINGLE("Capture Boost(+20dB)", NAU8810_REG_ADCBOOST,
349 NAU8810_PGABST_SFT, 1, 0),
350 SOC_SINGLE("Mono Mute Switch", NAU8810_REG_MONOMIX,
351 NAU8810_MOUTMXMT_SFT, 1, 0),
352
353 SOC_SINGLE("DAC Oversampling Rate(128x) Switch", NAU8810_REG_DAC,
354 NAU8810_DACOS_SFT, 1, 0),
355 SOC_SINGLE("ADC Oversampling Rate(128x) Switch", NAU8810_REG_ADC,
356 NAU8810_ADCOS_SFT, 1, 0),
357 };
358
359 /* Speaker Output Mixer */
360 static const struct snd_kcontrol_new nau8810_speaker_mixer_controls[] = {
361 SOC_DAPM_SINGLE("Line Bypass Switch", NAU8810_REG_SPKMIX,
362 NAU8810_BYPSPK_SFT, 1, 0),
363 SOC_DAPM_SINGLE("PCM Playback Switch", NAU8810_REG_SPKMIX,
364 NAU8810_DACSPK_SFT, 1, 0),
365 };
366
367 /* Mono Output Mixer */
368 static const struct snd_kcontrol_new nau8810_mono_mixer_controls[] = {
369 SOC_DAPM_SINGLE("Line Bypass Switch", NAU8810_REG_MONOMIX,
370 NAU8810_BYPMOUT_SFT, 1, 0),
371 SOC_DAPM_SINGLE("PCM Playback Switch", NAU8810_REG_MONOMIX,
372 NAU8810_DACMOUT_SFT, 1, 0),
373 };
374
375 /* PGA Mute */
376 static const struct snd_kcontrol_new nau8810_pgaboost_mixer_controls[] = {
377 SOC_DAPM_SINGLE("PGA Mute Switch", NAU8810_REG_PGAGAIN,
378 NAU8810_PGAMT_SFT, 1, 1),
379 SOC_DAPM_SINGLE("PMIC PGA Switch", NAU8810_REG_ADCBOOST,
380 NAU8810_PMICBSTGAIN_SFT, 0x7, 0),
381 };
382
383 /* Input PGA */
384 static const struct snd_kcontrol_new nau8810_inpga[] = {
385 SOC_DAPM_SINGLE("MicN Switch", NAU8810_REG_INPUT_SIGNAL,
386 NAU8810_NMICPGA_SFT, 1, 0),
387 SOC_DAPM_SINGLE("MicP Switch", NAU8810_REG_INPUT_SIGNAL,
388 NAU8810_PMICPGA_SFT, 1, 0),
389 };
390
391 /* Loopback Switch */
392 static const struct snd_kcontrol_new nau8810_loopback =
393 SOC_DAPM_SINGLE("Switch", NAU8810_REG_COMP,
394 NAU8810_ADDAP_SFT, 1, 0);
395
396 static int check_mclk_select_pll(struct snd_soc_dapm_widget *source,
397 struct snd_soc_dapm_widget *sink)
398 {
399 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
400 struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
401 unsigned int value;
402
403 regmap_read(nau8810->regmap, NAU8810_REG_CLOCK, &value);
404 return (value & NAU8810_CLKM_MASK);
405 }
406
407 static const struct snd_soc_dapm_widget nau8810_dapm_widgets[] = {
408 SND_SOC_DAPM_MIXER("Speaker Mixer", NAU8810_REG_POWER3,
409 NAU8810_SPKMX_EN_SFT, 0, &nau8810_speaker_mixer_controls[0],
410 ARRAY_SIZE(nau8810_speaker_mixer_controls)),
411 SND_SOC_DAPM_MIXER("Mono Mixer", NAU8810_REG_POWER3,
412 NAU8810_MOUTMX_EN_SFT, 0, &nau8810_mono_mixer_controls[0],
413 ARRAY_SIZE(nau8810_mono_mixer_controls)),
414 SND_SOC_DAPM_DAC("DAC", "HiFi Playback", NAU8810_REG_POWER3,
415 NAU8810_DAC_EN_SFT, 0),
416 SND_SOC_DAPM_ADC("ADC", "HiFi Capture", NAU8810_REG_POWER2,
417 NAU8810_ADC_EN_SFT, 0),
418 SND_SOC_DAPM_PGA("SpkN Out", NAU8810_REG_POWER3,
419 NAU8810_NSPK_EN_SFT, 0, NULL, 0),
420 SND_SOC_DAPM_PGA("SpkP Out", NAU8810_REG_POWER3,
421 NAU8810_PSPK_EN_SFT, 0, NULL, 0),
422 SND_SOC_DAPM_PGA("Mono Out", NAU8810_REG_POWER3,
423 NAU8810_MOUT_EN_SFT, 0, NULL, 0),
424
425 SND_SOC_DAPM_MIXER("Input PGA", NAU8810_REG_POWER2,
426 NAU8810_PGA_EN_SFT, 0, nau8810_inpga,
427 ARRAY_SIZE(nau8810_inpga)),
428 SND_SOC_DAPM_MIXER("Input Boost Stage", NAU8810_REG_POWER2,
429 NAU8810_BST_EN_SFT, 0, nau8810_pgaboost_mixer_controls,
430 ARRAY_SIZE(nau8810_pgaboost_mixer_controls)),
431
432 SND_SOC_DAPM_SUPPLY("Mic Bias", NAU8810_REG_POWER1,
433 NAU8810_MICBIAS_EN_SFT, 0, NULL, 0),
434 SND_SOC_DAPM_SUPPLY("PLL", NAU8810_REG_POWER1,
435 NAU8810_PLL_EN_SFT, 0, NULL, 0),
436
437 SND_SOC_DAPM_SWITCH("Digital Loopback", SND_SOC_NOPM, 0, 0,
438 &nau8810_loopback),
439
440 SND_SOC_DAPM_INPUT("MICN"),
441 SND_SOC_DAPM_INPUT("MICP"),
442 SND_SOC_DAPM_OUTPUT("MONOOUT"),
443 SND_SOC_DAPM_OUTPUT("SPKOUTP"),
444 SND_SOC_DAPM_OUTPUT("SPKOUTN"),
445 };
446
447 static const struct snd_soc_dapm_route nau8810_dapm_routes[] = {
448 {"DAC", NULL, "PLL", check_mclk_select_pll},
449
450 /* Mono output mixer */
451 {"Mono Mixer", "PCM Playback Switch", "DAC"},
452 {"Mono Mixer", "Line Bypass Switch", "Input Boost Stage"},
453
454 /* Speaker output mixer */
455 {"Speaker Mixer", "PCM Playback Switch", "DAC"},
456 {"Speaker Mixer", "Line Bypass Switch", "Input Boost Stage"},
457
458 /* Outputs */
459 {"Mono Out", NULL, "Mono Mixer"},
460 {"MONOOUT", NULL, "Mono Out"},
461 {"SpkN Out", NULL, "Speaker Mixer"},
462 {"SpkP Out", NULL, "Speaker Mixer"},
463 {"SPKOUTN", NULL, "SpkN Out"},
464 {"SPKOUTP", NULL, "SpkP Out"},
465
466 /* Input Boost Stage */
467 {"ADC", NULL, "Input Boost Stage"},
468 {"ADC", NULL, "PLL", check_mclk_select_pll},
469 {"Input Boost Stage", "PGA Mute Switch", "Input PGA"},
470 {"Input Boost Stage", "PMIC PGA Switch", "MICP"},
471
472 /* Input PGA */
473 {"Input PGA", NULL, "Mic Bias"},
474 {"Input PGA", "MicN Switch", "MICN"},
475 {"Input PGA", "MicP Switch", "MICP"},
476
477 /* Digital Looptack */
478 {"Digital Loopback", "Switch", "ADC"},
479 {"DAC", NULL, "Digital Loopback"},
480 };
481
482 static int nau8810_set_sysclk(struct snd_soc_dai *dai,
483 int clk_id, unsigned int freq, int dir)
484 {
485 struct snd_soc_component *component = dai->component;
486 struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
487
488 nau8810->clk_id = clk_id;
489 nau8810->sysclk = freq;
490 dev_dbg(nau8810->dev, "master sysclk %dHz, source %s\n",
491 freq, clk_id == NAU8810_SCLK_PLL ? "PLL" : "MCLK");
492
493 return 0;
494 }
495
496 static int nau88l0_calc_pll(unsigned int pll_in,
497 unsigned int fs, struct nau8810_pll *pll_param)
498 {
499 u64 f2, f2_max, pll_ratio;
500 int i, scal_sel;
501
502 if (pll_in > NAU_PLL_REF_MAX || pll_in < NAU_PLL_REF_MIN)
503 return -EINVAL;
504
505 f2_max = 0;
506 scal_sel = ARRAY_SIZE(nau8810_mclk_scaler);
507 for (i = 0; i < ARRAY_SIZE(nau8810_mclk_scaler); i++) {
508 f2 = 256 * fs * 4 * nau8810_mclk_scaler[i] / 10;
509 if (f2 > NAU_PLL_FREQ_MIN && f2 < NAU_PLL_FREQ_MAX &&
510 f2_max < f2) {
511 f2_max = f2;
512 scal_sel = i;
513 }
514 }
515 if (ARRAY_SIZE(nau8810_mclk_scaler) == scal_sel)
516 return -EINVAL;
517 pll_param->mclk_scaler = scal_sel;
518 f2 = f2_max;
519
520 /* Calculate the PLL 4-bit integer input and the PLL 24-bit fractional
521 * input; round up the 24+4bit.
522 */
523 pll_ratio = div_u64(f2 << 28, pll_in);
524 pll_param->pre_factor = 0;
525 if (((pll_ratio >> 28) & 0xF) < NAU_PLL_OPTOP_MIN) {
526 pll_ratio <<= 1;
527 pll_param->pre_factor = 1;
528 }
529 pll_param->pll_int = (pll_ratio >> 28) & 0xF;
530 pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4);
531
532 return 0;
533 }
534
535 static int nau8810_set_pll(struct snd_soc_dai *codec_dai, int pll_id,
536 int source, unsigned int freq_in, unsigned int freq_out)
537 {
538 struct snd_soc_component *component = codec_dai->component;
539 struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
540 struct regmap *map = nau8810->regmap;
541 struct nau8810_pll *pll_param = &nau8810->pll;
542 int ret, fs;
543
544 fs = freq_out / 256;
545 ret = nau88l0_calc_pll(freq_in, fs, pll_param);
546 if (ret < 0) {
547 dev_err(nau8810->dev, "Unsupported input clock %d\n", freq_in);
548 return ret;
549 }
550 dev_info(nau8810->dev, "pll_int=%x pll_frac=%x mclk_scaler=%x pre_factor=%x\n",
551 pll_param->pll_int, pll_param->pll_frac, pll_param->mclk_scaler,
552 pll_param->pre_factor);
553
554 regmap_update_bits(map, NAU8810_REG_PLLN,
555 NAU8810_PLLMCLK_DIV2 | NAU8810_PLLN_MASK,
556 (pll_param->pre_factor ? NAU8810_PLLMCLK_DIV2 : 0) |
557 pll_param->pll_int);
558 regmap_write(map, NAU8810_REG_PLLK1,
559 (pll_param->pll_frac >> NAU8810_PLLK1_SFT) &
560 NAU8810_PLLK1_MASK);
561 regmap_write(map, NAU8810_REG_PLLK2,
562 (pll_param->pll_frac >> NAU8810_PLLK2_SFT) &
563 NAU8810_PLLK2_MASK);
564 regmap_write(map, NAU8810_REG_PLLK3,
565 pll_param->pll_frac & NAU8810_PLLK3_MASK);
566 regmap_update_bits(map, NAU8810_REG_CLOCK, NAU8810_MCLKSEL_MASK,
567 pll_param->mclk_scaler << NAU8810_MCLKSEL_SFT);
568 regmap_update_bits(map, NAU8810_REG_CLOCK,
569 NAU8810_CLKM_MASK, NAU8810_CLKM_PLL);
570
571 return 0;
572 }
573
574 static int nau8810_set_dai_fmt(struct snd_soc_dai *codec_dai,
575 unsigned int fmt)
576 {
577 struct snd_soc_component *component = codec_dai->component;
578 struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
579 u16 ctrl1_val = 0, ctrl2_val = 0;
580
581 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
582 case SND_SOC_DAIFMT_CBM_CFM:
583 ctrl2_val |= NAU8810_CLKIO_MASTER;
584 break;
585 case SND_SOC_DAIFMT_CBS_CFS:
586 break;
587 default:
588 return -EINVAL;
589 }
590
591 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
592 case SND_SOC_DAIFMT_I2S:
593 ctrl1_val |= NAU8810_AIFMT_I2S;
594 break;
595 case SND_SOC_DAIFMT_RIGHT_J:
596 break;
597 case SND_SOC_DAIFMT_LEFT_J:
598 ctrl1_val |= NAU8810_AIFMT_LEFT;
599 break;
600 case SND_SOC_DAIFMT_DSP_A:
601 ctrl1_val |= NAU8810_AIFMT_PCM_A;
602 break;
603 default:
604 return -EINVAL;
605 }
606
607 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
608 case SND_SOC_DAIFMT_NB_NF:
609 break;
610 case SND_SOC_DAIFMT_IB_IF:
611 ctrl1_val |= NAU8810_BCLKP_IB | NAU8810_FSP_IF;
612 break;
613 case SND_SOC_DAIFMT_IB_NF:
614 ctrl1_val |= NAU8810_BCLKP_IB;
615 break;
616 case SND_SOC_DAIFMT_NB_IF:
617 ctrl1_val |= NAU8810_FSP_IF;
618 break;
619 default:
620 return -EINVAL;
621 }
622
623 regmap_update_bits(nau8810->regmap, NAU8810_REG_IFACE,
624 NAU8810_AIFMT_MASK | NAU8810_FSP_IF |
625 NAU8810_BCLKP_IB, ctrl1_val);
626 regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK,
627 NAU8810_CLKIO_MASK, ctrl2_val);
628
629 return 0;
630 }
631
632 static int nau8810_mclk_clkdiv(struct nau8810 *nau8810, int rate)
633 {
634 int i, sclk, imclk = rate * 256, div = 0;
635
636 if (!nau8810->sysclk) {
637 dev_err(nau8810->dev, "Make mclk div configuration fail because of invalid system clock\n");
638 return -EINVAL;
639 }
640
641 /* Configure the master clock prescaler div to make system
642 * clock to approximate the internal master clock (IMCLK);
643 * and large or equal to IMCLK.
644 */
645 for (i = 1; i < ARRAY_SIZE(nau8810_mclk_scaler); i++) {
646 sclk = (nau8810->sysclk * 10) /
647 nau8810_mclk_scaler[i];
648 if (sclk < imclk)
649 break;
650 div = i;
651 }
652 dev_dbg(nau8810->dev,
653 "master clock prescaler %x for fs %d\n", div, rate);
654
655 /* master clock from MCLK and disable PLL */
656 regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK,
657 NAU8810_MCLKSEL_MASK, (div << NAU8810_MCLKSEL_SFT));
658 regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK,
659 NAU8810_CLKM_MASK, NAU8810_CLKM_MCLK);
660
661 return 0;
662 }
663
664 static int nau8810_pcm_hw_params(struct snd_pcm_substream *substream,
665 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
666 {
667 struct snd_soc_component *component = dai->component;
668 struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
669 int val_len = 0, val_rate = 0, ret = 0;
670
671 switch (params_width(params)) {
672 case 16:
673 break;
674 case 20:
675 val_len |= NAU8810_WLEN_20;
676 break;
677 case 24:
678 val_len |= NAU8810_WLEN_24;
679 break;
680 case 32:
681 val_len |= NAU8810_WLEN_32;
682 break;
683 }
684
685 switch (params_rate(params)) {
686 case 8000:
687 val_rate |= NAU8810_SMPLR_8K;
688 break;
689 case 11025:
690 val_rate |= NAU8810_SMPLR_12K;
691 break;
692 case 16000:
693 val_rate |= NAU8810_SMPLR_16K;
694 break;
695 case 22050:
696 val_rate |= NAU8810_SMPLR_24K;
697 break;
698 case 32000:
699 val_rate |= NAU8810_SMPLR_32K;
700 break;
701 case 44100:
702 case 48000:
703 break;
704 }
705
706 regmap_update_bits(nau8810->regmap, NAU8810_REG_IFACE,
707 NAU8810_WLEN_MASK, val_len);
708 regmap_update_bits(nau8810->regmap, NAU8810_REG_SMPLR,
709 NAU8810_SMPLR_MASK, val_rate);
710
711 /* If the master clock is from MCLK, provide the runtime FS for driver
712 * to get the master clock prescaler configuration.
713 */
714 if (nau8810->clk_id == NAU8810_SCLK_MCLK) {
715 ret = nau8810_mclk_clkdiv(nau8810, params_rate(params));
716 if (ret < 0)
717 dev_err(nau8810->dev, "MCLK div configuration fail\n");
718 }
719
720 return ret;
721 }
722
723 static int nau8810_set_bias_level(struct snd_soc_component *component,
724 enum snd_soc_bias_level level)
725 {
726 struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
727 struct regmap *map = nau8810->regmap;
728
729 switch (level) {
730 case SND_SOC_BIAS_ON:
731 case SND_SOC_BIAS_PREPARE:
732 regmap_update_bits(map, NAU8810_REG_POWER1,
733 NAU8810_REFIMP_MASK, NAU8810_REFIMP_80K);
734 break;
735
736 case SND_SOC_BIAS_STANDBY:
737 regmap_update_bits(map, NAU8810_REG_POWER1,
738 NAU8810_IOBUF_EN | NAU8810_ABIAS_EN,
739 NAU8810_IOBUF_EN | NAU8810_ABIAS_EN);
740
741 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
742 regcache_sync(map);
743 regmap_update_bits(map, NAU8810_REG_POWER1,
744 NAU8810_REFIMP_MASK, NAU8810_REFIMP_3K);
745 mdelay(100);
746 }
747 regmap_update_bits(map, NAU8810_REG_POWER1,
748 NAU8810_REFIMP_MASK, NAU8810_REFIMP_300K);
749 break;
750
751 case SND_SOC_BIAS_OFF:
752 regmap_write(map, NAU8810_REG_POWER1, 0);
753 regmap_write(map, NAU8810_REG_POWER2, 0);
754 regmap_write(map, NAU8810_REG_POWER3, 0);
755 break;
756 }
757
758 return 0;
759 }
760
761
762 #define NAU8810_RATES (SNDRV_PCM_RATE_8000_48000)
763
764 #define NAU8810_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
765 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
766
767 static const struct snd_soc_dai_ops nau8810_ops = {
768 .hw_params = nau8810_pcm_hw_params,
769 .set_fmt = nau8810_set_dai_fmt,
770 .set_sysclk = nau8810_set_sysclk,
771 .set_pll = nau8810_set_pll,
772 };
773
774 static struct snd_soc_dai_driver nau8810_dai = {
775 .name = "nau8810-hifi",
776 .playback = {
777 .stream_name = "Playback",
778 .channels_min = 1,
779 .channels_max = 2, /* Only 1 channel of data */
780 .rates = NAU8810_RATES,
781 .formats = NAU8810_FORMATS,
782 },
783 .capture = {
784 .stream_name = "Capture",
785 .channels_min = 1,
786 .channels_max = 2, /* Only 1 channel of data */
787 .rates = NAU8810_RATES,
788 .formats = NAU8810_FORMATS,
789 },
790 .ops = &nau8810_ops,
791 .symmetric_rates = 1,
792 };
793
794 static const struct regmap_config nau8810_regmap_config = {
795 .reg_bits = 7,
796 .val_bits = 9,
797
798 .max_register = NAU8810_REG_MAX,
799 .readable_reg = nau8810_readable_reg,
800 .writeable_reg = nau8810_writeable_reg,
801 .volatile_reg = nau8810_volatile_reg,
802
803 .cache_type = REGCACHE_RBTREE,
804 .reg_defaults = nau8810_reg_defaults,
805 .num_reg_defaults = ARRAY_SIZE(nau8810_reg_defaults),
806 };
807
808 static const struct snd_soc_component_driver nau8810_component_driver = {
809 .set_bias_level = nau8810_set_bias_level,
810 .controls = nau8810_snd_controls,
811 .num_controls = ARRAY_SIZE(nau8810_snd_controls),
812 .dapm_widgets = nau8810_dapm_widgets,
813 .num_dapm_widgets = ARRAY_SIZE(nau8810_dapm_widgets),
814 .dapm_routes = nau8810_dapm_routes,
815 .num_dapm_routes = ARRAY_SIZE(nau8810_dapm_routes),
816 .suspend_bias_off = 1,
817 .idle_bias_on = 1,
818 .use_pmdown_time = 1,
819 .endianness = 1,
820 .non_legacy_dai_naming = 1,
821 };
822
823 static int nau8810_i2c_probe(struct i2c_client *i2c,
824 const struct i2c_device_id *id)
825 {
826 struct device *dev = &i2c->dev;
827 struct nau8810 *nau8810 = dev_get_platdata(dev);
828
829 if (!nau8810) {
830 nau8810 = devm_kzalloc(dev, sizeof(*nau8810), GFP_KERNEL);
831 if (!nau8810)
832 return -ENOMEM;
833 }
834 i2c_set_clientdata(i2c, nau8810);
835
836 nau8810->regmap = devm_regmap_init_i2c(i2c, &nau8810_regmap_config);
837 if (IS_ERR(nau8810->regmap))
838 return PTR_ERR(nau8810->regmap);
839 nau8810->dev = dev;
840
841 regmap_write(nau8810->regmap, NAU8810_REG_RESET, 0x00);
842
843 return devm_snd_soc_register_component(dev,
844 &nau8810_component_driver, &nau8810_dai, 1);
845 }
846
847 static const struct i2c_device_id nau8810_i2c_id[] = {
848 { "nau8810", 0 },
849 { }
850 };
851 MODULE_DEVICE_TABLE(i2c, nau8810_i2c_id);
852
853 #ifdef CONFIG_OF
854 static const struct of_device_id nau8810_of_match[] = {
855 { .compatible = "nuvoton,nau8810", },
856 { }
857 };
858 MODULE_DEVICE_TABLE(of, nau8810_of_match);
859 #endif
860
861 static struct i2c_driver nau8810_i2c_driver = {
862 .driver = {
863 .name = "nau8810",
864 .of_match_table = of_match_ptr(nau8810_of_match),
865 },
866 .probe = nau8810_i2c_probe,
867 .id_table = nau8810_i2c_id,
868 };
869
870 module_i2c_driver(nau8810_i2c_driver);
871
872 MODULE_DESCRIPTION("ASoC NAU8810 driver");
873 MODULE_AUTHOR("David Lin <ctlin0@nuvoton.com>");
874 MODULE_LICENSE("GPL v2");
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