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Merge tag 'asoc-fix-v5.0-rc2' into asoc-5.1
[thirdparty/linux.git] / sound / soc / codecs / tlv320aic32x4.c
1 /*
2 * linux/sound/soc/codecs/tlv320aic32x4.c
3 *
4 * Copyright 2011 Vista Silicon S.L.
5 *
6 * Author: Javier Martin <javier.martin@vista-silicon.com>
7 *
8 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 * MA 02110-1301, USA.
24 */
25
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/init.h>
29 #include <linux/delay.h>
30 #include <linux/pm.h>
31 #include <linux/gpio.h>
32 #include <linux/of_gpio.h>
33 #include <linux/cdev.h>
34 #include <linux/slab.h>
35 #include <linux/clk.h>
36 #include <linux/regulator/consumer.h>
37
38 #include <sound/tlv320aic32x4.h>
39 #include <sound/core.h>
40 #include <sound/pcm.h>
41 #include <sound/pcm_params.h>
42 #include <sound/soc.h>
43 #include <sound/soc-dapm.h>
44 #include <sound/initval.h>
45 #include <sound/tlv.h>
46
47 #include "tlv320aic32x4.h"
48
49 struct aic32x4_rate_divs {
50 u32 mclk;
51 u32 rate;
52 u8 p_val;
53 u8 pll_j;
54 u16 pll_d;
55 u16 dosr;
56 u8 ndac;
57 u8 mdac;
58 u8 aosr;
59 u8 nadc;
60 u8 madc;
61 u8 blck_N;
62 };
63
64 struct aic32x4_priv {
65 struct regmap *regmap;
66 u32 sysclk;
67 u32 power_cfg;
68 u32 micpga_routing;
69 bool swapdacs;
70 int rstn_gpio;
71 struct clk *mclk;
72
73 struct regulator *supply_ldo;
74 struct regulator *supply_iov;
75 struct regulator *supply_dv;
76 struct regulator *supply_av;
77
78 struct aic32x4_setup_data *setup;
79 struct device *dev;
80 };
81
82 static int mic_bias_event(struct snd_soc_dapm_widget *w,
83 struct snd_kcontrol *kcontrol, int event)
84 {
85 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
86
87 switch (event) {
88 case SND_SOC_DAPM_POST_PMU:
89 /* Change Mic Bias Registor */
90 snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
91 AIC32x4_MICBIAS_MASK,
92 AIC32X4_MICBIAS_LDOIN |
93 AIC32X4_MICBIAS_2075V);
94 printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__);
95 break;
96 case SND_SOC_DAPM_PRE_PMD:
97 snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
98 AIC32x4_MICBIAS_MASK, 0);
99 printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n",
100 __func__);
101 break;
102 }
103
104 return 0;
105 }
106
107
108 static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol,
109 struct snd_ctl_elem_value *ucontrol)
110 {
111 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
112 u8 val;
113
114 val = snd_soc_component_read32(component, AIC32X4_DINCTL);
115
116 ucontrol->value.integer.value[0] = (val & 0x01);
117
118 return 0;
119 };
120
121 static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
122 struct snd_ctl_elem_value *ucontrol)
123 {
124 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
125 u8 val;
126 u8 gpio_check;
127
128 val = snd_soc_component_read32(component, AIC32X4_DOUTCTL);
129 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
130 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
131 printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n",
132 __func__);
133 return -EINVAL;
134 }
135
136 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH))
137 return 0;
138
139 if (ucontrol->value.integer.value[0])
140 val |= ucontrol->value.integer.value[0];
141 else
142 val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH;
143
144 snd_soc_component_write(component, AIC32X4_DOUTCTL, val);
145
146 return 0;
147 };
148
149 static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol,
150 struct snd_ctl_elem_value *ucontrol)
151 {
152 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
153 u8 val;
154
155 val = snd_soc_component_read32(component, AIC32X4_SCLKCTL);
156
157 ucontrol->value.integer.value[0] = (val & 0x01);
158
159 return 0;
160 };
161
162 static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
163 struct snd_ctl_elem_value *ucontrol)
164 {
165 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
166 u8 val;
167 u8 gpio_check;
168
169 val = snd_soc_component_read32(component, AIC32X4_MISOCTL);
170 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
171 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
172 printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n",
173 __func__);
174 return -EINVAL;
175 }
176
177 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH))
178 return 0;
179
180 if (ucontrol->value.integer.value[0])
181 val |= ucontrol->value.integer.value[0];
182 else
183 val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH;
184
185 snd_soc_component_write(component, AIC32X4_MISOCTL, val);
186
187 return 0;
188 };
189
190 static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol,
191 struct snd_ctl_elem_value *ucontrol)
192 {
193 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
194 u8 val;
195
196 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL);
197 ucontrol->value.integer.value[0] = ((val & 0x2) >> 1);
198
199 return 0;
200 };
201
202 static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol,
203 struct snd_ctl_elem_value *ucontrol)
204 {
205 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
206 u8 val;
207 u8 gpio_check;
208
209 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL);
210 gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT);
211 if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) {
212 printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n",
213 __func__);
214 return -EINVAL;
215 }
216
217 if (ucontrol->value.integer.value[0] == (val & 0x1))
218 return 0;
219
220 if (ucontrol->value.integer.value[0])
221 val |= ucontrol->value.integer.value[0];
222 else
223 val &= 0xfe;
224
225 snd_soc_component_write(component, AIC32X4_GPIOCTL, val);
226
227 return 0;
228 };
229
230 static const struct snd_kcontrol_new aic32x4_mfp1[] = {
231 SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL),
232 };
233
234 static const struct snd_kcontrol_new aic32x4_mfp2[] = {
235 SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio),
236 };
237
238 static const struct snd_kcontrol_new aic32x4_mfp3[] = {
239 SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL),
240 };
241
242 static const struct snd_kcontrol_new aic32x4_mfp4[] = {
243 SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio),
244 };
245
246 static const struct snd_kcontrol_new aic32x4_mfp5[] = {
247 SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio,
248 aic32x4_set_mfp5_gpio),
249 };
250
251 /* 0dB min, 0.5dB steps */
252 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
253 /* -63.5dB min, 0.5dB steps */
254 static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
255 /* -6dB min, 1dB steps */
256 static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
257 /* -12dB min, 0.5dB steps */
258 static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
259
260 static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
261 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
262 AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
263 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
264 AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
265 tlv_driver_gain),
266 SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
267 AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
268 tlv_driver_gain),
269 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
270 AIC32X4_HPRGAIN, 6, 0x01, 1),
271 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
272 AIC32X4_LORGAIN, 6, 0x01, 1),
273 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
274 AIC32X4_RMICPGAVOL, 7, 0x01, 1),
275
276 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
277 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
278
279 SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
280 AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
281 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
282 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
283
284 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
285
286 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
287 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
288 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
289 4, 0x07, 0),
290 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
291 0, 0x03, 0),
292 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
293 6, 0x03, 0),
294 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
295 1, 0x1F, 0),
296 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
297 0, 0x7F, 0),
298 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
299 3, 0x1F, 0),
300 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
301 3, 0x1F, 0),
302 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
303 0, 0x1F, 0),
304 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
305 0, 0x0F, 0),
306 };
307
308 static const struct aic32x4_rate_divs aic32x4_divs[] = {
309 /* 8k rate */
310 {12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},
311 {24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},
312 {25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24},
313 /* 11.025k rate */
314 {12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},
315 {24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},
316 /* 16k rate */
317 {12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},
318 {24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},
319 {25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12},
320 /* 22.05k rate */
321 {12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},
322 {24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},
323 {25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8},
324 /* 32k rate */
325 {12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},
326 {24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},
327 /* 44.1k rate */
328 {12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},
329 {24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},
330 {25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4},
331 /* 48k rate */
332 {12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
333 {24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
334 {25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4},
335
336 /* 96k rate */
337 {25000000, 96000, 2, 7, 8643, 64, 4, 4, 64, 4, 4, 1},
338 };
339
340 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
341 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
342 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
343 };
344
345 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
346 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
347 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
348 };
349
350 static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
351 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
352 };
353
354 static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
355 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
356 };
357
358 static const char * const resistor_text[] = {
359 "Off", "10 kOhm", "20 kOhm", "40 kOhm",
360 };
361
362 /* Left mixer pins */
363 static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text);
364 static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text);
365 static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text);
366 static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text);
367
368 static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text);
369 static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text);
370 static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text);
371
372 static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = {
373 SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum),
374 };
375 static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = {
376 SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum),
377 };
378 static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = {
379 SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum),
380 };
381 static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = {
382 SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum),
383 };
384 static const struct snd_kcontrol_new cml_to_lmixer_controls[] = {
385 SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum),
386 };
387 static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = {
388 SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum),
389 };
390 static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = {
391 SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
392 };
393
394 /* Right mixer pins */
395 static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text);
396 static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text);
397 static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text);
398 static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text);
399 static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text);
400 static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text);
401 static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text);
402
403 static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = {
404 SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum),
405 };
406 static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = {
407 SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum),
408 };
409 static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = {
410 SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum),
411 };
412 static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = {
413 SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum),
414 };
415 static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = {
416 SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum),
417 };
418 static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = {
419 SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum),
420 };
421 static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = {
422 SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum),
423 };
424
425 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
426 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
427 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
428 &hpl_output_mixer_controls[0],
429 ARRAY_SIZE(hpl_output_mixer_controls)),
430 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
431
432 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
433 &lol_output_mixer_controls[0],
434 ARRAY_SIZE(lol_output_mixer_controls)),
435 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
436
437 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
438 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
439 &hpr_output_mixer_controls[0],
440 ARRAY_SIZE(hpr_output_mixer_controls)),
441 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
442 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
443 &lor_output_mixer_controls[0],
444 ARRAY_SIZE(lor_output_mixer_controls)),
445 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
446
447 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
448 SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
449 in1r_to_rmixer_controls),
450 SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
451 in2r_to_rmixer_controls),
452 SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
453 in3r_to_rmixer_controls),
454 SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
455 in2l_to_rmixer_controls),
456 SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
457 cmr_to_rmixer_controls),
458 SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
459 in1l_to_rmixer_controls),
460 SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
461 in3l_to_rmixer_controls),
462
463 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
464 SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
465 in1l_to_lmixer_controls),
466 SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
467 in2l_to_lmixer_controls),
468 SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
469 in3l_to_lmixer_controls),
470 SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
471 in1r_to_lmixer_controls),
472 SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
473 cml_to_lmixer_controls),
474 SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
475 in2r_to_lmixer_controls),
476 SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
477 in3r_to_lmixer_controls),
478
479 SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event,
480 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
481
482
483 SND_SOC_DAPM_OUTPUT("HPL"),
484 SND_SOC_DAPM_OUTPUT("HPR"),
485 SND_SOC_DAPM_OUTPUT("LOL"),
486 SND_SOC_DAPM_OUTPUT("LOR"),
487 SND_SOC_DAPM_INPUT("IN1_L"),
488 SND_SOC_DAPM_INPUT("IN1_R"),
489 SND_SOC_DAPM_INPUT("IN2_L"),
490 SND_SOC_DAPM_INPUT("IN2_R"),
491 SND_SOC_DAPM_INPUT("IN3_L"),
492 SND_SOC_DAPM_INPUT("IN3_R"),
493 };
494
495 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
496 /* Left Output */
497 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
498 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
499
500 {"HPL Power", NULL, "HPL Output Mixer"},
501 {"HPL", NULL, "HPL Power"},
502
503 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
504
505 {"LOL Power", NULL, "LOL Output Mixer"},
506 {"LOL", NULL, "LOL Power"},
507
508 /* Right Output */
509 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
510 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
511
512 {"HPR Power", NULL, "HPR Output Mixer"},
513 {"HPR", NULL, "HPR Power"},
514
515 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
516
517 {"LOR Power", NULL, "LOR Output Mixer"},
518 {"LOR", NULL, "LOR Power"},
519
520 /* Right Input */
521 {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"},
522 {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"},
523 {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"},
524 {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"},
525
526 {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"},
527 {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"},
528 {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"},
529 {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"},
530
531 {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"},
532 {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"},
533 {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"},
534 {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"},
535
536 {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"},
537 {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"},
538 {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"},
539 {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"},
540
541 {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"},
542 {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"},
543 {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"},
544 {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"},
545
546 {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"},
547 {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"},
548 {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"},
549 {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"},
550
551 {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"},
552 {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"},
553 {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"},
554 {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"},
555
556 /* Left Input */
557 {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"},
558 {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"},
559 {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"},
560 {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"},
561
562 {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"},
563 {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"},
564 {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"},
565 {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"},
566
567 {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"},
568 {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"},
569 {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"},
570 {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"},
571
572 {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"},
573 {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"},
574 {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"},
575 {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"},
576
577 {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"},
578 {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"},
579 {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"},
580 {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"},
581
582 {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"},
583 {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"},
584 {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"},
585 {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"},
586
587 {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"},
588 {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"},
589 {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"},
590 {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"},
591 };
592
593 static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
594 {
595 .selector_reg = 0,
596 .selector_mask = 0xff,
597 .window_start = 0,
598 .window_len = 128,
599 .range_min = 0,
600 .range_max = AIC32X4_RMICPGAVOL,
601 },
602 };
603
604 const struct regmap_config aic32x4_regmap_config = {
605 .max_register = AIC32X4_RMICPGAVOL,
606 .ranges = aic32x4_regmap_pages,
607 .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
608 };
609 EXPORT_SYMBOL(aic32x4_regmap_config);
610
611 static inline int aic32x4_get_divs(int mclk, int rate)
612 {
613 int i;
614
615 for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
616 if ((aic32x4_divs[i].rate == rate)
617 && (aic32x4_divs[i].mclk == mclk)) {
618 return i;
619 }
620 }
621 printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n");
622 return -EINVAL;
623 }
624
625 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
626 int clk_id, unsigned int freq, int dir)
627 {
628 struct snd_soc_component *component = codec_dai->component;
629 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
630
631 switch (freq) {
632 case 12000000:
633 case 24000000:
634 case 25000000:
635 aic32x4->sysclk = freq;
636 return 0;
637 }
638 printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n");
639 return -EINVAL;
640 }
641
642 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
643 {
644 struct snd_soc_component *component = codec_dai->component;
645 u8 iface_reg_1 = 0;
646 u8 iface_reg_2 = 0;
647 u8 iface_reg_3 = 0;
648
649 /* set master/slave audio interface */
650 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
651 case SND_SOC_DAIFMT_CBM_CFM:
652 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
653 break;
654 case SND_SOC_DAIFMT_CBS_CFS:
655 break;
656 default:
657 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
658 return -EINVAL;
659 }
660
661 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
662 case SND_SOC_DAIFMT_I2S:
663 break;
664 case SND_SOC_DAIFMT_DSP_A:
665 iface_reg_1 |= (AIC32X4_DSP_MODE <<
666 AIC32X4_IFACE1_DATATYPE_SHIFT);
667 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
668 iface_reg_2 = 0x01; /* add offset 1 */
669 break;
670 case SND_SOC_DAIFMT_DSP_B:
671 iface_reg_1 |= (AIC32X4_DSP_MODE <<
672 AIC32X4_IFACE1_DATATYPE_SHIFT);
673 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
674 break;
675 case SND_SOC_DAIFMT_RIGHT_J:
676 iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE <<
677 AIC32X4_IFACE1_DATATYPE_SHIFT);
678 break;
679 case SND_SOC_DAIFMT_LEFT_J:
680 iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE <<
681 AIC32X4_IFACE1_DATATYPE_SHIFT);
682 break;
683 default:
684 printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
685 return -EINVAL;
686 }
687
688 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
689 AIC32X4_IFACE1_DATATYPE_MASK |
690 AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
691 snd_soc_component_update_bits(component, AIC32X4_IFACE2,
692 AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
693 snd_soc_component_update_bits(component, AIC32X4_IFACE3,
694 AIC32X4_BCLKINV_MASK, iface_reg_3);
695
696 return 0;
697 }
698
699 static int aic32x4_hw_params(struct snd_pcm_substream *substream,
700 struct snd_pcm_hw_params *params,
701 struct snd_soc_dai *dai)
702 {
703 struct snd_soc_component *component = dai->component;
704 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
705 u8 iface1_reg = 0;
706 u8 dacsetup_reg = 0;
707 int i;
708
709 i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params));
710 if (i < 0) {
711 printk(KERN_ERR "aic32x4: sampling rate not supported\n");
712 return i;
713 }
714
715 /* MCLK as PLL_CLKIN */
716 snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_PLL_CLKIN_MASK,
717 AIC32X4_PLL_CLKIN_MCLK << AIC32X4_PLL_CLKIN_SHIFT);
718 /* PLL as CODEC_CLKIN */
719 snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_CODEC_CLKIN_MASK,
720 AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT);
721 /* DAC_MOD_CLK as BDIV_CLKIN */
722 snd_soc_component_update_bits(component, AIC32X4_IFACE3, AIC32X4_BDIVCLK_MASK,
723 AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
724
725 /* We will fix R value to 1 and will make P & J=K.D as variable */
726 snd_soc_component_update_bits(component, AIC32X4_PLLPR, AIC32X4_PLL_R_MASK, 0x01);
727
728 /* PLL P value */
729 snd_soc_component_update_bits(component, AIC32X4_PLLPR, AIC32X4_PLL_P_MASK,
730 aic32x4_divs[i].p_val << AIC32X4_PLL_P_SHIFT);
731
732 /* PLL J value */
733 snd_soc_component_write(component, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
734
735 /* PLL D value */
736 snd_soc_component_write(component, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
737 snd_soc_component_write(component, AIC32X4_PLLDLSB, (aic32x4_divs[i].pll_d & 0xff));
738
739 /* NDAC divider value */
740 snd_soc_component_update_bits(component, AIC32X4_NDAC,
741 AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac);
742
743 /* MDAC divider value */
744 snd_soc_component_update_bits(component, AIC32X4_MDAC,
745 AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac);
746
747 /* DOSR MSB & LSB values */
748 snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
749 snd_soc_component_write(component, AIC32X4_DOSRLSB, (aic32x4_divs[i].dosr & 0xff));
750
751 /* NADC divider value */
752 snd_soc_component_update_bits(component, AIC32X4_NADC,
753 AIC32X4_NADC_MASK, aic32x4_divs[i].nadc);
754
755 /* MADC divider value */
756 snd_soc_component_update_bits(component, AIC32X4_MADC,
757 AIC32X4_MADC_MASK, aic32x4_divs[i].madc);
758
759 /* AOSR value */
760 snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr);
761
762 /* BCLK N divider */
763 snd_soc_component_update_bits(component, AIC32X4_BCLKN,
764 AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N);
765
766 switch (params_width(params)) {
767 case 16:
768 iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
769 AIC32X4_IFACE1_DATALEN_SHIFT);
770 break;
771 case 20:
772 iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
773 AIC32X4_IFACE1_DATALEN_SHIFT);
774 break;
775 case 24:
776 iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
777 AIC32X4_IFACE1_DATALEN_SHIFT);
778 break;
779 case 32:
780 iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
781 AIC32X4_IFACE1_DATALEN_SHIFT);
782 break;
783 }
784 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
785 AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
786
787 if (params_channels(params) == 1) {
788 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
789 } else {
790 if (aic32x4->swapdacs)
791 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
792 else
793 dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
794 }
795 snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
796 AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
797
798 return 0;
799 }
800
801 static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
802 {
803 struct snd_soc_component *component = dai->component;
804
805 snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
806 AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
807
808 return 0;
809 }
810
811 static int aic32x4_set_bias_level(struct snd_soc_component *component,
812 enum snd_soc_bias_level level)
813 {
814 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
815 int ret;
816
817 switch (level) {
818 case SND_SOC_BIAS_ON:
819 /* Switch on master clock */
820 ret = clk_prepare_enable(aic32x4->mclk);
821 if (ret) {
822 dev_err(component->dev, "Failed to enable master clock\n");
823 return ret;
824 }
825
826 /* Switch on PLL */
827 snd_soc_component_update_bits(component, AIC32X4_PLLPR,
828 AIC32X4_PLLEN, AIC32X4_PLLEN);
829
830 /* Switch on NDAC Divider */
831 snd_soc_component_update_bits(component, AIC32X4_NDAC,
832 AIC32X4_NDACEN, AIC32X4_NDACEN);
833
834 /* Switch on MDAC Divider */
835 snd_soc_component_update_bits(component, AIC32X4_MDAC,
836 AIC32X4_MDACEN, AIC32X4_MDACEN);
837
838 /* Switch on NADC Divider */
839 snd_soc_component_update_bits(component, AIC32X4_NADC,
840 AIC32X4_NADCEN, AIC32X4_NADCEN);
841
842 /* Switch on MADC Divider */
843 snd_soc_component_update_bits(component, AIC32X4_MADC,
844 AIC32X4_MADCEN, AIC32X4_MADCEN);
845
846 /* Switch on BCLK_N Divider */
847 snd_soc_component_update_bits(component, AIC32X4_BCLKN,
848 AIC32X4_BCLKEN, AIC32X4_BCLKEN);
849 break;
850 case SND_SOC_BIAS_PREPARE:
851 break;
852 case SND_SOC_BIAS_STANDBY:
853 /* Initial cold start */
854 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
855 break;
856
857 /* Switch off BCLK_N Divider */
858 snd_soc_component_update_bits(component, AIC32X4_BCLKN,
859 AIC32X4_BCLKEN, 0);
860
861 /* Switch off MADC Divider */
862 snd_soc_component_update_bits(component, AIC32X4_MADC,
863 AIC32X4_MADCEN, 0);
864
865 /* Switch off NADC Divider */
866 snd_soc_component_update_bits(component, AIC32X4_NADC,
867 AIC32X4_NADCEN, 0);
868
869 /* Switch off MDAC Divider */
870 snd_soc_component_update_bits(component, AIC32X4_MDAC,
871 AIC32X4_MDACEN, 0);
872
873 /* Switch off NDAC Divider */
874 snd_soc_component_update_bits(component, AIC32X4_NDAC,
875 AIC32X4_NDACEN, 0);
876
877 /* Switch off PLL */
878 snd_soc_component_update_bits(component, AIC32X4_PLLPR,
879 AIC32X4_PLLEN, 0);
880
881 /* Switch off master clock */
882 clk_disable_unprepare(aic32x4->mclk);
883 break;
884 case SND_SOC_BIAS_OFF:
885 break;
886 }
887 return 0;
888 }
889
890 #define AIC32X4_RATES SNDRV_PCM_RATE_8000_96000
891 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
892 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
893
894 static const struct snd_soc_dai_ops aic32x4_ops = {
895 .hw_params = aic32x4_hw_params,
896 .digital_mute = aic32x4_mute,
897 .set_fmt = aic32x4_set_dai_fmt,
898 .set_sysclk = aic32x4_set_dai_sysclk,
899 };
900
901 static struct snd_soc_dai_driver aic32x4_dai = {
902 .name = "tlv320aic32x4-hifi",
903 .playback = {
904 .stream_name = "Playback",
905 .channels_min = 1,
906 .channels_max = 2,
907 .rates = AIC32X4_RATES,
908 .formats = AIC32X4_FORMATS,},
909 .capture = {
910 .stream_name = "Capture",
911 .channels_min = 1,
912 .channels_max = 2,
913 .rates = AIC32X4_RATES,
914 .formats = AIC32X4_FORMATS,},
915 .ops = &aic32x4_ops,
916 .symmetric_rates = 1,
917 };
918
919 static void aic32x4_setup_gpios(struct snd_soc_component *component)
920 {
921 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
922
923 /* setup GPIO functions */
924 /* MFP1 */
925 if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) {
926 snd_soc_component_write(component, AIC32X4_DINCTL,
927 aic32x4->setup->gpio_func[0]);
928 snd_soc_add_component_controls(component, aic32x4_mfp1,
929 ARRAY_SIZE(aic32x4_mfp1));
930 }
931
932 /* MFP2 */
933 if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) {
934 snd_soc_component_write(component, AIC32X4_DOUTCTL,
935 aic32x4->setup->gpio_func[1]);
936 snd_soc_add_component_controls(component, aic32x4_mfp2,
937 ARRAY_SIZE(aic32x4_mfp2));
938 }
939
940 /* MFP3 */
941 if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) {
942 snd_soc_component_write(component, AIC32X4_SCLKCTL,
943 aic32x4->setup->gpio_func[2]);
944 snd_soc_add_component_controls(component, aic32x4_mfp3,
945 ARRAY_SIZE(aic32x4_mfp3));
946 }
947
948 /* MFP4 */
949 if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) {
950 snd_soc_component_write(component, AIC32X4_MISOCTL,
951 aic32x4->setup->gpio_func[3]);
952 snd_soc_add_component_controls(component, aic32x4_mfp4,
953 ARRAY_SIZE(aic32x4_mfp4));
954 }
955
956 /* MFP5 */
957 if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) {
958 snd_soc_component_write(component, AIC32X4_GPIOCTL,
959 aic32x4->setup->gpio_func[4]);
960 snd_soc_add_component_controls(component, aic32x4_mfp5,
961 ARRAY_SIZE(aic32x4_mfp5));
962 }
963 }
964
965 static int aic32x4_component_probe(struct snd_soc_component *component)
966 {
967 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
968 u32 tmp_reg;
969
970 if (gpio_is_valid(aic32x4->rstn_gpio)) {
971 ndelay(10);
972 gpio_set_value(aic32x4->rstn_gpio, 1);
973 }
974
975 snd_soc_component_write(component, AIC32X4_RESET, 0x01);
976
977 if (aic32x4->setup)
978 aic32x4_setup_gpios(component);
979
980 /* Power platform configuration */
981 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
982 snd_soc_component_write(component, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
983 AIC32X4_MICBIAS_2075V);
984 }
985 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
986 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
987
988 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
989 AIC32X4_LDOCTLEN : 0;
990 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
991
992 tmp_reg = snd_soc_component_read32(component, AIC32X4_CMMODE);
993 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
994 tmp_reg |= AIC32X4_LDOIN_18_36;
995 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
996 tmp_reg |= AIC32X4_LDOIN2HP;
997 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
998
999 /* Mic PGA routing */
1000 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
1001 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
1002 AIC32X4_LMICPGANIN_IN2R_10K);
1003 else
1004 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
1005 AIC32X4_LMICPGANIN_CM1L_10K);
1006 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
1007 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
1008 AIC32X4_RMICPGANIN_IN1L_10K);
1009 else
1010 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
1011 AIC32X4_RMICPGANIN_CM1R_10K);
1012
1013 /*
1014 * Workaround: for an unknown reason, the ADC needs to be powered up
1015 * and down for the first capture to work properly. It seems related to
1016 * a HW BUG or some kind of behavior not documented in the datasheet.
1017 */
1018 tmp_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP);
1019 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg |
1020 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
1021 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg);
1022
1023 return 0;
1024 }
1025
1026 static const struct snd_soc_component_driver soc_component_dev_aic32x4 = {
1027 .probe = aic32x4_component_probe,
1028 .set_bias_level = aic32x4_set_bias_level,
1029 .controls = aic32x4_snd_controls,
1030 .num_controls = ARRAY_SIZE(aic32x4_snd_controls),
1031 .dapm_widgets = aic32x4_dapm_widgets,
1032 .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
1033 .dapm_routes = aic32x4_dapm_routes,
1034 .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
1035 .suspend_bias_off = 1,
1036 .idle_bias_on = 1,
1037 .use_pmdown_time = 1,
1038 .endianness = 1,
1039 .non_legacy_dai_naming = 1,
1040 };
1041
1042 static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
1043 struct device_node *np)
1044 {
1045 struct aic32x4_setup_data *aic32x4_setup;
1046
1047 aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup),
1048 GFP_KERNEL);
1049 if (!aic32x4_setup)
1050 return -ENOMEM;
1051
1052 aic32x4->swapdacs = false;
1053 aic32x4->micpga_routing = 0;
1054 aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
1055
1056 if (of_property_read_u32_array(np, "aic32x4-gpio-func",
1057 aic32x4_setup->gpio_func, 5) >= 0)
1058 aic32x4->setup = aic32x4_setup;
1059 return 0;
1060 }
1061
1062 static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
1063 {
1064 regulator_disable(aic32x4->supply_iov);
1065
1066 if (!IS_ERR(aic32x4->supply_ldo))
1067 regulator_disable(aic32x4->supply_ldo);
1068
1069 if (!IS_ERR(aic32x4->supply_dv))
1070 regulator_disable(aic32x4->supply_dv);
1071
1072 if (!IS_ERR(aic32x4->supply_av))
1073 regulator_disable(aic32x4->supply_av);
1074 }
1075
1076 static int aic32x4_setup_regulators(struct device *dev,
1077 struct aic32x4_priv *aic32x4)
1078 {
1079 int ret = 0;
1080
1081 aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin");
1082 aic32x4->supply_iov = devm_regulator_get(dev, "iov");
1083 aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv");
1084 aic32x4->supply_av = devm_regulator_get_optional(dev, "av");
1085
1086 /* Check if the regulator requirements are fulfilled */
1087
1088 if (IS_ERR(aic32x4->supply_iov)) {
1089 dev_err(dev, "Missing supply 'iov'\n");
1090 return PTR_ERR(aic32x4->supply_iov);
1091 }
1092
1093 if (IS_ERR(aic32x4->supply_ldo)) {
1094 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER)
1095 return -EPROBE_DEFER;
1096
1097 if (IS_ERR(aic32x4->supply_dv)) {
1098 dev_err(dev, "Missing supply 'dv' or 'ldoin'\n");
1099 return PTR_ERR(aic32x4->supply_dv);
1100 }
1101 if (IS_ERR(aic32x4->supply_av)) {
1102 dev_err(dev, "Missing supply 'av' or 'ldoin'\n");
1103 return PTR_ERR(aic32x4->supply_av);
1104 }
1105 } else {
1106 if (IS_ERR(aic32x4->supply_dv) &&
1107 PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER)
1108 return -EPROBE_DEFER;
1109 if (IS_ERR(aic32x4->supply_av) &&
1110 PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER)
1111 return -EPROBE_DEFER;
1112 }
1113
1114 ret = regulator_enable(aic32x4->supply_iov);
1115 if (ret) {
1116 dev_err(dev, "Failed to enable regulator iov\n");
1117 return ret;
1118 }
1119
1120 if (!IS_ERR(aic32x4->supply_ldo)) {
1121 ret = regulator_enable(aic32x4->supply_ldo);
1122 if (ret) {
1123 dev_err(dev, "Failed to enable regulator ldo\n");
1124 goto error_ldo;
1125 }
1126 }
1127
1128 if (!IS_ERR(aic32x4->supply_dv)) {
1129 ret = regulator_enable(aic32x4->supply_dv);
1130 if (ret) {
1131 dev_err(dev, "Failed to enable regulator dv\n");
1132 goto error_dv;
1133 }
1134 }
1135
1136 if (!IS_ERR(aic32x4->supply_av)) {
1137 ret = regulator_enable(aic32x4->supply_av);
1138 if (ret) {
1139 dev_err(dev, "Failed to enable regulator av\n");
1140 goto error_av;
1141 }
1142 }
1143
1144 if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av))
1145 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE;
1146
1147 return 0;
1148
1149 error_av:
1150 if (!IS_ERR(aic32x4->supply_dv))
1151 regulator_disable(aic32x4->supply_dv);
1152
1153 error_dv:
1154 if (!IS_ERR(aic32x4->supply_ldo))
1155 regulator_disable(aic32x4->supply_ldo);
1156
1157 error_ldo:
1158 regulator_disable(aic32x4->supply_iov);
1159 return ret;
1160 }
1161
1162 int aic32x4_probe(struct device *dev, struct regmap *regmap)
1163 {
1164 struct aic32x4_priv *aic32x4;
1165 struct aic32x4_pdata *pdata = dev->platform_data;
1166 struct device_node *np = dev->of_node;
1167 int ret;
1168
1169 if (IS_ERR(regmap))
1170 return PTR_ERR(regmap);
1171
1172 aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
1173 GFP_KERNEL);
1174 if (aic32x4 == NULL)
1175 return -ENOMEM;
1176
1177 aic32x4->dev = dev;
1178 dev_set_drvdata(dev, aic32x4);
1179
1180 if (pdata) {
1181 aic32x4->power_cfg = pdata->power_cfg;
1182 aic32x4->swapdacs = pdata->swapdacs;
1183 aic32x4->micpga_routing = pdata->micpga_routing;
1184 aic32x4->rstn_gpio = pdata->rstn_gpio;
1185 } else if (np) {
1186 ret = aic32x4_parse_dt(aic32x4, np);
1187 if (ret) {
1188 dev_err(dev, "Failed to parse DT node\n");
1189 return ret;
1190 }
1191 } else {
1192 aic32x4->power_cfg = 0;
1193 aic32x4->swapdacs = false;
1194 aic32x4->micpga_routing = 0;
1195 aic32x4->rstn_gpio = -1;
1196 }
1197
1198 aic32x4->mclk = devm_clk_get(dev, "mclk");
1199 if (IS_ERR(aic32x4->mclk)) {
1200 dev_err(dev, "Failed getting the mclk. The current implementation does not support the usage of this codec without mclk\n");
1201 return PTR_ERR(aic32x4->mclk);
1202 }
1203
1204 if (gpio_is_valid(aic32x4->rstn_gpio)) {
1205 ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio,
1206 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
1207 if (ret != 0)
1208 return ret;
1209 }
1210
1211 ret = aic32x4_setup_regulators(dev, aic32x4);
1212 if (ret) {
1213 dev_err(dev, "Failed to setup regulators\n");
1214 return ret;
1215 }
1216
1217 ret = devm_snd_soc_register_component(dev,
1218 &soc_component_dev_aic32x4, &aic32x4_dai, 1);
1219 if (ret) {
1220 dev_err(dev, "Failed to register component\n");
1221 aic32x4_disable_regulators(aic32x4);
1222 return ret;
1223 }
1224
1225 return 0;
1226 }
1227 EXPORT_SYMBOL(aic32x4_probe);
1228
1229 int aic32x4_remove(struct device *dev)
1230 {
1231 struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev);
1232
1233 aic32x4_disable_regulators(aic32x4);
1234
1235 return 0;
1236 }
1237 EXPORT_SYMBOL(aic32x4_remove);
1238
1239 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
1240 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
1241 MODULE_LICENSE("GPL");
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