]> git.ipfire.org Git - thirdparty/u-boot.git/blob - src/arm/broadcom/bcm2711.dtsi
projects / thirdparty / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Squashed 'dts/upstream/' content from commit aaba2d45dc2a
[thirdparty/u-boot.git] / src / arm / broadcom / bcm2711.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 #include "bcm283x.dtsi"
3
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
6
7 / {
8 compatible = "brcm,bcm2711";
9
10 #address-cells = <2>;
11 #size-cells = <1>;
12
13 interrupt-parent = <&gicv2>;
14
15 vc4: gpu {
16 compatible = "brcm,bcm2711-vc5";
17 status = "disabled";
18 };
19
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <27000000>;
24 clock-output-names = "27MHz-clock";
25 };
26
27 clk_108MHz: clk-108M {
28 #clock-cells = <0>;
29 compatible = "fixed-clock";
30 clock-frequency = <108000000>;
31 clock-output-names = "108MHz-clock";
32 };
33
34 soc {
35 /*
36 * Defined ranges:
37 * Common BCM283x peripherals
38 * BCM2711-specific peripherals
39 * ARM-local peripherals
40 */
41 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
42 <0x7c000000 0x0 0xfc000000 0x02000000>,
43 <0x40000000 0x0 0xff800000 0x00800000>;
44 /* Emulate a contiguous 30-bit address range for DMA */
45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
46
47 /*
48 * This node is the provider for the enable-method for
49 * bringing up secondary cores.
50 */
51 local_intc: interrupt-controller@40000000 {
52 compatible = "brcm,bcm2836-l1-intc";
53 reg = <0x40000000 0x100>;
54 };
55
56 gicv2: interrupt-controller@40041000 {
57 interrupt-controller;
58 #interrupt-cells = <3>;
59 compatible = "arm,gic-400";
60 reg = <0x40041000 0x1000>,
61 <0x40042000 0x2000>,
62 <0x40044000 0x2000>,
63 <0x40046000 0x2000>;
64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
65 IRQ_TYPE_LEVEL_HIGH)>;
66 };
67
68 avs_monitor: avs-monitor@7d5d2000 {
69 compatible = "brcm,bcm2711-avs-monitor",
70 "syscon", "simple-mfd";
71 reg = <0x7d5d2000 0xf00>;
72
73 thermal: thermal {
74 compatible = "brcm,bcm2711-thermal";
75 #thermal-sensor-cells = <0>;
76 };
77 };
78
79 dma: dma-controller@7e007000 {
80 compatible = "brcm,bcm2835-dma";
81 reg = <0x7e007000 0xb00>;
82 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
89 /* DMA lite 7 - 10 */
90 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
94 interrupt-names = "dma0",
95 "dma1",
96 "dma2",
97 "dma3",
98 "dma4",
99 "dma5",
100 "dma6",
101 "dma7",
102 "dma8",
103 "dma9",
104 "dma10";
105 #dma-cells = <1>;
106 brcm,dma-channel-mask = <0x07f5>;
107 };
108
109 pm: watchdog@7e100000 {
110 compatible = "brcm,bcm2711-pm", "brcm,bcm2835-pm-wdt";
111 #power-domain-cells = <1>;
112 #reset-cells = <1>;
113 reg = <0x7e100000 0x114>,
114 <0x7e00a000 0x24>,
115 <0x7ec11000 0x20>;
116 reg-names = "pm", "asb", "rpivid_asb";
117 clocks = <&clocks BCM2835_CLOCK_V3D>,
118 <&clocks BCM2835_CLOCK_PERI_IMAGE>,
119 <&clocks BCM2835_CLOCK_H264>,
120 <&clocks BCM2835_CLOCK_ISP>;
121 clock-names = "v3d", "peri_image", "h264", "isp";
122 system-power-controller;
123 };
124
125 rng@7e104000 {
126 compatible = "brcm,bcm2711-rng200";
127 reg = <0x7e104000 0x28>;
128 };
129
130 uart2: serial@7e201400 {
131 compatible = "arm,pl011", "arm,primecell";
132 reg = <0x7e201400 0x200>;
133 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&clocks BCM2835_CLOCK_UART>,
135 <&clocks BCM2835_CLOCK_VPU>;
136 clock-names = "uartclk", "apb_pclk";
137 arm,primecell-periphid = <0x00241011>;
138 status = "disabled";
139 };
140
141 uart3: serial@7e201600 {
142 compatible = "arm,pl011", "arm,primecell";
143 reg = <0x7e201600 0x200>;
144 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&clocks BCM2835_CLOCK_UART>,
146 <&clocks BCM2835_CLOCK_VPU>;
147 clock-names = "uartclk", "apb_pclk";
148 arm,primecell-periphid = <0x00241011>;
149 status = "disabled";
150 };
151
152 uart4: serial@7e201800 {
153 compatible = "arm,pl011", "arm,primecell";
154 reg = <0x7e201800 0x200>;
155 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&clocks BCM2835_CLOCK_UART>,
157 <&clocks BCM2835_CLOCK_VPU>;
158 clock-names = "uartclk", "apb_pclk";
159 arm,primecell-periphid = <0x00241011>;
160 status = "disabled";
161 };
162
163 uart5: serial@7e201a00 {
164 compatible = "arm,pl011", "arm,primecell";
165 reg = <0x7e201a00 0x200>;
166 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
167 clocks = <&clocks BCM2835_CLOCK_UART>,
168 <&clocks BCM2835_CLOCK_VPU>;
169 clock-names = "uartclk", "apb_pclk";
170 arm,primecell-periphid = <0x00241011>;
171 status = "disabled";
172 };
173
174 spi3: spi@7e204600 {
175 compatible = "brcm,bcm2835-spi";
176 reg = <0x7e204600 0x0200>;
177 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&clocks BCM2835_CLOCK_VPU>;
179 #address-cells = <1>;
180 #size-cells = <0>;
181 status = "disabled";
182 };
183
184 spi4: spi@7e204800 {
185 compatible = "brcm,bcm2835-spi";
186 reg = <0x7e204800 0x0200>;
187 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&clocks BCM2835_CLOCK_VPU>;
189 #address-cells = <1>;
190 #size-cells = <0>;
191 status = "disabled";
192 };
193
194 spi5: spi@7e204a00 {
195 compatible = "brcm,bcm2835-spi";
196 reg = <0x7e204a00 0x0200>;
197 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&clocks BCM2835_CLOCK_VPU>;
199 #address-cells = <1>;
200 #size-cells = <0>;
201 status = "disabled";
202 };
203
204 spi6: spi@7e204c00 {
205 compatible = "brcm,bcm2835-spi";
206 reg = <0x7e204c00 0x0200>;
207 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&clocks BCM2835_CLOCK_VPU>;
209 #address-cells = <1>;
210 #size-cells = <0>;
211 status = "disabled";
212 };
213
214 i2c3: i2c@7e205600 {
215 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
216 reg = <0x7e205600 0x200>;
217 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&clocks BCM2835_CLOCK_VPU>;
219 #address-cells = <1>;
220 #size-cells = <0>;
221 status = "disabled";
222 };
223
224 i2c4: i2c@7e205800 {
225 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
226 reg = <0x7e205800 0x200>;
227 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&clocks BCM2835_CLOCK_VPU>;
229 #address-cells = <1>;
230 #size-cells = <0>;
231 status = "disabled";
232 };
233
234 i2c5: i2c@7e205a00 {
235 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
236 reg = <0x7e205a00 0x200>;
237 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&clocks BCM2835_CLOCK_VPU>;
239 #address-cells = <1>;
240 #size-cells = <0>;
241 status = "disabled";
242 };
243
244 i2c6: i2c@7e205c00 {
245 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
246 reg = <0x7e205c00 0x200>;
247 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&clocks BCM2835_CLOCK_VPU>;
249 #address-cells = <1>;
250 #size-cells = <0>;
251 status = "disabled";
252 };
253
254 pixelvalve0: pixelvalve@7e206000 {
255 compatible = "brcm,bcm2711-pixelvalve0";
256 reg = <0x7e206000 0x100>;
257 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
258 status = "disabled";
259 };
260
261 pixelvalve1: pixelvalve@7e207000 {
262 compatible = "brcm,bcm2711-pixelvalve1";
263 reg = <0x7e207000 0x100>;
264 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
265 status = "disabled";
266 };
267
268 pixelvalve2: pixelvalve@7e20a000 {
269 compatible = "brcm,bcm2711-pixelvalve2";
270 reg = <0x7e20a000 0x100>;
271 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
272 status = "disabled";
273 };
274
275 pwm1: pwm@7e20c800 {
276 compatible = "brcm,bcm2835-pwm";
277 reg = <0x7e20c800 0x28>;
278 clocks = <&clocks BCM2835_CLOCK_PWM>;
279 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
280 assigned-clock-rates = <10000000>;
281 #pwm-cells = <3>;
282 status = "disabled";
283 };
284
285 pixelvalve4: pixelvalve@7e216000 {
286 compatible = "brcm,bcm2711-pixelvalve4";
287 reg = <0x7e216000 0x100>;
288 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
289 status = "disabled";
290 };
291
292 hvs: hvs@7e400000 {
293 compatible = "brcm,bcm2711-hvs";
294 reg = <0x7e400000 0x8000>;
295 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
296 };
297
298 pixelvalve3: pixelvalve@7ec12000 {
299 compatible = "brcm,bcm2711-pixelvalve3";
300 reg = <0x7ec12000 0x100>;
301 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
302 status = "disabled";
303 };
304
305 vec: vec@7ec13000 {
306 compatible = "brcm,bcm2711-vec";
307 reg = <0x7ec13000 0x1000>;
308 clocks = <&clocks BCM2835_CLOCK_VEC>;
309 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
310 status = "disabled";
311 };
312
313 dvp: clock@7ef00000 {
314 compatible = "brcm,brcm2711-dvp";
315 reg = <0x7ef00000 0x10>;
316 clocks = <&clk_108MHz>;
317 #clock-cells = <1>;
318 #reset-cells = <1>;
319 };
320
321 aon_intr: interrupt-controller@7ef00100 {
322 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
323 reg = <0x7ef00100 0x30>;
324 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
325 interrupt-controller;
326 #interrupt-cells = <1>;
327 };
328
329 hdmi0: hdmi@7ef00700 {
330 compatible = "brcm,bcm2711-hdmi0";
331 reg = <0x7ef00700 0x300>,
332 <0x7ef00300 0x200>,
333 <0x7ef00f00 0x80>,
334 <0x7ef00f80 0x80>,
335 <0x7ef01b00 0x200>,
336 <0x7ef01f00 0x400>,
337 <0x7ef00200 0x80>,
338 <0x7ef04300 0x100>,
339 <0x7ef20000 0x100>;
340 reg-names = "hdmi",
341 "dvp",
342 "phy",
343 "rm",
344 "packet",
345 "metadata",
346 "csc",
347 "cec",
348 "hd";
349 clock-names = "hdmi", "bvb", "audio", "cec";
350 resets = <&dvp 0>;
351 interrupt-parent = <&aon_intr>;
352 interrupts = <0>, <1>, <2>,
353 <3>, <4>, <5>;
354 interrupt-names = "cec-tx", "cec-rx", "cec-low",
355 "wakeup", "hpd-connected", "hpd-removed";
356 ddc = <&ddc0>;
357 dmas = <&dma 10>;
358 dma-names = "audio-rx";
359 status = "disabled";
360 };
361
362 ddc0: i2c@7ef04500 {
363 compatible = "brcm,bcm2711-hdmi-i2c";
364 reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
365 reg-names = "bsc", "auto-i2c";
366 clock-frequency = <97500>;
367 status = "disabled";
368 };
369
370 hdmi1: hdmi@7ef05700 {
371 compatible = "brcm,bcm2711-hdmi1";
372 reg = <0x7ef05700 0x300>,
373 <0x7ef05300 0x200>,
374 <0x7ef05f00 0x80>,
375 <0x7ef05f80 0x80>,
376 <0x7ef06b00 0x200>,
377 <0x7ef06f00 0x400>,
378 <0x7ef00280 0x80>,
379 <0x7ef09300 0x100>,
380 <0x7ef20000 0x100>;
381 reg-names = "hdmi",
382 "dvp",
383 "phy",
384 "rm",
385 "packet",
386 "metadata",
387 "csc",
388 "cec",
389 "hd";
390 ddc = <&ddc1>;
391 clock-names = "hdmi", "bvb", "audio", "cec";
392 resets = <&dvp 1>;
393 interrupt-parent = <&aon_intr>;
394 interrupts = <8>, <7>, <6>,
395 <9>, <10>, <11>;
396 interrupt-names = "cec-tx", "cec-rx", "cec-low",
397 "wakeup", "hpd-connected", "hpd-removed";
398 dmas = <&dma 17>;
399 dma-names = "audio-rx";
400 status = "disabled";
401 };
402
403 ddc1: i2c@7ef09500 {
404 compatible = "brcm,bcm2711-hdmi-i2c";
405 reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
406 reg-names = "bsc", "auto-i2c";
407 clock-frequency = <97500>;
408 status = "disabled";
409 };
410 };
411
412 /*
413 * emmc2 has different DMA constraints based on SoC revisions. It was
414 * moved into its own bus, so as for RPi4's firmware to update them.
415 * The firmware will find whether the emmc2bus alias is defined, and if
416 * so, it'll edit the dma-ranges property below accordingly.
417 */
418 emmc2bus: emmc2bus {
419 compatible = "simple-bus";
420 #address-cells = <2>;
421 #size-cells = <1>;
422
423 ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
424 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
425
426 emmc2: mmc@7e340000 {
427 compatible = "brcm,bcm2711-emmc2";
428 reg = <0x0 0x7e340000 0x100>;
429 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&clocks BCM2711_CLOCK_EMMC2>;
431 status = "disabled";
432 };
433 };
434
435 arm-pmu {
436 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
437 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
441 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
442 };
443
444 timer {
445 compatible = "arm,armv8-timer";
446 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
447 IRQ_TYPE_LEVEL_LOW)>,
448 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
449 IRQ_TYPE_LEVEL_LOW)>,
450 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
451 IRQ_TYPE_LEVEL_LOW)>,
452 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
453 IRQ_TYPE_LEVEL_LOW)>;
454 /* This only applies to the ARMv7 stub */
455 arm,cpu-registers-not-fw-configured;
456 };
457
458 cpus: cpus {
459 #address-cells = <1>;
460 #size-cells = <0>;
461 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
462
463 /* Source for d/i-cache-line-size and d/i-cache-sets
464 * https://developer.arm.com/documentation/100095/0003
465 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en
466 * Source for d/i-cache-size
467 * https://www.raspberrypi.com/documentation/computers
468 * /processors.html#bcm2711
469 */
470 cpu0: cpu@0 {
471 device_type = "cpu";
472 compatible = "arm,cortex-a72";
473 reg = <0>;
474 enable-method = "spin-table";
475 cpu-release-addr = <0x0 0x000000d8>;
476 d-cache-size = <0x8000>;
477 d-cache-line-size = <64>;
478 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
479 i-cache-size = <0xc000>;
480 i-cache-line-size = <64>;
481 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
482 next-level-cache = <&l2>;
483 };
484
485 cpu1: cpu@1 {
486 device_type = "cpu";
487 compatible = "arm,cortex-a72";
488 reg = <1>;
489 enable-method = "spin-table";
490 cpu-release-addr = <0x0 0x000000e0>;
491 d-cache-size = <0x8000>;
492 d-cache-line-size = <64>;
493 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
494 i-cache-size = <0xc000>;
495 i-cache-line-size = <64>;
496 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
497 next-level-cache = <&l2>;
498 };
499
500 cpu2: cpu@2 {
501 device_type = "cpu";
502 compatible = "arm,cortex-a72";
503 reg = <2>;
504 enable-method = "spin-table";
505 cpu-release-addr = <0x0 0x000000e8>;
506 d-cache-size = <0x8000>;
507 d-cache-line-size = <64>;
508 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
509 i-cache-size = <0xc000>;
510 i-cache-line-size = <64>;
511 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
512 next-level-cache = <&l2>;
513 };
514
515 cpu3: cpu@3 {
516 device_type = "cpu";
517 compatible = "arm,cortex-a72";
518 reg = <3>;
519 enable-method = "spin-table";
520 cpu-release-addr = <0x0 0x000000f0>;
521 d-cache-size = <0x8000>;
522 d-cache-line-size = <64>;
523 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
524 i-cache-size = <0xc000>;
525 i-cache-line-size = <64>;
526 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
527 next-level-cache = <&l2>;
528 };
529
530 /* Source for d/i-cache-line-size and d/i-cache-sets
531 * https://developer.arm.com/documentation/100095/0003
532 * /Level-2-Memory-System/About-the-L2-memory-system?lang=en
533 * Source for d/i-cache-size
534 * https://www.raspberrypi.com/documentation/computers
535 * /processors.html#bcm2711
536 */
537 l2: l2-cache0 {
538 compatible = "cache";
539 cache-unified;
540 cache-size = <0x100000>;
541 cache-line-size = <64>;
542 cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
543 cache-level = <2>;
544 };
545 };
546
547 scb {
548 compatible = "simple-bus";
549 #address-cells = <2>;
550 #size-cells = <1>;
551
552 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
553 <0x6 0x00000000 0x6 0x00000000 0x40000000>;
554
555 pcie0: pcie@7d500000 {
556 compatible = "brcm,bcm2711-pcie";
557 reg = <0x0 0x7d500000 0x9310>;
558 device_type = "pci";
559 #address-cells = <3>;
560 #interrupt-cells = <1>;
561 #size-cells = <2>;
562 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
564 interrupt-names = "pcie", "msi";
565 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
566 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
567 IRQ_TYPE_LEVEL_HIGH>,
568 <0 0 0 2 &gicv2 GIC_SPI 144
569 IRQ_TYPE_LEVEL_HIGH>,
570 <0 0 0 3 &gicv2 GIC_SPI 145
571 IRQ_TYPE_LEVEL_HIGH>,
572 <0 0 0 4 &gicv2 GIC_SPI 146
573 IRQ_TYPE_LEVEL_HIGH>;
574 msi-controller;
575 msi-parent = <&pcie0>;
576
577 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
578 0x0 0x04000000>;
579 /*
580 * The wrapper around the PCIe block has a bug
581 * preventing it from accessing beyond the first 3GB of
582 * memory.
583 */
584 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
585 0x0 0xc0000000>;
586 brcm,enable-ssc;
587 };
588
589 genet: ethernet@7d580000 {
590 compatible = "brcm,bcm2711-genet-v5";
591 reg = <0x0 0x7d580000 0x10000>;
592 #address-cells = <0x1>;
593 #size-cells = <0x1>;
594 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
596 status = "disabled";
597
598 genet_mdio: mdio@e14 {
599 compatible = "brcm,genet-mdio-v5";
600 reg = <0xe14 0x8>;
601 reg-names = "mdio";
602 #address-cells = <0x1>;
603 #size-cells = <0x0>;
604 };
605 };
606
607 v3d: gpu@7ec00000 {
608 compatible = "brcm,2711-v3d";
609 reg = <0x0 0x7ec00000 0x4000>,
610 <0x0 0x7ec04000 0x4000>;
611 reg-names = "hub", "core0";
612
613 power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
614 resets = <&pm BCM2835_RESET_V3D>;
615 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
616 };
617 };
618 };
619
620 &clk_osc {
621 clock-frequency = <54000000>;
622 };
623
624 &clocks {
625 compatible = "brcm,bcm2711-cprman";
626 };
627
628 &cpu_thermal {
629 coefficients = <(-487) 410040>;
630 thermal-sensors = <&thermal>;
631 };
632
633 &dsi0 {
634 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
635 };
636
637 &dsi1 {
638 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
639 compatible = "brcm,bcm2711-dsi1";
640 };
641
642 &gpio {
643 compatible = "brcm,bcm2711-gpio";
644 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
648
649 gpio-ranges = <&gpio 0 0 58>;
650
651 gpclk0_gpio49: gpclk0-gpio49 {
652 pin-gpclk {
653 pins = "gpio49";
654 function = "alt1";
655 bias-disable;
656 };
657 };
658 gpclk1_gpio50: gpclk1-gpio50 {
659 pin-gpclk {
660 pins = "gpio50";
661 function = "alt1";
662 bias-disable;
663 };
664 };
665 gpclk2_gpio51: gpclk2-gpio51 {
666 pin-gpclk {
667 pins = "gpio51";
668 function = "alt1";
669 bias-disable;
670 };
671 };
672
673 i2c0_gpio46: i2c0-gpio46 {
674 pin-sda {
675 function = "alt0";
676 pins = "gpio46";
677 bias-pull-up;
678 };
679 pin-scl {
680 function = "alt0";
681 pins = "gpio47";
682 bias-disable;
683 };
684 };
685 i2c1_gpio46: i2c1-gpio46 {
686 pin-sda {
687 function = "alt1";
688 pins = "gpio46";
689 bias-pull-up;
690 };
691 pin-scl {
692 function = "alt1";
693 pins = "gpio47";
694 bias-disable;
695 };
696 };
697 i2c3_gpio2: i2c3-gpio2 {
698 pin-sda {
699 function = "alt5";
700 pins = "gpio2";
701 bias-pull-up;
702 };
703 pin-scl {
704 function = "alt5";
705 pins = "gpio3";
706 bias-disable;
707 };
708 };
709 i2c3_gpio4: i2c3-gpio4 {
710 pin-sda {
711 function = "alt5";
712 pins = "gpio4";
713 bias-pull-up;
714 };
715 pin-scl {
716 function = "alt5";
717 pins = "gpio5";
718 bias-disable;
719 };
720 };
721 i2c4_gpio6: i2c4-gpio6 {
722 pin-sda {
723 function = "alt5";
724 pins = "gpio6";
725 bias-pull-up;
726 };
727 pin-scl {
728 function = "alt5";
729 pins = "gpio7";
730 bias-disable;
731 };
732 };
733 i2c4_gpio8: i2c4-gpio8 {
734 pin-sda {
735 function = "alt5";
736 pins = "gpio8";
737 bias-pull-up;
738 };
739 pin-scl {
740 function = "alt5";
741 pins = "gpio9";
742 bias-disable;
743 };
744 };
745 i2c5_gpio10: i2c5-gpio10 {
746 pin-sda {
747 function = "alt5";
748 pins = "gpio10";
749 bias-pull-up;
750 };
751 pin-scl {
752 function = "alt5";
753 pins = "gpio11";
754 bias-disable;
755 };
756 };
757 i2c5_gpio12: i2c5-gpio12 {
758 pin-sda {
759 function = "alt5";
760 pins = "gpio12";
761 bias-pull-up;
762 };
763 pin-scl {
764 function = "alt5";
765 pins = "gpio13";
766 bias-disable;
767 };
768 };
769 i2c6_gpio0: i2c6-gpio0 {
770 pin-sda {
771 function = "alt5";
772 pins = "gpio0";
773 bias-pull-up;
774 };
775 pin-scl {
776 function = "alt5";
777 pins = "gpio1";
778 bias-disable;
779 };
780 };
781 i2c6_gpio22: i2c6-gpio22 {
782 pin-sda {
783 function = "alt5";
784 pins = "gpio22";
785 bias-pull-up;
786 };
787 pin-scl {
788 function = "alt5";
789 pins = "gpio23";
790 bias-disable;
791 };
792 };
793 i2c_slave_gpio8: i2c-slave-gpio8 {
794 pins-i2c-slave {
795 pins = "gpio8",
796 "gpio9",
797 "gpio10",
798 "gpio11";
799 function = "alt3";
800 };
801 };
802
803 jtag_gpio48: jtag-gpio48 {
804 pins-jtag {
805 pins = "gpio48",
806 "gpio49",
807 "gpio50",
808 "gpio51",
809 "gpio52",
810 "gpio53";
811 function = "alt4";
812 };
813 };
814
815 mii_gpio28: mii-gpio28 {
816 pins-mii {
817 pins = "gpio28",
818 "gpio29",
819 "gpio30",
820 "gpio31";
821 function = "alt4";
822 };
823 };
824 mii_gpio36: mii-gpio36 {
825 pins-mii {
826 pins = "gpio36",
827 "gpio37",
828 "gpio38",
829 "gpio39";
830 function = "alt5";
831 };
832 };
833
834 pcm_gpio50: pcm-gpio50 {
835 pins-pcm {
836 pins = "gpio50",
837 "gpio51",
838 "gpio52",
839 "gpio53";
840 function = "alt2";
841 };
842 };
843
844 pwm0_0_gpio12: pwm0-0-gpio12 {
845 pin-pwm {
846 pins = "gpio12";
847 function = "alt0";
848 bias-disable;
849 };
850 };
851 pwm0_0_gpio18: pwm0-0-gpio18 {
852 pin-pwm {
853 pins = "gpio18";
854 function = "alt5";
855 bias-disable;
856 };
857 };
858 pwm1_0_gpio40: pwm1-0-gpio40 {
859 pin-pwm {
860 pins = "gpio40";
861 function = "alt0";
862 bias-disable;
863 };
864 };
865 pwm0_1_gpio13: pwm0-1-gpio13 {
866 pin-pwm {
867 pins = "gpio13";
868 function = "alt0";
869 bias-disable;
870 };
871 };
872 pwm0_1_gpio19: pwm0-1-gpio19 {
873 pin-pwm {
874 pins = "gpio19";
875 function = "alt5";
876 bias-disable;
877 };
878 };
879 pwm1_1_gpio41: pwm1-1-gpio41 {
880 pin-pwm {
881 pins = "gpio41";
882 function = "alt0";
883 bias-disable;
884 };
885 };
886 pwm0_1_gpio45: pwm0-1-gpio45 {
887 pin-pwm {
888 pins = "gpio45";
889 function = "alt0";
890 bias-disable;
891 };
892 };
893 pwm0_0_gpio52: pwm0-0-gpio52 {
894 pin-pwm {
895 pins = "gpio52";
896 function = "alt1";
897 bias-disable;
898 };
899 };
900 pwm0_1_gpio53: pwm0-1-gpio53 {
901 pin-pwm {
902 pins = "gpio53";
903 function = "alt1";
904 bias-disable;
905 };
906 };
907
908 rgmii_gpio35: rgmii-gpio35 {
909 pin-start-stop {
910 pins = "gpio35";
911 function = "alt4";
912 };
913 pin-rx-ok {
914 pins = "gpio36";
915 function = "alt4";
916 };
917 };
918 rgmii_irq_gpio34: rgmii-irq-gpio34 {
919 pin-irq {
920 pins = "gpio34";
921 function = "alt5";
922 };
923 };
924 rgmii_irq_gpio39: rgmii-irq-gpio39 {
925 pin-irq {
926 pins = "gpio39";
927 function = "alt4";
928 };
929 };
930 rgmii_mdio_gpio28: rgmii-mdio-gpio28 {
931 pins-mdio {
932 pins = "gpio28",
933 "gpio29";
934 function = "alt5";
935 };
936 };
937 rgmii_mdio_gpio37: rgmii-mdio-gpio37 {
938 pins-mdio {
939 pins = "gpio37",
940 "gpio38";
941 function = "alt4";
942 };
943 };
944
945 spi0_gpio46: spi0-gpio46 {
946 pins-spi {
947 pins = "gpio46",
948 "gpio47",
949 "gpio48",
950 "gpio49";
951 function = "alt2";
952 };
953 };
954 spi2_gpio46: spi2-gpio46 {
955 pins-spi {
956 pins = "gpio46",
957 "gpio47",
958 "gpio48",
959 "gpio49",
960 "gpio50";
961 function = "alt5";
962 };
963 };
964 spi3_gpio0: spi3-gpio0 {
965 pins-spi {
966 pins = "gpio0",
967 "gpio1",
968 "gpio2",
969 "gpio3";
970 function = "alt3";
971 };
972 };
973 spi4_gpio4: spi4-gpio4 {
974 pins-spi {
975 pins = "gpio4",
976 "gpio5",
977 "gpio6",
978 "gpio7";
979 function = "alt3";
980 };
981 };
982 spi5_gpio12: spi5-gpio12 {
983 pins-spi {
984 pins = "gpio12",
985 "gpio13",
986 "gpio14",
987 "gpio15";
988 function = "alt3";
989 };
990 };
991 spi6_gpio18: spi6-gpio18 {
992 pins-spi {
993 pins = "gpio18",
994 "gpio19",
995 "gpio20",
996 "gpio21";
997 function = "alt3";
998 };
999 };
1000
1001 uart2_gpio0: uart2-gpio0 {
1002 pin-tx {
1003 pins = "gpio0";
1004 function = "alt4";
1005 bias-disable;
1006 };
1007 pin-rx {
1008 pins = "gpio1";
1009 function = "alt4";
1010 bias-pull-up;
1011 };
1012 };
1013 uart2_ctsrts_gpio2: uart2-ctsrts-gpio2 {
1014 pin-cts {
1015 pins = "gpio2";
1016 function = "alt4";
1017 bias-pull-up;
1018 };
1019 pin-rts {
1020 pins = "gpio3";
1021 function = "alt4";
1022 bias-disable;
1023 };
1024 };
1025 uart3_gpio4: uart3-gpio4 {
1026 pin-tx {
1027 pins = "gpio4";
1028 function = "alt4";
1029 bias-disable;
1030 };
1031 pin-rx {
1032 pins = "gpio5";
1033 function = "alt4";
1034 bias-pull-up;
1035 };
1036 };
1037 uart3_ctsrts_gpio6: uart3-ctsrts-gpio6 {
1038 pin-cts {
1039 pins = "gpio6";
1040 function = "alt4";
1041 bias-pull-up;
1042 };
1043 pin-rts {
1044 pins = "gpio7";
1045 function = "alt4";
1046 bias-disable;
1047 };
1048 };
1049 uart4_gpio8: uart4-gpio8 {
1050 pin-tx {
1051 pins = "gpio8";
1052 function = "alt4";
1053 bias-disable;
1054 };
1055 pin-rx {
1056 pins = "gpio9";
1057 function = "alt4";
1058 bias-pull-up;
1059 };
1060 };
1061 uart4_ctsrts_gpio10: uart4-ctsrts-gpio10 {
1062 pin-cts {
1063 pins = "gpio10";
1064 function = "alt4";
1065 bias-pull-up;
1066 };
1067 pin-rts {
1068 pins = "gpio11";
1069 function = "alt4";
1070 bias-disable;
1071 };
1072 };
1073 uart5_gpio12: uart5-gpio12 {
1074 pin-tx {
1075 pins = "gpio12";
1076 function = "alt4";
1077 bias-disable;
1078 };
1079 pin-rx {
1080 pins = "gpio13";
1081 function = "alt4";
1082 bias-pull-up;
1083 };
1084 };
1085 uart5_ctsrts_gpio14: uart5-ctsrts-gpio14 {
1086 pin-cts {
1087 pins = "gpio14";
1088 function = "alt4";
1089 bias-pull-up;
1090 };
1091 pin-rts {
1092 pins = "gpio15";
1093 function = "alt4";
1094 bias-disable;
1095 };
1096 };
1097 };
1098
1099 &rmem {
1100 #address-cells = <2>;
1101 };
1102
1103 &cma {
1104 /*
1105 * arm64 reserves the CMA by default somewhere in ZONE_DMA32,
1106 * that's not good enough for the BCM2711 as some devices can
1107 * only address the lower 1G of memory (ZONE_DMA).
1108 */
1109 alloc-ranges = <0x0 0x00000000 0x40000000>;
1110 };
1111
1112 &i2c0 {
1113 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1114 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1115 };
1116
1117 &i2c1 {
1118 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1119 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1120 };
1121
1122 &mailbox {
1123 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1124 };
1125
1126 &sdhci {
1127 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1128 };
1129
1130 &sdhost {
1131 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1132 };
1133
1134 &spi {
1135 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1136 };
1137
1138 &spi1 {
1139 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1140 };
1141
1142 &spi2 {
1143 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1144 };
1145
1146 &system_timer {
1147 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1148 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1149 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
1150 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1151 };
1152
1153 &txp {
1154 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1155 };
1156
1157 &uart0 {
1158 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1159 };
1160
1161 &uart1 {
1162 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1163 };
1164
1165 &usb {
1166 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1167 };
1168
1169 &vec {
1170 compatible = "brcm,bcm2711-vec";
1171 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1172 };
"Das U-Boot" Source Tree