1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2022 Broadcom Ltd.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "brcm,bcm47622", "brcm,bcmbca";
14 interrupt-parent = <&gic>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
25 enable-method = "psci";
30 compatible = "arm,cortex-a7";
32 next-level-cache = <&L2_0>;
33 enable-method = "psci";
38 compatible = "arm,cortex-a7";
40 next-level-cache = <&L2_0>;
41 enable-method = "psci";
46 compatible = "arm,cortex-a7";
48 next-level-cache = <&L2_0>;
49 enable-method = "psci";
60 compatible = "arm,armv7-timer";
61 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
64 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
65 arm,cpu-registers-not-fw-configured;
69 compatible = "arm,cortex-a7-pmu";
70 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
74 interrupt-affinity = <&CA7_0>, <&CA7_1>,
79 periph_clk: periph-clk {
80 compatible = "fixed-clock";
82 clock-frequency = <200000000>;
86 compatible = "fixed-factor-clock";
88 clocks = <&periph_clk>;
93 hsspi_pll: hsspi-pll {
94 compatible = "fixed-clock";
96 clock-frequency = <200000000>;
101 compatible = "arm,psci-0.2";
106 compatible = "simple-bus";
107 #address-cells = <1>;
109 ranges = <0 0x81000000 0x8000>;
111 gic: interrupt-controller@1000 {
112 compatible = "arm,cortex-a7-gic";
113 #interrupt-cells = <3>;
114 interrupt-controller;
115 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
116 reg = <0x1000 0x1000>,
124 compatible = "simple-bus";
125 #address-cells = <1>;
127 ranges = <0 0xff800000 0x800000>;
130 #address-cells = <1>;
132 compatible = "brcm,bcm47622-hsspi", "brcm,bcmbca-hsspi-v1.0";
133 reg = <0x1000 0x600>;
134 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
135 clocks = <&hsspi_pll &hsspi_pll>;
136 clock-names = "hsspi", "pll";
141 uart0: serial@12000 {
142 compatible = "arm,pl011", "arm,primecell";
143 reg = <0x12000 0x1000>;
144 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&uart_clk>, <&uart_clk>;
146 clock-names = "uartclk", "apb_pclk";