src/arm/marvell/armada-385-turris-omnia.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Device Tree file for the Turris Omnia
   4  *
   5  * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
   6  * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
   7  *
   8  * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
   9  */
  10
  11 /dts-v1/;
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/input/input.h>
  15 #include <dt-bindings/leds/common.h>
  16 #include "armada-385.dtsi"
  17
  18 / {
  19         model = "Turris Omnia";
  20         compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
  21
  22         chosen {
  23                 stdout-path = &uart0;
  24         };
  25
  26         aliases {
  27                 ethernet0 = &eth0;
  28                 ethernet1 = &eth1;
  29                 ethernet2 = &eth2;
  30         };
  31
  32         memory {
  33                 device_type = "memory";
  34                 reg = <0x00000000 0x40000000>; /* 1024 MB */
  35         };
  36
  37         soc {
  38                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  39                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
  40                           MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
  41                           MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
  42                           MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
  43
  44                 internal-regs {
  45
  46                         /* USB part of the PCIe2/USB 2.0 port */
  47                         usb@58000 {
  48                                 status = "okay";
  49                         };
  50
  51                         sata@a8000 {
  52                                 status = "okay";
  53                         };
  54
  55                         sdhci@d8000 {
  56                                 pinctrl-names = "default";
  57                                 pinctrl-0 = <&sdhci_pins>;
  58                                 status = "okay";
  59
  60                                 bus-width = <8>;
  61                                 no-1-8-v;
  62                                 non-removable;
  63                         };
  64
  65                         usb3@f0000 {
  66                                 status = "okay";
  67                         };
  68
  69                         usb3@f8000 {
  70                                 status = "okay";
  71                         };
  72                 };
  73
  74                 pcie {
  75                         status = "okay";
  76
  77                         pcie@1,0 {
  78                                 /* Port 0, Lane 0 */
  79                                 status = "okay";
  80                                 slot-power-limit-milliwatt = <10000>;
  81                         };
  82
  83                         pcie@2,0 {
  84                                 /* Port 1, Lane 0 */
  85                                 status = "okay";
  86                                 slot-power-limit-milliwatt = <10000>;
  87                         };
  88
  89                         pcie@3,0 {
  90                                 /* Port 2, Lane 0 */
  91                                 status = "okay";
  92                                 slot-power-limit-milliwatt = <10000>;
  93                         };
  94                 };
  95         };
  96
  97         sfp: sfp {
  98                 compatible = "sff,sfp";
  99                 i2c-bus = <&sfp_i2c>;
 100                 tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>;
 101                 tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>;
 102                 rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>;
 103                 los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>;
 104                 mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>;
 105                 maximum-power-milliwatt = <3000>;
 106
 107                 /*
 108                  * For now this has to be enabled at boot time by U-Boot when
 109                  * a SFP module is present. Read more in the comment in the
 110                  * eth2 node below.
 111                  */
 112                 status = "disabled";
 113         };
 114
 115         sound {
 116                 compatible = "simple-audio-card";
 117                 simple-audio-card,name = "SPDIF";
 118                 simple-audio-card,format = "i2s";
 119
 120                 simple-audio-card,cpu {
 121                         sound-dai = <&audio_controller 1>;
 122                 };
 123
 124                 simple-audio-card,codec {
 125                         sound-dai = <&spdif_out>;
 126                 };
 127         };
 128
 129         spdif_out: spdif-out {
 130                 #sound-dai-cells = <0>;
 131                 compatible = "linux,spdif-dit";
 132         };
 133 };
 134
 135 &audio_controller {
 136         /* Pin header U16, GPIO51 in SPDIFO mode */
 137         pinctrl-0 = <&spdif_pins>;
 138         pinctrl-names = "default";
 139         spdif-mode;
 140         status = "okay";
 141 };
 142
 143 &bm {
 144         status = "okay";
 145 };
 146
 147 &bm_bppi {
 148         status = "okay";
 149 };
 150
 151 /* Connected to 88E6176 switch, port 6 */
 152 &eth0 {
 153         pinctrl-names = "default";
 154         pinctrl-0 = <&ge0_rgmii_pins>;
 155         status = "okay";
 156         phy-mode = "rgmii";
 157         buffer-manager = <&bm>;
 158         bm,pool-long = <0>;
 159         bm,pool-short = <3>;
 160
 161         fixed-link {
 162                 speed = <1000>;
 163                 full-duplex;
 164         };
 165 };
 166
 167 /* Connected to 88E6176 switch, port 5 */
 168 &eth1 {
 169         pinctrl-names = "default";
 170         pinctrl-0 = <&ge1_rgmii_pins>;
 171         status = "okay";
 172         phy-mode = "rgmii";
 173         buffer-manager = <&bm>;
 174         bm,pool-long = <1>;
 175         bm,pool-short = <3>;
 176
 177         fixed-link {
 178                 speed = <1000>;
 179                 full-duplex;
 180         };
 181 };
 182
 183 /* WAN port */
 184 &eth2 {
 185         /*
 186          * eth2 is connected via a multiplexor to both the SFP cage and to
 187          * ethernet-phy@1. The multiplexor switches the signal to SFP cage when
 188          * a SFP module is present, as determined by the mode-def0 GPIO.
 189          *
 190          * Until kernel supports this configuration properly, in case SFP module
 191          * is present, U-Boot has to enable the sfp node above, remove phy
 192          * handle and add managed = "in-band-status" property.
 193          */
 194         status = "okay";
 195         phy-mode = "sgmii";
 196         phy-handle = <&phy1>;
 197         phys = <&comphy5 2>;
 198         sfp = <&sfp>;
 199         buffer-manager = <&bm>;
 200         bm,pool-long = <2>;
 201         bm,pool-short = <3>;
 202         label = "wan";
 203 };
 204
 205 &i2c0 {
 206         pinctrl-names = "default";
 207         pinctrl-0 = <&i2c0_pins>;
 208         status = "okay";
 209
 210         i2cmux@70 {
 211                 compatible = "nxp,pca9547";
 212                 #address-cells = <1>;
 213                 #size-cells = <0>;
 214                 reg = <0x70>;
 215
 216                 i2c@0 {
 217                         #address-cells = <1>;
 218                         #size-cells = <0>;
 219                         reg = <0>;
 220
 221                         /* STM32F0 command interface at address 0x2a */
 222
 223                         led-controller@2b {
 224                                 compatible = "cznic,turris-omnia-leds";
 225                                 reg = <0x2b>;
 226                                 #address-cells = <1>;
 227                                 #size-cells = <0>;
 228                                 status = "okay";
 229
 230                                 /*
 231                                  * LEDs are controlled by MCU (STM32F0) at
 232                                  * address 0x2b.
 233                                  *
 234                                  * LED functions are not stable yet:
 235                                  * - there are 3 LEDs connected via MCU to PCIe
 236                                  *   ports. One of these ports supports mSATA.
 237                                  *   There is no mSATA nor PCIe function.
 238                                  *   For now we use LED_FUNCTION_WLAN, since
 239                                  *   in most cases users have wifi cards in
 240                                  *   these slots
 241                                  * - there are 2 LEDs dedicated for user: A and
 242                                  *   B. Again there is no such function defined.
 243                                  *   For now we use LED_FUNCTION_INDICATOR
 244                                  */
 245
 246                                 multi-led@0 {
 247                                         reg = <0x0>;
 248                                         color = <LED_COLOR_ID_RGB>;
 249                                         function = LED_FUNCTION_INDICATOR;
 250                                         function-enumerator = <2>;
 251                                 };
 252
 253                                 multi-led@1 {
 254                                         reg = <0x1>;
 255                                         color = <LED_COLOR_ID_RGB>;
 256                                         function = LED_FUNCTION_INDICATOR;
 257                                         function-enumerator = <1>;
 258                                 };
 259
 260                                 multi-led@2 {
 261                                         reg = <0x2>;
 262                                         color = <LED_COLOR_ID_RGB>;
 263                                         function = LED_FUNCTION_WLAN;
 264                                         function-enumerator = <3>;
 265                                 };
 266
 267                                 multi-led@3 {
 268                                         reg = <0x3>;
 269                                         color = <LED_COLOR_ID_RGB>;
 270                                         function = LED_FUNCTION_WLAN;
 271                                         function-enumerator = <2>;
 272                                 };
 273
 274                                 multi-led@4 {
 275                                         reg = <0x4>;
 276                                         color = <LED_COLOR_ID_RGB>;
 277                                         function = LED_FUNCTION_WLAN;
 278                                         function-enumerator = <1>;
 279                                 };
 280
 281                                 multi-led@5 {
 282                                         reg = <0x5>;
 283                                         color = <LED_COLOR_ID_RGB>;
 284                                         function = LED_FUNCTION_WAN;
 285                                 };
 286
 287                                 multi-led@6 {
 288                                         reg = <0x6>;
 289                                         color = <LED_COLOR_ID_RGB>;
 290                                         function = LED_FUNCTION_LAN;
 291                                         function-enumerator = <4>;
 292                                 };
 293
 294                                 multi-led@7 {
 295                                         reg = <0x7>;
 296                                         color = <LED_COLOR_ID_RGB>;
 297                                         function = LED_FUNCTION_LAN;
 298                                         function-enumerator = <3>;
 299                                 };
 300
 301                                 multi-led@8 {
 302                                         reg = <0x8>;
 303                                         color = <LED_COLOR_ID_RGB>;
 304                                         function = LED_FUNCTION_LAN;
 305                                         function-enumerator = <2>;
 306                                 };
 307
 308                                 multi-led@9 {
 309                                         reg = <0x9>;
 310                                         color = <LED_COLOR_ID_RGB>;
 311                                         function = LED_FUNCTION_LAN;
 312                                         function-enumerator = <1>;
 313                                 };
 314
 315                                 multi-led@a {
 316                                         reg = <0xa>;
 317                                         color = <LED_COLOR_ID_RGB>;
 318                                         function = LED_FUNCTION_LAN;
 319                                         function-enumerator = <0>;
 320                                 };
 321
 322                                 multi-led@b {
 323                                         reg = <0xb>;
 324                                         color = <LED_COLOR_ID_RGB>;
 325                                         function = LED_FUNCTION_POWER;
 326                                 };
 327                         };
 328
 329                         eeprom@54 {
 330                                 compatible = "atmel,24c64";
 331                                 reg = <0x54>;
 332
 333                                 /* The EEPROM contains data for bootloader.
 334                                  * Contents:
 335                                  *      struct omnia_eeprom {
 336                                  *              u32 magic; (=0x0341a034 in LE)
 337                                  *              u32 ramsize; (in GiB)
 338                                  *              char regdomain[4];
 339                                  *              u32 crc32;
 340                                  *      };
 341                                  */
 342                         };
 343                 };
 344
 345                 i2c@1 {
 346                         #address-cells = <1>;
 347                         #size-cells = <0>;
 348                         reg = <1>;
 349
 350                         /* routed to PCIe0/mSATA connector (CN7A) */
 351                 };
 352
 353                 i2c@2 {
 354                         #address-cells = <1>;
 355                         #size-cells = <0>;
 356                         reg = <2>;
 357
 358                         /* routed to PCIe1/USB2 connector (CN61A) */
 359                 };
 360
 361                 i2c@3 {
 362                         #address-cells = <1>;
 363                         #size-cells = <0>;
 364                         reg = <3>;
 365
 366                         /* routed to PCIe2 connector (CN62A) */
 367                 };
 368
 369                 sfp_i2c: i2c@4 {
 370                         #address-cells = <1>;
 371                         #size-cells = <0>;
 372                         reg = <4>;
 373
 374                         /* routed to SFP+ */
 375                 };
 376
 377                 i2c@5 {
 378                         #address-cells = <1>;
 379                         #size-cells = <0>;
 380                         reg = <5>;
 381
 382                         /* ATSHA204A-MAHDA-T crypto module */
 383                         crypto@64 {
 384                                 compatible = "atmel,atsha204a";
 385                                 reg = <0x64>;
 386                         };
 387                 };
 388
 389                 i2c@6 {
 390                         #address-cells = <1>;
 391                         #size-cells = <0>;
 392                         reg = <6>;
 393
 394                         /* exposed on pin header */
 395                 };
 396
 397                 i2c@7 {
 398                         #address-cells = <1>;
 399                         #size-cells = <0>;
 400                         reg = <7>;
 401
 402                         pcawan: gpio@71 {
 403                                 /*
 404                                  * GPIO expander for SFP+ signals and
 405                                  * and phy irq
 406                                  */
 407                                 compatible = "nxp,pca9538";
 408                                 reg = <0x71>;
 409
 410                                 pinctrl-names = "default";
 411                                 pinctrl-0 = <&pcawan_pins>;
 412
 413                                 interrupt-parent = <&gpio1>;
 414                                 interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
 415
 416                                 gpio-controller;
 417                                 #gpio-cells = <2>;
 418                         };
 419                 };
 420         };
 421 };
 422
 423 &mdio {
 424         pinctrl-names = "default";
 425         pinctrl-0 = <&mdio_pins>;
 426         status = "okay";
 427
 428         phy1: ethernet-phy@1 {
 429                 compatible = "ethernet-phy-ieee802.3-c22";
 430                 reg = <1>;
 431                 marvell,reg-init = <3 18 0 0x4985>,
 432                                    <3 16 0xfff0 0x0001>;
 433
 434                 /* irq is connected to &pcawan pin 7 */
 435         };
 436
 437         /* Switch MV88E6176 at address 0x10 */
 438         ethernet-switch@10 {
 439                 pinctrl-names = "default";
 440                 pinctrl-0 = <&swint_pins>;
 441                 compatible = "marvell,mv88e6085";
 442
 443                 dsa,member = <0 0>;
 444                 reg = <0x10>;
 445
 446                 interrupt-parent = <&gpio1>;
 447                 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
 448
 449                 ethernet-ports {
 450                         #address-cells = <1>;
 451                         #size-cells = <0>;
 452
 453                         ethernet-port@0 {
 454                                 reg = <0>;
 455                                 label = "lan0";
 456                         };
 457
 458                         ethernet-port@1 {
 459                                 reg = <1>;
 460                                 label = "lan1";
 461                         };
 462
 463                         ethernet-port@2 {
 464                                 reg = <2>;
 465                                 label = "lan2";
 466                         };
 467
 468                         ethernet-port@3 {
 469                                 reg = <3>;
 470                                 label = "lan3";
 471                         };
 472
 473                         ethernet-port@4 {
 474                                 reg = <4>;
 475                                 label = "lan4";
 476                         };
 477
 478                         ethernet-port@5 {
 479                                 reg = <5>;
 480                                 ethernet = <&eth1>;
 481                                 phy-mode = "rgmii-id";
 482
 483                                 fixed-link {
 484                                         speed = <1000>;
 485                                         full-duplex;
 486                                 };
 487                         };
 488
 489                         ethernet-port@6 {
 490                                 reg = <6>;
 491                                 ethernet = <&eth0>;
 492                                 phy-mode = "rgmii-id";
 493
 494                                 fixed-link {
 495                                         speed = <1000>;
 496                                         full-duplex;
 497                                 };
 498                         };
 499                 };
 500         };
 501 };
 502
 503 &pinctrl {
 504         pcawan_pins: pcawan-pins {
 505                 marvell,pins = "mpp46";
 506                 marvell,function = "gpio";
 507         };
 508
 509         swint_pins: swint-pins {
 510                 marvell,pins = "mpp45";
 511                 marvell,function = "gpio";
 512         };
 513
 514         spi0cs0_pins: spi0cs0-pins {
 515                 marvell,pins = "mpp25";
 516                 marvell,function = "spi0";
 517         };
 518
 519         spi0cs2_pins: spi0cs2-pins {
 520                 marvell,pins = "mpp26";
 521                 marvell,function = "spi0";
 522         };
 523 };
 524
 525 &spi0 {
 526         pinctrl-names = "default";
 527         pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
 528         status = "okay";
 529
 530         flash@0 {
 531                 compatible = "spansion,s25fl164k", "jedec,spi-nor";
 532                 #address-cells = <1>;
 533                 #size-cells = <1>;
 534                 reg = <0>;
 535                 spi-max-frequency = <40000000>;
 536
 537                 partitions {
 538                         compatible = "fixed-partitions";
 539                         #address-cells = <1>;
 540                         #size-cells = <1>;
 541
 542                         partition@0 {
 543                                 reg = <0x0 0x00100000>;
 544                                 label = "U-Boot";
 545                         };
 546
 547                         partition@100000 {
 548                                 reg = <0x00100000 0x00700000>;
 549                                 label = "Rescue system";
 550                         };
 551                 };
 552         };
 553
 554         /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */
 555 };
 556
 557 &uart0 {
 558         /* Pin header CN10 */
 559         pinctrl-names = "default";
 560         pinctrl-0 = <&uart0_pins>;
 561         status = "okay";
 562 };
 563
 564 &uart1 {
 565         /* Pin header CN11 */
 566         pinctrl-names = "default";
 567         pinctrl-0 = <&uart1_pins>;
 568         status = "okay";
 569 };