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Squashed 'dts/upstream/' content from commit aaba2d45dc2a
[thirdparty/u-boot.git] / src / arm / nxp / imx / imx6q.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright 2013 Freescale Semiconductor, Inc.
4
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
7 #include "imx6qdl.dtsi"
8
9 / {
10 aliases {
11 ipu1 = &ipu2;
12 spi4 = &ecspi5;
13 };
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu0: cpu@0 {
20 compatible = "arm,cortex-a9";
21 device_type = "cpu";
22 reg = <0>;
23 next-level-cache = <&L2>;
24 operating-points = <
25 /* kHz uV */
26 1200000 1275000
27 996000 1250000
28 852000 1250000
29 792000 1175000
30 396000 975000
31 >;
32 fsl,soc-operating-points = <
33 /* ARM kHz SOC-PU uV */
34 1200000 1275000
35 996000 1250000
36 852000 1250000
37 792000 1175000
38 396000 1175000
39 >;
40 clock-latency = <61036>; /* two CLK32 periods */
41 #cooling-cells = <2>;
42 clocks = <&clks IMX6QDL_CLK_ARM>,
43 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
44 <&clks IMX6QDL_CLK_STEP>,
45 <&clks IMX6QDL_CLK_PLL1_SW>,
46 <&clks IMX6QDL_CLK_PLL1_SYS>;
47 clock-names = "arm", "pll2_pfd2_396m", "step",
48 "pll1_sw", "pll1_sys";
49 arm-supply = <&reg_arm>;
50 pu-supply = <&reg_pu>;
51 soc-supply = <&reg_soc>;
52 nvmem-cells = <&cpu_speed_grade>;
53 nvmem-cell-names = "speed_grade";
54 };
55
56 cpu1: cpu@1 {
57 compatible = "arm,cortex-a9";
58 device_type = "cpu";
59 reg = <1>;
60 next-level-cache = <&L2>;
61 operating-points = <
62 /* kHz uV */
63 1200000 1275000
64 996000 1250000
65 852000 1250000
66 792000 1175000
67 396000 975000
68 >;
69 fsl,soc-operating-points = <
70 /* ARM kHz SOC-PU uV */
71 1200000 1275000
72 996000 1250000
73 852000 1250000
74 792000 1175000
75 396000 1175000
76 >;
77 clock-latency = <61036>; /* two CLK32 periods */
78 #cooling-cells = <2>;
79 clocks = <&clks IMX6QDL_CLK_ARM>,
80 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
81 <&clks IMX6QDL_CLK_STEP>,
82 <&clks IMX6QDL_CLK_PLL1_SW>,
83 <&clks IMX6QDL_CLK_PLL1_SYS>;
84 clock-names = "arm", "pll2_pfd2_396m", "step",
85 "pll1_sw", "pll1_sys";
86 arm-supply = <&reg_arm>;
87 pu-supply = <&reg_pu>;
88 soc-supply = <&reg_soc>;
89 };
90
91 cpu2: cpu@2 {
92 compatible = "arm,cortex-a9";
93 device_type = "cpu";
94 reg = <2>;
95 next-level-cache = <&L2>;
96 operating-points = <
97 /* kHz uV */
98 1200000 1275000
99 996000 1250000
100 852000 1250000
101 792000 1175000
102 396000 975000
103 >;
104 fsl,soc-operating-points = <
105 /* ARM kHz SOC-PU uV */
106 1200000 1275000
107 996000 1250000
108 852000 1250000
109 792000 1175000
110 396000 1175000
111 >;
112 clock-latency = <61036>; /* two CLK32 periods */
113 #cooling-cells = <2>;
114 clocks = <&clks IMX6QDL_CLK_ARM>,
115 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
116 <&clks IMX6QDL_CLK_STEP>,
117 <&clks IMX6QDL_CLK_PLL1_SW>,
118 <&clks IMX6QDL_CLK_PLL1_SYS>;
119 clock-names = "arm", "pll2_pfd2_396m", "step",
120 "pll1_sw", "pll1_sys";
121 arm-supply = <&reg_arm>;
122 pu-supply = <&reg_pu>;
123 soc-supply = <&reg_soc>;
124 };
125
126 cpu3: cpu@3 {
127 compatible = "arm,cortex-a9";
128 device_type = "cpu";
129 reg = <3>;
130 next-level-cache = <&L2>;
131 operating-points = <
132 /* kHz uV */
133 1200000 1275000
134 996000 1250000
135 852000 1250000
136 792000 1175000
137 396000 975000
138 >;
139 fsl,soc-operating-points = <
140 /* ARM kHz SOC-PU uV */
141 1200000 1275000
142 996000 1250000
143 852000 1250000
144 792000 1175000
145 396000 1175000
146 >;
147 clock-latency = <61036>; /* two CLK32 periods */
148 #cooling-cells = <2>;
149 clocks = <&clks IMX6QDL_CLK_ARM>,
150 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
151 <&clks IMX6QDL_CLK_STEP>,
152 <&clks IMX6QDL_CLK_PLL1_SW>,
153 <&clks IMX6QDL_CLK_PLL1_SYS>;
154 clock-names = "arm", "pll2_pfd2_396m", "step",
155 "pll1_sw", "pll1_sys";
156 arm-supply = <&reg_arm>;
157 pu-supply = <&reg_pu>;
158 soc-supply = <&reg_soc>;
159 };
160 };
161
162 soc: soc {
163 ocram: sram@900000 {
164 compatible = "mmio-sram";
165 reg = <0x00900000 0x40000>;
166 ranges = <0 0x00900000 0x40000>;
167 #address-cells = <1>;
168 #size-cells = <1>;
169 clocks = <&clks IMX6QDL_CLK_OCRAM>;
170 };
171
172 aips1: bus@2000000 { /* AIPS1 */
173 spba-bus@2000000 {
174 ecspi5: spi@2018000 {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
178 reg = <0x02018000 0x4000>;
179 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&clks IMX6Q_CLK_ECSPI5>,
181 <&clks IMX6Q_CLK_ECSPI5>;
182 clock-names = "ipg", "per";
183 dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
184 dma-names = "rx", "tx";
185 status = "disabled";
186 };
187 };
188 };
189
190 sata: sata@2200000 {
191 compatible = "fsl,imx6q-ahci";
192 reg = <0x02200000 0x4000>;
193 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&clks IMX6QDL_CLK_SATA>,
195 <&clks IMX6QDL_CLK_SATA_REF_100M>,
196 <&clks IMX6QDL_CLK_AHB>;
197 clock-names = "sata", "sata_ref", "ahb";
198 status = "disabled";
199 };
200
201 gpu_vg: gpu@2204000 {
202 compatible = "vivante,gc";
203 reg = <0x02204000 0x4000>;
204 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
206 <&clks IMX6QDL_CLK_GPU2D_CORE>;
207 clock-names = "bus", "core";
208 power-domains = <&pd_pu>;
209 #cooling-cells = <2>;
210 };
211
212 ipu2: ipu@2800000 {
213 #address-cells = <1>;
214 #size-cells = <0>;
215 compatible = "fsl,imx6q-ipu";
216 reg = <0x02800000 0x400000>;
217 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
218 <0 7 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&clks IMX6QDL_CLK_IPU2>,
220 <&clks IMX6QDL_CLK_IPU2_DI0>,
221 <&clks IMX6QDL_CLK_IPU2_DI1>;
222 clock-names = "bus", "di0", "di1";
223 resets = <&src 4>;
224
225 ipu2_csi0: port@0 {
226 reg = <0>;
227
228 ipu2_csi0_from_mipi_vc2: endpoint {
229 remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
230 };
231 };
232
233 ipu2_csi1: port@1 {
234 reg = <1>;
235
236 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
237 remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
238 };
239 };
240
241 ipu2_di0: port@2 {
242 #address-cells = <1>;
243 #size-cells = <0>;
244 reg = <2>;
245
246 ipu2_di0_disp0: endpoint@0 {
247 reg = <0>;
248 };
249
250 ipu2_di0_hdmi: endpoint@1 {
251 reg = <1>;
252 remote-endpoint = <&hdmi_mux_2>;
253 };
254
255 ipu2_di0_mipi: endpoint@2 {
256 reg = <2>;
257 remote-endpoint = <&mipi_mux_2>;
258 };
259
260 ipu2_di0_lvds0: endpoint@3 {
261 reg = <3>;
262 remote-endpoint = <&lvds0_mux_2>;
263 };
264
265 ipu2_di0_lvds1: endpoint@4 {
266 reg = <4>;
267 remote-endpoint = <&lvds1_mux_2>;
268 };
269 };
270
271 ipu2_di1: port@3 {
272 #address-cells = <1>;
273 #size-cells = <0>;
274 reg = <3>;
275
276 ipu2_di1_hdmi: endpoint@1 {
277 reg = <1>;
278 remote-endpoint = <&hdmi_mux_3>;
279 };
280
281 ipu2_di1_mipi: endpoint@2 {
282 reg = <2>;
283 remote-endpoint = <&mipi_mux_3>;
284 };
285
286 ipu2_di1_lvds0: endpoint@3 {
287 reg = <3>;
288 remote-endpoint = <&lvds0_mux_3>;
289 };
290
291 ipu2_di1_lvds1: endpoint@4 {
292 reg = <4>;
293 remote-endpoint = <&lvds1_mux_3>;
294 };
295 };
296 };
297 };
298
299 capture-subsystem {
300 compatible = "fsl,imx-capture-subsystem";
301 ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
302 };
303
304 display-subsystem {
305 compatible = "fsl,imx-display-subsystem";
306 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
307 };
308 };
309
310 &gpio1 {
311 gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
312 <&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,
313 <&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,
314 <&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,
315 <&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
316 <&iomuxc 22 116 10>;
317 };
318
319 &gpio2 {
320 gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
321 <&iomuxc 31 44 1>;
322 };
323
324 &gpio3 {
325 gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
326 };
327
328 &gpio4 {
329 gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
330 };
331
332 &gpio5 {
333 gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
334 <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
335 };
336
337 &gpio6 {
338 gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
339 <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,
340 <&iomuxc 31 86 1>;
341 };
342
343 &gpio7 {
344 gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
345 };
346
347 &gpr {
348 ipu1_csi0_mux {
349 compatible = "video-mux";
350 mux-controls = <&mux 0>;
351 #address-cells = <1>;
352 #size-cells = <0>;
353
354 port@0 {
355 reg = <0>;
356
357 ipu1_csi0_mux_from_mipi_vc0: endpoint {
358 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
359 };
360 };
361
362 port@1 {
363 reg = <1>;
364
365 ipu1_csi0_mux_from_parallel_sensor: endpoint {
366 };
367 };
368
369 port@2 {
370 reg = <2>;
371
372 ipu1_csi0_mux_to_ipu1_csi0: endpoint {
373 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
374 };
375 };
376 };
377
378 ipu2_csi1_mux {
379 compatible = "video-mux";
380 mux-controls = <&mux 1>;
381 #address-cells = <1>;
382 #size-cells = <0>;
383
384 port@0 {
385 reg = <0>;
386
387 ipu2_csi1_mux_from_mipi_vc3: endpoint {
388 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
389 };
390 };
391
392 port@1 {
393 reg = <1>;
394
395 ipu2_csi1_mux_from_parallel_sensor: endpoint {
396 };
397 };
398
399 port@2 {
400 reg = <2>;
401
402 ipu2_csi1_mux_to_ipu2_csi1: endpoint {
403 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
404 };
405 };
406 };
407 };
408
409 &hdmi {
410 compatible = "fsl,imx6q-hdmi";
411
412 ports {
413 port@2 {
414 reg = <2>;
415
416 hdmi_mux_2: endpoint {
417 remote-endpoint = <&ipu2_di0_hdmi>;
418 };
419 };
420
421 port@3 {
422 reg = <3>;
423
424 hdmi_mux_3: endpoint {
425 remote-endpoint = <&ipu2_di1_hdmi>;
426 };
427 };
428 };
429 };
430
431 &iomuxc {
432 compatible = "fsl,imx6q-iomuxc";
433 };
434
435 &ipu1_csi1 {
436 ipu1_csi1_from_mipi_vc1: endpoint {
437 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
438 };
439 };
440
441 &ldb {
442 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
443 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
444 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
445 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
446 clock-names = "di0_pll", "di1_pll",
447 "di0_sel", "di1_sel", "di2_sel", "di3_sel",
448 "di0", "di1";
449
450 lvds-channel@0 {
451 port@2 {
452 reg = <2>;
453
454 lvds0_mux_2: endpoint {
455 remote-endpoint = <&ipu2_di0_lvds0>;
456 };
457 };
458
459 port@3 {
460 reg = <3>;
461
462 lvds0_mux_3: endpoint {
463 remote-endpoint = <&ipu2_di1_lvds0>;
464 };
465 };
466 };
467
468 lvds-channel@1 {
469 port@2 {
470 reg = <2>;
471
472 lvds1_mux_2: endpoint {
473 remote-endpoint = <&ipu2_di0_lvds1>;
474 };
475 };
476
477 port@3 {
478 reg = <3>;
479
480 lvds1_mux_3: endpoint {
481 remote-endpoint = <&ipu2_di1_lvds1>;
482 };
483 };
484 };
485 };
486
487 &mipi_csi {
488 port@1 {
489 reg = <1>;
490
491 mipi_vc0_to_ipu1_csi0_mux: endpoint {
492 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
493 };
494 };
495
496 port@2 {
497 reg = <2>;
498
499 mipi_vc1_to_ipu1_csi1: endpoint {
500 remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
501 };
502 };
503
504 port@3 {
505 reg = <3>;
506
507 mipi_vc2_to_ipu2_csi0: endpoint {
508 remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
509 };
510 };
511
512 port@4 {
513 reg = <4>;
514
515 mipi_vc3_to_ipu2_csi1_mux: endpoint {
516 remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
517 };
518 };
519 };
520
521 &mipi_dsi {
522 ports {
523 port@2 {
524 reg = <2>;
525
526 mipi_mux_2: endpoint {
527 remote-endpoint = <&ipu2_di0_mipi>;
528 };
529 };
530
531 port@3 {
532 reg = <3>;
533
534 mipi_mux_3: endpoint {
535 remote-endpoint = <&ipu2_di1_mipi>;
536 };
537 };
538 };
539 };
540
541 &mux {
542 mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
543 <0x04 0x00100000>, /* MIPI_IPU2_MUX */
544 <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
545 <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
546 <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
547 <0x28 0x00000003>, /* DCIC1_MUX_CTL */
548 <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
549 };
550
551 &vpu {
552 compatible = "fsl,imx6q-vpu", "cnm,coda960";
553 };
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