src/arm/nxp/imx/imx6qdl-gw5904.dtsi

   1 /*
   2  * Copyright 2017 Gateworks Corporation
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/gpio/gpio.h>
  49 #include <dt-bindings/input/linux-event-codes.h>
  50 #include <dt-bindings/interrupt-controller/irq.h>
  51
  52 / {
  53         /* these are used by bootloader for disabling nodes */
  54         aliases {
  55                 ethernet0 = &fec;
  56                 ethernet1 = &lan1;
  57                 ethernet2 = &lan2;
  58                 ethernet3 = &lan3;
  59                 ethernet4 = &lan4;
  60                 led0 = &led0;
  61                 led1 = &led1;
  62                 led2 = &led2;
  63                 usb0 = &usbh1;
  64                 usb1 = &usbotg;
  65         };
  66
  67         chosen {
  68                 stdout-path = &uart2;
  69         };
  70
  71         backlight {
  72                 compatible = "pwm-backlight";
  73                 pwms = <&pwm4 0 5000000>;
  74                 brightness-levels = <0 4 8 16 32 64 128 255>;
  75                 default-brightness-level = <7>;
  76         };
  77
  78         gpio-keys {
  79                 compatible = "gpio-keys";
  80
  81                 user-pb {
  82                         label = "user_pb";
  83                         gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  84                         linux,code = <BTN_0>;
  85                 };
  86
  87                 user-pb1x {
  88                         label = "user_pb1x";
  89                         linux,code = <BTN_1>;
  90                         interrupt-parent = <&gsc>;
  91                         interrupts = <0>;
  92                 };
  93
  94                 key-erased {
  95                         label = "key-erased";
  96                         linux,code = <BTN_2>;
  97                         interrupt-parent = <&gsc>;
  98                         interrupts = <1>;
  99                 };
 100
 101                 eeprom-wp {
 102                         label = "eeprom_wp";
 103                         linux,code = <BTN_3>;
 104                         interrupt-parent = <&gsc>;
 105                         interrupts = <2>;
 106                 };
 107
 108                 tamper {
 109                         label = "tamper";
 110                         linux,code = <BTN_4>;
 111                         interrupt-parent = <&gsc>;
 112                         interrupts = <5>;
 113                 };
 114
 115                 switch-hold {
 116                         label = "switch_hold";
 117                         linux,code = <BTN_5>;
 118                         interrupt-parent = <&gsc>;
 119                         interrupts = <7>;
 120                 };
 121         };
 122
 123         leds {
 124                 compatible = "gpio-leds";
 125                 pinctrl-names = "default";
 126                 pinctrl-0 = <&pinctrl_gpio_leds>;
 127
 128                 led0: led-user1 {
 129                         label = "user1";
 130                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
 131                         default-state = "on";
 132                         linux,default-trigger = "heartbeat";
 133                 };
 134
 135                 led1: led-user2 {
 136                         label = "user2";
 137                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
 138                         default-state = "off";
 139                 };
 140
 141                 led2: led-user3 {
 142                         label = "user3";
 143                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
 144                         default-state = "off";
 145                 };
 146         };
 147
 148         memory@10000000 {
 149                 device_type = "memory";
 150                 reg = <0x10000000 0x40000000>;
 151         };
 152
 153         pps {
 154                 compatible = "pps-gpio";
 155                 pinctrl-names = "default";
 156                 pinctrl-0 = <&pinctrl_pps>;
 157                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 158         };
 159
 160         reg_1p0v: regulator-1p0v {
 161                 compatible = "regulator-fixed";
 162                 regulator-name = "1P0V";
 163                 regulator-min-microvolt = <1000000>;
 164                 regulator-max-microvolt = <1000000>;
 165                 regulator-always-on;
 166         };
 167
 168         reg_3p3v: regulator-3p3v {
 169                 compatible = "regulator-fixed";
 170                 regulator-name = "3P3V";
 171                 regulator-min-microvolt = <3300000>;
 172                 regulator-max-microvolt = <3300000>;
 173                 regulator-always-on;
 174         };
 175
 176         reg_usb_h1_vbus: regulator-usb-h1-vbus {
 177                 compatible = "regulator-fixed";
 178                 regulator-name = "usb_h1_vbus";
 179                 regulator-min-microvolt = <5000000>;
 180                 regulator-max-microvolt = <5000000>;
 181                 regulator-always-on;
 182         };
 183
 184         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 185                 compatible = "regulator-fixed";
 186                 regulator-name = "usb_otg_vbus";
 187                 regulator-min-microvolt = <5000000>;
 188                 regulator-max-microvolt = <5000000>;
 189                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 190                 enable-active-high;
 191         };
 192 };
 193
 194 &clks {
 195         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 196                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 197         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 198                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 199 };
 200
 201 &fec {
 202         pinctrl-names = "default";
 203         pinctrl-0 = <&pinctrl_enet>;
 204         phy-mode = "rgmii-id";
 205         status = "okay";
 206
 207         fixed-link {
 208                 speed = <1000>;
 209                 full-duplex;
 210         };
 211
 212         mdio {
 213                 #address-cells = <1>;
 214                 #size-cells = <0>;
 215
 216                 switch@0 {
 217                         compatible = "marvell,mv88e6085";
 218                         reg = <0>;
 219
 220                         mdio {
 221                                 #address-cells = <1>;
 222                                 #size-cells = <0>;
 223
 224                                 sw_phy0: ethernet-phy@0 {
 225                                         reg = <0x0>;
 226                                 };
 227
 228                                 sw_phy1: ethernet-phy@1 {
 229                                         reg = <0x1>;
 230                                 };
 231
 232                                 sw_phy2: ethernet-phy@2 {
 233                                         reg = <0x2>;
 234                                 };
 235
 236                                 sw_phy3: ethernet-phy@3 {
 237                                         reg = <0x3>;
 238                                 };
 239                         };
 240
 241                         ports {
 242                                 #address-cells = <1>;
 243                                 #size-cells = <0>;
 244
 245                                 lan4: port@0 {
 246                                         reg = <0>;
 247                                         label = "lan4";
 248                                         phy-handle = <&sw_phy0>;
 249                                         phy-mode = "internal";
 250                                         local-mac-address = [00 00 00 00 00 00];
 251                                 };
 252
 253                                 lan3: port@1 {
 254                                         reg = <1>;
 255                                         label = "lan3";
 256                                         phy-handle = <&sw_phy1>;
 257                                         phy-mode = "internal";
 258                                         local-mac-address = [00 00 00 00 00 00];
 259                                 };
 260
 261                                 lan2: port@2 {
 262                                         reg = <2>;
 263                                         label = "lan2";
 264                                         phy-handle = <&sw_phy2>;
 265                                         phy-mode = "internal";
 266                                         local-mac-address = [00 00 00 00 00 00];
 267                                 };
 268
 269                                 lan1: port@3 {
 270                                         reg = <3>;
 271                                         label = "lan1";
 272                                         phy-handle = <&sw_phy3>;
 273                                         phy-mode = "internal";
 274                                         local-mac-address = [00 00 00 00 00 00];
 275                                 };
 276
 277                                 port@5 {
 278                                         reg = <5>;
 279                                         ethernet = <&fec>;
 280                                         phy-mode = "rgmii-id";
 281
 282                                         fixed-link {
 283                                                 speed = <1000>;
 284                                                 full-duplex;
 285                                         };
 286                                 };
 287                         };
 288                 };
 289         };
 290 };
 291
 292 &i2c1 {
 293         clock-frequency = <100000>;
 294         pinctrl-names = "default";
 295         pinctrl-0 = <&pinctrl_i2c1>;
 296         status = "okay";
 297
 298         gsc: gsc@20 {
 299                 compatible = "gw,gsc";
 300                 reg = <0x20>;
 301                 interrupt-parent = <&gpio1>;
 302                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 303                 interrupt-controller;
 304                 #interrupt-cells = <1>;
 305                 #size-cells = <0>;
 306
 307                 adc {
 308                         compatible = "gw,gsc-adc";
 309                         #address-cells = <1>;
 310                         #size-cells = <0>;
 311
 312                         channel@0 {
 313                                 gw,mode = <0>;
 314                                 reg = <0x00>;
 315                                 label = "temp";
 316                         };
 317
 318                         channel@2 {
 319                                 gw,mode = <1>;
 320                                 reg = <0x02>;
 321                                 label = "vdd_vin";
 322                         };
 323
 324                         channel@5 {
 325                                 gw,mode = <1>;
 326                                 reg = <0x05>;
 327                                 label = "vdd_3p3";
 328                         };
 329
 330                         channel@8 {
 331                                 gw,mode = <1>;
 332                                 reg = <0x08>;
 333                                 label = "vdd_bat";
 334                         };
 335
 336                         channel@b {
 337                                 gw,mode = <1>;
 338                                 reg = <0x0b>;
 339                                 label = "vdd_5p0";
 340                         };
 341
 342                         channel@e {
 343                                 gw,mode = <1>;
 344                                 reg = <0xe>;
 345                                 label = "vdd_arm";
 346                         };
 347
 348                         channel@11 {
 349                                 gw,mode = <1>;
 350                                 reg = <0x11>;
 351                                 label = "vdd_soc";
 352                         };
 353
 354                         channel@14 {
 355                                 gw,mode = <1>;
 356                                 reg = <0x14>;
 357                                 label = "vdd_3p0";
 358                         };
 359
 360                         channel@17 {
 361                                 gw,mode = <1>;
 362                                 reg = <0x17>;
 363                                 label = "vdd_1p5";
 364                         };
 365
 366                         channel@1d {
 367                                 gw,mode = <1>;
 368                                 reg = <0x1d>;
 369                                 label = "vdd_1p8";
 370                         };
 371
 372                         channel@20 {
 373                                 gw,mode = <1>;
 374                                 reg = <0x20>;
 375                                 label = "vdd_an1";
 376                         };
 377
 378                         channel@23 {
 379                                 gw,mode = <1>;
 380                                 reg = <0x23>;
 381                                 label = "vdd_2p5";
 382                         };
 383                 };
 384         };
 385
 386         gsc_gpio: gpio@23 {
 387                 compatible = "nxp,pca9555";
 388                 reg = <0x23>;
 389                 gpio-controller;
 390                 #gpio-cells = <2>;
 391                 interrupt-parent = <&gsc>;
 392                 interrupts = <4>;
 393         };
 394
 395         eeprom1: eeprom@50 {
 396                 compatible = "atmel,24c02";
 397                 reg = <0x50>;
 398                 pagesize = <16>;
 399         };
 400
 401         eeprom2: eeprom@51 {
 402                 compatible = "atmel,24c02";
 403                 reg = <0x51>;
 404                 pagesize = <16>;
 405         };
 406
 407         eeprom3: eeprom@52 {
 408                 compatible = "atmel,24c02";
 409                 reg = <0x52>;
 410                 pagesize = <16>;
 411         };
 412
 413         eeprom4: eeprom@53 {
 414                 compatible = "atmel,24c02";
 415                 reg = <0x53>;
 416                 pagesize = <16>;
 417         };
 418
 419         dts1672: rtc@68 {
 420                 compatible = "dallas,ds1672";
 421                 reg = <0x68>;
 422         };
 423 };
 424
 425 &i2c2 {
 426         clock-frequency = <100000>;
 427         pinctrl-names = "default";
 428         pinctrl-0 = <&pinctrl_i2c2>;
 429         status = "okay";
 430
 431         magn@1c {
 432                 compatible = "st,lsm9ds1-magn";
 433                 reg = <0x1c>;
 434                 pinctrl-names = "default";
 435                 pinctrl-0 = <&pinctrl_mag>;
 436                 interrupt-parent = <&gpio5>;
 437                 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
 438         };
 439
 440         ltc3676: pmic@3c {
 441                 compatible = "lltc,ltc3676";
 442                 reg = <0x3c>;
 443                 interrupt-parent = <&gpio1>;
 444                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 445
 446                 regulators {
 447                         /* VDD_SOC (1+R1/R2 = 1.635) */
 448                         reg_vdd_soc: sw1 {
 449                                 regulator-name = "vddsoc";
 450                                 regulator-min-microvolt = <674400>;
 451                                 regulator-max-microvolt = <1308000>;
 452                                 lltc,fb-voltage-divider = <127000 200000>;
 453                                 regulator-ramp-delay = <7000>;
 454                                 regulator-boot-on;
 455                                 regulator-always-on;
 456                         };
 457
 458                         /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */
 459                         reg_1p8v: sw2 {
 460                                 regulator-name = "vdd1p8";
 461                                 regulator-min-microvolt = <1033310>;
 462                                 regulator-max-microvolt = <2004000>;
 463                                 lltc,fb-voltage-divider = <301000 200000>;
 464                                 regulator-ramp-delay = <7000>;
 465                                 regulator-boot-on;
 466                                 regulator-always-on;
 467                         };
 468
 469                         /* VDD_ARM (1+R1/R2 = 1.635) */
 470                         reg_vdd_arm: sw3 {
 471                                 regulator-name = "vddarm";
 472                                 regulator-min-microvolt = <674400>;
 473                                 regulator-max-microvolt = <1308000>;
 474                                 lltc,fb-voltage-divider = <127000 200000>;
 475                                 regulator-ramp-delay = <7000>;
 476                                 regulator-boot-on;
 477                                 regulator-always-on;
 478                         };
 479
 480                         /* VDD_DDR (1+R1/R2 = 2.105) */
 481                         reg_vdd_ddr: sw4 {
 482                                 regulator-name = "vddddr";
 483                                 regulator-min-microvolt = <868310>;
 484                                 regulator-max-microvolt = <1684000>;
 485                                 lltc,fb-voltage-divider = <221000 200000>;
 486                                 regulator-ramp-delay = <7000>;
 487                                 regulator-boot-on;
 488                                 regulator-always-on;
 489                         };
 490
 491                         /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
 492                         reg_2p5v: ldo2 {
 493                                 regulator-name = "vdd2p5";
 494                                 regulator-min-microvolt = <2490375>;
 495                                 regulator-max-microvolt = <2490375>;
 496                                 lltc,fb-voltage-divider = <487000 200000>;
 497                                 regulator-boot-on;
 498                                 regulator-always-on;
 499                         };
 500
 501                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 502                         reg_3p0v: ldo4 {
 503                                 regulator-name = "vdd3p0";
 504                                 regulator-min-microvolt = <3023250>;
 505                                 regulator-max-microvolt = <3023250>;
 506                                 lltc,fb-voltage-divider = <634000 200000>;
 507                                 regulator-boot-on;
 508                                 regulator-always-on;
 509                         };
 510                 };
 511         };
 512
 513         crypto@60 {
 514                 compatible = "atmel,atecc508a";
 515                 reg = <0x60>;
 516         };
 517
 518         imu@6a {
 519                 compatible = "st,lsm9ds1-imu";
 520                 reg = <0x6a>;
 521                 st,drdy-int-pin = <1>;
 522                 pinctrl-names = "default";
 523                 pinctrl-0 = <&pinctrl_imu>;
 524                 interrupt-parent = <&gpio4>;
 525                 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
 526         };
 527 };
 528
 529 &i2c3 {
 530         clock-frequency = <100000>;
 531         pinctrl-names = "default";
 532         pinctrl-0 = <&pinctrl_i2c3>;
 533         status = "okay";
 534
 535         egalax_ts: touchscreen@4 {
 536                 compatible = "eeti,egalax_ts";
 537                 reg = <0x04>;
 538                 interrupt-parent = <&gpio1>;
 539                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 540                 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
 541         };
 542 };
 543
 544 &ldb {
 545         status = "okay";
 546
 547         lvds-channel@0 {
 548                 fsl,data-mapping = "spwg";
 549                 fsl,data-width = <18>;
 550                 status = "okay";
 551
 552                 display-timings {
 553                         native-mode = <&timing0>;
 554                         timing0: hsd100pxn1 {
 555                                 clock-frequency = <65000000>;
 556                                 hactive = <1024>;
 557                                 vactive = <768>;
 558                                 hback-porch = <220>;
 559                                 hfront-porch = <40>;
 560                                 vback-porch = <21>;
 561                                 vfront-porch = <7>;
 562                                 hsync-len = <60>;
 563                                 vsync-len = <10>;
 564                         };
 565                 };
 566         };
 567 };
 568
 569 &pcie {
 570         pinctrl-names = "default";
 571         pinctrl-0 = <&pinctrl_pcie>;
 572         reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 573         status = "okay";
 574 };
 575
 576 &pwm2 {
 577         pinctrl-names = "default";
 578         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 579         status = "disabled";
 580 };
 581
 582 &pwm3 {
 583         pinctrl-names = "default";
 584         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 585         status = "disabled";
 586 };
 587
 588 &pwm4 {
 589         #pwm-cells = <2>;
 590         pinctrl-names = "default";
 591         pinctrl-0 = <&pinctrl_pwm4>;
 592         status = "okay";
 593 };
 594
 595 &uart1 {
 596         pinctrl-names = "default";
 597         pinctrl-0 = <&pinctrl_uart1>;
 598         status = "okay";
 599 };
 600
 601 &uart2 {
 602         pinctrl-names = "default";
 603         pinctrl-0 = <&pinctrl_uart2>;
 604         status = "okay";
 605 };
 606
 607 &uart3 {
 608         pinctrl-names = "default";
 609         pinctrl-0 = <&pinctrl_uart3>;
 610         uart-has-rtscts;
 611         status = "okay";
 612 };
 613
 614 &uart4 {
 615         pinctrl-names = "default";
 616         pinctrl-0 = <&pinctrl_uart4>;
 617         uart-has-rtscts;
 618         status = "okay";
 619 };
 620
 621 &uart5 {
 622         pinctrl-names = "default";
 623         pinctrl-0 = <&pinctrl_uart5>;
 624         status = "okay";
 625 };
 626
 627 &usbotg {
 628         vbus-supply = <&reg_usb_otg_vbus>;
 629         pinctrl-names = "default";
 630         pinctrl-0 = <&pinctrl_usbotg>;
 631         disable-over-current;
 632         status = "okay";
 633 };
 634
 635 &usbh1 {
 636         vbus-supply = <&reg_usb_h1_vbus>;
 637         status = "okay";
 638 };
 639
 640 &usdhc3 {
 641         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 642         pinctrl-0 = <&pinctrl_usdhc3>;
 643         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 644         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 645         non-removable;
 646         vmmc-supply = <&reg_3p3v>;
 647         keep-power-in-suspend;
 648         status = "okay";
 649 };
 650
 651 &wdog1 {
 652         pinctrl-names = "default";
 653         pinctrl-0 = <&pinctrl_wdog>;
 654         fsl,ext-reset-output;
 655 };
 656
 657 &iomuxc {
 658         pinctrl_enet: enetgrp {
 659                 fsl,pins = <
 660                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 661                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 662                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 663                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 664                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 665                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 666                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 667                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 668                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 669                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 670                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 671                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 672                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 673                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 674                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 675                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 676                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x4001b0b0 /* PHY_RST# */
 677                 >;
 678         };
 679
 680         pinctrl_gpio_leds: gpioledsgrp {
 681                 fsl,pins = <
 682                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 683                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 684                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 685                 >;
 686         };
 687
 688         pinctrl_i2c1: i2c1grp {
 689                 fsl,pins = <
 690                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 691                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 692                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0 /* GSC_IRQ# */
 693                 >;
 694         };
 695
 696         pinctrl_i2c2: i2c2grp {
 697                 fsl,pins = <
 698                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 699                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 700                 >;
 701         };
 702
 703         pinctrl_i2c3: i2c3grp {
 704                 fsl,pins = <
 705                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 706                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 707                 >;
 708         };
 709
 710         pinctrl_imu: imugrp {
 711                 fsl,pins = <
 712                         MX6QDL_PAD_DI0_PIN2__GPIO4_IO18         0x1b0b0
 713                 >;
 714         };
 715
 716         pinctrl_mag: maggrp {
 717                 fsl,pins = <
 718                         MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x1b0b0
 719                 >;
 720         };
 721
 722         pinctrl_pcie: pciegrp {
 723                 fsl,pins = <
 724                         MX6QDL_PAD_GPIO_0__GPIO1_IO00   0x1b0b0 /* PCIE RST */
 725                 >;
 726         };
 727
 728         pinctrl_pmic: pmicgrp {
 729                 fsl,pins = <
 730                         MX6QDL_PAD_GPIO_8__GPIO1_IO08   0x1b0b0 /* PMIC_IRQ# */
 731                 >;
 732         };
 733
 734         pinctrl_pps: ppsgrp {
 735                 fsl,pins = <
 736                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 737                 >;
 738         };
 739
 740         pinctrl_pwm2: pwm2grp {
 741                 fsl,pins = <
 742                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 743                 >;
 744         };
 745
 746         pinctrl_pwm3: pwm3grp {
 747                 fsl,pins = <
 748                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 749                 >;
 750         };
 751
 752         pinctrl_pwm4: pwm4grp {
 753                 fsl,pins = <
 754                         MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 755                 >;
 756         };
 757
 758         pinctrl_uart1: uart1grp {
 759                 fsl,pins = <
 760                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 761                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 762                 >;
 763         };
 764
 765         pinctrl_uart2: uart2grp {
 766                 fsl,pins = <
 767                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 768                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 769                 >;
 770         };
 771
 772         pinctrl_uart3: uart3grp {
 773                 fsl,pins = <
 774                         MX6QDL_PAD_EIM_D23__UART3_CTS_B         0x1b0b1
 775                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 776                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 777                         MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
 778                 >;
 779         };
 780
 781         pinctrl_uart4: uart4grp {
 782                 fsl,pins = <
 783                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
 784                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
 785                         MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
 786                         MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
 787                 >;
 788         };
 789
 790         pinctrl_uart5: uart5grp {
 791                 fsl,pins = <
 792                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 793                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 794                 >;
 795         };
 796
 797         pinctrl_usbotg: usbotggrp {
 798                 fsl,pins = <
 799                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 800                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* PWR_EN */
 801                         MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0 /* OC */
 802                 >;
 803         };
 804
 805         pinctrl_usdhc3: usdhc3grp {
 806                 fsl,pins = <
 807                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 808                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 809                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x10059
 810                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 811                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 812                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 813                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 814                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 815                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 816                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 817                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 818                 >;
 819         };
 820
 821         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 822                 fsl,pins = <
 823                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 824                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 825                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x100b9
 826                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 827                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 828                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 829                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 830                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
 831                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
 832                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
 833                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
 834                 >;
 835         };
 836
 837         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 838                 fsl,pins = <
 839                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 840                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 841                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x100f9
 842                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 843                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 844                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 845                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 846                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
 847                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
 848                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
 849                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
 850                 >;
 851         };
 852
 853         pinctrl_wdog: wdoggrp {
 854                 fsl,pins = <
 855                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 856                 >;
 857         };
 858 };