src/arm/nxp/imx/imx6qdl-phytec-pfla02.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         model = "Phytec phyFLEX-i.MX6 Quad";
  10         compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
  11
  12         memory@10000000 {
  13                 device_type = "memory";
  14                 reg = <0x10000000 0x80000000>;
  15         };
  16
  17         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  18                 compatible = "regulator-fixed";
  19                 regulator-name = "usb_otg_vbus";
  20                 regulator-min-microvolt = <5000000>;
  21                 regulator-max-microvolt = <5000000>;
  22                 gpio = <&gpio4 15 0>;
  23                 enable-active-high;
  24         };
  25
  26         reg_usb_h1_vbus: regulator-usb-h1-vbus {
  27                 compatible = "regulator-fixed";
  28                 pinctrl-names = "default";
  29                 pinctrl-0 = <&pinctrl_usbh1_vbus>;
  30                 regulator-name = "usb_h1_vbus";
  31                 regulator-min-microvolt = <5000000>;
  32                 regulator-max-microvolt = <5000000>;
  33                 gpio = <&gpio1 0 0>;
  34                 enable-active-high;
  35         };
  36
  37         gpio_leds: leds {
  38                 pinctrl-names = "default";
  39                 pinctrl-0 = <&pinctrl_leds>;
  40                 compatible = "gpio-leds";
  41
  42                 led_green: led-green {
  43                         label = "phyflex:green";
  44                         gpios = <&gpio1 30 0>;
  45                 };
  46
  47                 led_red: led-red {
  48                         label = "phyflex:red";
  49                         gpios = <&gpio2 31 0>;
  50                 };
  51         };
  52 };
  53
  54 &audmux {
  55         pinctrl-names = "default";
  56         pinctrl-0 = <&pinctrl_audmux>;
  57         status = "disabled";
  58 };
  59
  60 &can1 {
  61         pinctrl-names = "default";
  62         pinctrl-0 = <&pinctrl_flexcan1>;
  63         status = "disabled";
  64 };
  65
  66 &ecspi3 {
  67         pinctrl-names = "default";
  68         pinctrl-0 = <&pinctrl_ecspi3>;
  69         status = "okay";
  70         cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
  71
  72         som_flash: flash@0 {
  73                 compatible = "m25p80", "jedec,spi-nor";
  74                 spi-max-frequency = <20000000>;
  75                 reg = <0>;
  76         };
  77 };
  78
  79 &fec {
  80         pinctrl-names = "default";
  81         pinctrl-0 = <&pinctrl_enet>;
  82         phy-handle = <&ethphy>;
  83         phy-mode = "rgmii";
  84         phy-reset-duration = <10>; /* in msecs */
  85         phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
  86         phy-supply = <&vdd_eth_io_reg>;
  87         status = "disabled";
  88
  89         fec_mdio: mdio {
  90                 #address-cells = <1>;
  91                 #size-cells = <0>;
  92
  93                 ethphy: ethernet-phy@0 {
  94                         compatible = "ethernet-phy-ieee802.3-c22";
  95                         reg = <0>;
  96                         txc-skew-ps = <1680>;
  97                         rxc-skew-ps = <1860>;
  98                 };
  99         };
 100 };
 101
 102 &gpmi {
 103         pinctrl-names = "default";
 104         pinctrl-0 = <&pinctrl_gpmi_nand>;
 105         nand-on-flash-bbt;
 106         status = "okay";
 107 };
 108
 109 &i2c1 {
 110         pinctrl-names = "default";
 111         pinctrl-0 = <&pinctrl_i2c1>;
 112         status = "okay";
 113
 114         som_eeprom: eeprom@50 {
 115                 compatible = "catalyst,24c32", "atmel,24c32";
 116                 pagesize = <32>;
 117                 reg = <0x50>;
 118         };
 119
 120         pmic@58 {
 121                 pinctrl-names = "default";
 122                 pinctrl-0 = <&pinctrl_pmic>;
 123                 compatible = "dlg,da9063";
 124                 reg = <0x58>;
 125                 interrupt-parent = <&gpio2>;
 126                 interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
 127                 interrupt-controller;
 128
 129                 regulators {
 130                         vddcore_reg: bcore1 {
 131                                 regulator-min-microvolt = <730000>;
 132                                 regulator-max-microvolt = <1380000>;
 133                                 regulator-always-on;
 134                         };
 135
 136                         vddsoc_reg: bcore2 {
 137                                 regulator-min-microvolt = <730000>;
 138                                 regulator-max-microvolt = <1380000>;
 139                                 regulator-always-on;
 140                         };
 141
 142                         vdd_ddr3_reg: bpro {
 143                                 regulator-min-microvolt = <1500000>;
 144                                 regulator-max-microvolt = <1500000>;
 145                                 regulator-always-on;
 146                         };
 147
 148                         vdd_3v3_reg: bperi {
 149                                 regulator-min-microvolt = <3300000>;
 150                                 regulator-max-microvolt = <3300000>;
 151                                 regulator-always-on;
 152                         };
 153
 154                         vdd_buckmem_reg: bmem {
 155                                 regulator-min-microvolt = <3300000>;
 156                                 regulator-max-microvolt = <3300000>;
 157                                 regulator-always-on;
 158                         };
 159
 160                         vdd_eth_reg: bio {
 161                                 regulator-min-microvolt = <1200000>;
 162                                 regulator-max-microvolt = <1200000>;
 163                                 regulator-always-on;
 164                         };
 165
 166                         vdd_eth_io_reg: ldo4 {
 167                                 regulator-min-microvolt = <2500000>;
 168                                 regulator-max-microvolt = <2500000>;
 169                                 regulator-always-on;
 170                         };
 171
 172                         vdd_mx6_snvs_reg: ldo5 {
 173                                 regulator-min-microvolt = <3000000>;
 174                                 regulator-max-microvolt = <3000000>;
 175                                 regulator-always-on;
 176                         };
 177
 178                         vdd_3v3_pmic_io_reg: ldo6 {
 179                                 regulator-min-microvolt = <3300000>;
 180                                 regulator-max-microvolt = <3300000>;
 181                                 regulator-always-on;
 182                         };
 183
 184                         vdd_sd0_reg: ldo9 {
 185                                 regulator-min-microvolt = <3300000>;
 186                                 regulator-max-microvolt = <3300000>;
 187                         };
 188
 189                         vdd_sd1_reg: ldo10 {
 190                                 regulator-min-microvolt = <3300000>;
 191                                 regulator-max-microvolt = <3300000>;
 192                         };
 193
 194                         vdd_mx6_high_reg: ldo11 {
 195                                 regulator-min-microvolt = <3000000>;
 196                                 regulator-max-microvolt = <3000000>;
 197                                 regulator-always-on;
 198                         };
 199                 };
 200
 201                 da9063_rtc: rtc {
 202                         compatible = "dlg,da9063-rtc";
 203                 };
 204
 205                 da9063_wdog: watchdog {
 206                         compatible = "dlg,da9063-watchdog";
 207                 };
 208
 209                 onkey {
 210                         compatible = "dlg,da9063-onkey";
 211                         status = "disabled";
 212                 };
 213         };
 214 };
 215
 216 &i2c2 {
 217         pinctrl-names = "default";
 218         pinctrl-0 = <&pinctrl_i2c2>;
 219         clock-frequency = <100000>;
 220 };
 221
 222 &i2c3 {
 223         pinctrl-names = "default";
 224         pinctrl-0 = <&pinctrl_i2c3>;
 225         clock-frequency = <100000>;
 226 };
 227
 228 &iomuxc {
 229         imx6q-phytec-pfla02 {
 230                 pinctrl_ecspi3: ecspi3grp {
 231                         fsl,pins = <
 232                                 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 233                                 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 234                                 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 235                                 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24       0x80000000 /* CS0 */
 236                         >;
 237                 };
 238
 239                 pinctrl_enet: enetgrp {
 240                         fsl,pins = <
 241                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 242                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 243                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 244                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 245                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 246                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 247                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 248                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 249                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 250                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 251                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 252                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 253                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 254                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 255                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 256                                 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 257                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x80000000 /* Reset GPIO */
 258                         >;
 259                 };
 260
 261                 pinctrl_flexcan1: flexcan1grp {
 262                         fsl,pins = <
 263                                 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b0
 264                                 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b0
 265                         >;
 266                 };
 267
 268                 pinctrl_gpmi_nand: gpminandgrp {
 269                         fsl,pins = <
 270                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 271                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 272                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 273                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 274                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 275                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 276                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 277                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 278                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 279                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 280                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 281                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 282                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 283                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 284                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 285                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 286                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 287                         >;
 288                 };
 289
 290                 pinctrl_i2c1: i2c1grp {
 291                         fsl,pins = <
 292                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 293                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 294                         >;
 295                 };
 296
 297                 pinctrl_i2c2: i2c2grp {
 298                         fsl,pins = <
 299                                 MX6QDL_PAD_EIM_EB2__I2C2_SCL            0x4001b8b1
 300                                 MX6QDL_PAD_EIM_D16__I2C2_SDA            0x4001b8b1
 301                         >;
 302                 };
 303
 304                 pinctrl_i2c3: i2c3grp {
 305                         fsl,pins = <
 306                                 MX6QDL_PAD_EIM_D17__I2C3_SCL            0x4001b8b1
 307                                 MX6QDL_PAD_EIM_D18__I2C3_SDA            0x4001b8b1
 308                         >;
 309                 };
 310
 311                 pinctrl_leds: ledsgrp {
 312                         fsl,pins = <
 313                                 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x80000000 /* Green LED */
 314                                 MX6QDL_PAD_EIM_EB3__GPIO2_IO31          0x80000000 /* Red LED */
 315                         >;
 316                 };
 317
 318                 pinctrl_pcie: pciegrp {
 319                         fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000>;
 320                 };
 321
 322                 pinctrl_pmic: pmicgrp {
 323                         fsl,pins = <MX6QDL_PAD_SD4_DAT1__GPIO2_IO09     0x80000000>; /* PMIC interrupt */
 324                 };
 325
 326                 pinctrl_uart3: uart3grp {
 327                         fsl,pins = <
 328                                 MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 329                                 MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 330                                 MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
 331                                 MX6QDL_PAD_EIM_D30__UART3_CTS_B         0x1b0b1
 332                         >;
 333                 };
 334
 335                 pinctrl_uart4: uart4grp {
 336                         fsl,pins = <
 337                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 338                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 339                         >;
 340                 };
 341
 342                 pinctrl_usbh1_vbus: usbh1vbusgrp {
 343                         fsl,pins = <
 344                                 MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0
 345                         >;
 346                 };
 347
 348                 pinctrl_usbotg: usbotggrp {
 349                         fsl,pins = <
 350                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 351                                 MX6QDL_PAD_KEY_COL4__USB_OTG_OC         0x1b0b0
 352                                 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x80000000
 353                         >;
 354                 };
 355
 356                 pinctrl_usdhc2: usdhc2grp {
 357                         fsl,pins = <
 358                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 359                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 360                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 361                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 362                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 363                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 364                         >;
 365                 };
 366
 367                 pinctrl_usdhc3: usdhc3grp {
 368                         fsl,pins = <
 369                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 370                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 371                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 372                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 373                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 374                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 375                         >;
 376                 };
 377
 378                 pinctrl_usdhc3_cdwp: usdhc3cdwp {
 379                         fsl,pins = <
 380                                 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
 381                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
 382                         >;
 383                 };
 384
 385                 pinctrl_audmux: audmuxgrp {
 386                         fsl,pins = <
 387                                 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC        0x130b0
 388                                 MX6QDL_PAD_DISP0_DAT17__AUD5_TXD        0x110b0
 389                                 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS       0x130b0
 390                                 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
 391                         >;
 392                 };
 393         };
 394 };
 395
 396 &pcie {
 397         pinctrl-names = "default";
 398         pinctrl-0 = <&pinctrl_pcie>;
 399         reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>;
 400         status = "disabled";
 401 };
 402
 403 &reg_arm {
 404         vin-supply = <&vddcore_reg>;
 405 };
 406
 407 &reg_pu {
 408         vin-supply = <&vddsoc_reg>;
 409 };
 410
 411 &reg_soc {
 412         vin-supply = <&vddsoc_reg>;
 413 };
 414
 415 &uart3 {
 416         pinctrl-names = "default";
 417         pinctrl-0 = <&pinctrl_uart3>;
 418         uart-has-rtscts;
 419         status = "disabled";
 420 };
 421
 422 &uart4 {
 423         pinctrl-names = "default";
 424         pinctrl-0 = <&pinctrl_uart4>;
 425         status = "disabled";
 426 };
 427
 428 &usbh1 {
 429         vbus-supply = <&reg_usb_h1_vbus>;
 430         status = "disabled";
 431 };
 432
 433 &usbotg {
 434         vbus-supply = <&reg_usb_otg_vbus>;
 435         pinctrl-names = "default";
 436         pinctrl-0 = <&pinctrl_usbotg>;
 437         disable-over-current;
 438         status = "disabled";
 439 };
 440
 441 &usdhc2 {
 442         pinctrl-names = "default";
 443         pinctrl-0 = <&pinctrl_usdhc2>;
 444         cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 445         wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 446         vmmc-supply = <&vdd_sd1_reg>;
 447         status = "disabled";
 448 };
 449
 450 &usdhc3 {
 451         pinctrl-names = "default";
 452         pinctrl-0 = <&pinctrl_usdhc3
 453                      &pinctrl_usdhc3_cdwp>;
 454         cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
 455         wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
 456         vmmc-supply = <&vdd_sd0_reg>;
 457         status = "disabled";
 458 };
 459
 460 &wdog1 {
 461         /*
 462          * Rely on PMIC reboot handler. Internal i.MX6 watchdog, that is also
 463          * used for reboot, does not reset all external PMIC voltages on reset.
 464          */
 465         status = "disabled";
 466 };