1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright 2011 Freescale Semiconductor, Inc.
4 // Copyright 2011 Linaro Ltd.
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 * The decompressor and also some bootloaders rely on a
15 * pre-existing /chosen node to be available to insert the
16 * command line and merge other ATAGS info.
58 compatible = "fixed-clock";
60 clock-frequency = <32768>;
64 compatible = "fixed-clock";
66 clock-frequency = <0>;
70 compatible = "fixed-clock";
72 clock-frequency = <24000000>;
79 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
92 lvds0_mux_0: endpoint {
93 remote-endpoint = <&ipu1_di0_lvds0>;
100 lvds0_mux_1: endpoint {
101 remote-endpoint = <&ipu1_di1_lvds0>;
107 #address-cells = <1>;
115 lvds1_mux_0: endpoint {
116 remote-endpoint = <&ipu1_di0_lvds1>;
123 lvds1_mux_1: endpoint {
124 remote-endpoint = <&ipu1_di1_lvds1>;
131 compatible = "arm,cortex-a9-pmu";
132 interrupt-parent = <&gpc>;
133 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
136 usbphynop1: usbphynop1 {
137 compatible = "usb-nop-xceiv";
141 usbphynop2: usbphynop2 {
142 compatible = "usb-nop-xceiv";
147 #address-cells = <1>;
149 compatible = "simple-bus";
150 interrupt-parent = <&gpc>;
153 dma_apbh: dma-controller@110000 {
154 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
155 reg = <0x00110000 0x2000>;
156 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
157 <0 13 IRQ_TYPE_LEVEL_HIGH>,
158 <0 13 IRQ_TYPE_LEVEL_HIGH>,
159 <0 13 IRQ_TYPE_LEVEL_HIGH>;
162 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
165 gpmi: nand-controller@112000 {
166 compatible = "fsl,imx6q-gpmi-nand";
167 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
168 reg-names = "gpmi-nand", "bch";
169 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
170 interrupt-names = "bch";
171 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
172 <&clks IMX6QDL_CLK_GPMI_APB>,
173 <&clks IMX6QDL_CLK_GPMI_BCH>,
174 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
175 <&clks IMX6QDL_CLK_PER1_BCH>;
176 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
177 "gpmi_bch_apb", "per1_bch";
178 dmas = <&dma_apbh 0>;
184 reg = <0x00120000 0x9000>;
185 interrupts = <0 115 0x04>;
187 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
188 <&clks IMX6QDL_CLK_HDMI_ISFR>;
189 clock-names = "iahb", "isfr";
193 #address-cells = <1>;
199 hdmi_mux_0: endpoint {
200 remote-endpoint = <&ipu1_di0_hdmi>;
207 hdmi_mux_1: endpoint {
208 remote-endpoint = <&ipu1_di1_hdmi>;
215 compatible = "vivante,gc";
216 reg = <0x00130000 0x4000>;
217 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
219 <&clks IMX6QDL_CLK_GPU3D_CORE>,
220 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
221 clock-names = "bus", "core", "shader";
222 power-domains = <&pd_pu>;
223 #cooling-cells = <2>;
227 compatible = "vivante,gc";
228 reg = <0x00134000 0x4000>;
229 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
231 <&clks IMX6QDL_CLK_GPU2D_CORE>;
232 clock-names = "bus", "core";
233 power-domains = <&pd_pu>;
234 #cooling-cells = <2>;
238 compatible = "arm,cortex-a9-twd-timer";
239 reg = <0x00a00600 0x20>;
240 interrupts = <1 13 0xf01>;
241 interrupt-parent = <&intc>;
242 clocks = <&clks IMX6QDL_CLK_TWD>;
245 intc: interrupt-controller@a01000 {
246 compatible = "arm,cortex-a9-gic";
247 #interrupt-cells = <3>;
248 interrupt-controller;
249 reg = <0x00a01000 0x1000>,
251 interrupt-parent = <&intc>;
254 L2: cache-controller@a02000 {
255 compatible = "arm,pl310-cache";
256 reg = <0x00a02000 0x1000>;
257 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
260 arm,tag-latency = <4 2 3>;
261 arm,data-latency = <4 2 3>;
266 compatible = "fsl,imx6q-pcie";
267 reg = <0x01ffc000 0x04000>,
268 <0x01f00000 0x80000>;
269 reg-names = "dbi", "config";
270 #address-cells = <3>;
273 bus-range = <0x00 0xff>;
274 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, /* downstream I/O */
275 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
277 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
278 interrupt-names = "msi";
279 #interrupt-cells = <1>;
280 interrupt-map-mask = <0 0 0 0x7>;
281 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
282 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
283 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
284 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
286 <&clks IMX6QDL_CLK_LVDS1_GATE>,
287 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
288 clock-names = "pcie", "pcie_bus", "pcie_phy";
292 aips1: bus@2000000 { /* AIPS1 */
293 compatible = "fsl,aips-bus", "simple-bus";
294 #address-cells = <1>;
296 reg = <0x02000000 0x100000>;
300 compatible = "fsl,spba-bus", "simple-bus";
301 #address-cells = <1>;
303 reg = <0x02000000 0x40000>;
306 spdif: spdif@2004000 {
307 compatible = "fsl,imx35-spdif";
308 reg = <0x02004000 0x4000>;
309 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
310 dmas = <&sdma 14 18 0>,
312 dma-names = "rx", "tx";
313 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
314 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
315 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
316 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
317 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
318 clock-names = "core", "rxtx0",
326 ecspi1: spi@2008000 {
327 #address-cells = <1>;
329 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
330 reg = <0x02008000 0x4000>;
331 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
333 <&clks IMX6QDL_CLK_ECSPI1>;
334 clock-names = "ipg", "per";
335 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
336 dma-names = "rx", "tx";
340 ecspi2: spi@200c000 {
341 #address-cells = <1>;
343 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
344 reg = <0x0200c000 0x4000>;
345 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
347 <&clks IMX6QDL_CLK_ECSPI2>;
348 clock-names = "ipg", "per";
349 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
350 dma-names = "rx", "tx";
354 ecspi3: spi@2010000 {
355 #address-cells = <1>;
357 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
358 reg = <0x02010000 0x4000>;
359 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
361 <&clks IMX6QDL_CLK_ECSPI3>;
362 clock-names = "ipg", "per";
363 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
364 dma-names = "rx", "tx";
368 ecspi4: spi@2014000 {
369 #address-cells = <1>;
371 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
372 reg = <0x02014000 0x4000>;
373 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
375 <&clks IMX6QDL_CLK_ECSPI4>;
376 clock-names = "ipg", "per";
377 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
378 dma-names = "rx", "tx";
382 uart1: serial@2020000 {
383 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
384 reg = <0x02020000 0x4000>;
385 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
387 <&clks IMX6QDL_CLK_UART_SERIAL>;
388 clock-names = "ipg", "per";
389 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
390 dma-names = "rx", "tx";
395 #sound-dai-cells = <0>;
396 compatible = "fsl,imx35-esai";
397 reg = <0x02024000 0x4000>;
398 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
400 <&clks IMX6QDL_CLK_ESAI_MEM>,
401 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
402 <&clks IMX6QDL_CLK_ESAI_IPG>,
403 <&clks IMX6QDL_CLK_SPBA>;
404 clock-names = "core", "mem", "extal", "fsys", "spba";
405 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
406 dma-names = "rx", "tx";
411 #sound-dai-cells = <0>;
412 compatible = "fsl,imx6q-ssi",
414 reg = <0x02028000 0x4000>;
415 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
417 <&clks IMX6QDL_CLK_SSI1>;
418 clock-names = "ipg", "baud";
419 dmas = <&sdma 37 1 0>,
421 dma-names = "rx", "tx";
422 fsl,fifo-depth = <15>;
427 #sound-dai-cells = <0>;
428 compatible = "fsl,imx6q-ssi",
430 reg = <0x0202c000 0x4000>;
431 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
433 <&clks IMX6QDL_CLK_SSI2>;
434 clock-names = "ipg", "baud";
435 dmas = <&sdma 41 1 0>,
437 dma-names = "rx", "tx";
438 fsl,fifo-depth = <15>;
443 #sound-dai-cells = <0>;
444 compatible = "fsl,imx6q-ssi",
446 reg = <0x02030000 0x4000>;
447 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
449 <&clks IMX6QDL_CLK_SSI3>;
450 clock-names = "ipg", "baud";
451 dmas = <&sdma 45 1 0>,
453 dma-names = "rx", "tx";
454 fsl,fifo-depth = <15>;
459 compatible = "fsl,imx53-asrc";
460 reg = <0x02034000 0x4000>;
461 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
463 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
464 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
465 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
466 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
467 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
468 <&clks IMX6QDL_CLK_SPBA>;
469 clock-names = "mem", "ipg", "asrck_0",
470 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
471 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
472 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
473 "asrck_d", "asrck_e", "asrck_f", "spba";
474 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
475 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
476 dma-names = "rxa", "rxb", "rxc",
478 fsl,asrc-rate = <48000>;
479 fsl,asrc-width = <16>;
484 reg = <0x0203c000 0x4000>;
489 compatible = "cnm,coda960";
490 reg = <0x02040000 0x3c000>;
491 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
492 <0 3 IRQ_TYPE_LEVEL_HIGH>;
493 interrupt-names = "bit", "jpeg";
494 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
495 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
496 clock-names = "per", "ahb";
497 power-domains = <&pd_pu>;
502 aipstz@207c000 { /* AIPSTZ1 */
503 reg = <0x0207c000 0x4000>;
508 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
509 reg = <0x02080000 0x4000>;
510 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&clks IMX6QDL_CLK_IPG>,
512 <&clks IMX6QDL_CLK_PWM1>;
513 clock-names = "ipg", "per";
519 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
520 reg = <0x02084000 0x4000>;
521 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&clks IMX6QDL_CLK_IPG>,
523 <&clks IMX6QDL_CLK_PWM2>;
524 clock-names = "ipg", "per";
530 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
531 reg = <0x02088000 0x4000>;
532 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&clks IMX6QDL_CLK_IPG>,
534 <&clks IMX6QDL_CLK_PWM3>;
535 clock-names = "ipg", "per";
541 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
542 reg = <0x0208c000 0x4000>;
543 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&clks IMX6QDL_CLK_IPG>,
545 <&clks IMX6QDL_CLK_PWM4>;
546 clock-names = "ipg", "per";
551 compatible = "fsl,imx6q-flexcan";
552 reg = <0x02090000 0x4000>;
553 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
555 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
556 clock-names = "ipg", "per";
557 fsl,stop-mode = <&gpr 0x34 28>;
562 compatible = "fsl,imx6q-flexcan";
563 reg = <0x02094000 0x4000>;
564 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
566 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
567 clock-names = "ipg", "per";
568 fsl,stop-mode = <&gpr 0x34 29>;
573 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
574 reg = <0x02098000 0x4000>;
575 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
577 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
578 <&clks IMX6QDL_CLK_GPT_3M>;
579 clock-names = "ipg", "per", "osc_per";
582 gpio1: gpio@209c000 {
583 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
584 reg = <0x0209c000 0x4000>;
585 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
586 <0 67 IRQ_TYPE_LEVEL_HIGH>;
589 interrupt-controller;
590 #interrupt-cells = <2>;
593 gpio2: gpio@20a0000 {
594 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
595 reg = <0x020a0000 0x4000>;
596 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
597 <0 69 IRQ_TYPE_LEVEL_HIGH>;
600 interrupt-controller;
601 #interrupt-cells = <2>;
604 gpio3: gpio@20a4000 {
605 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
606 reg = <0x020a4000 0x4000>;
607 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
608 <0 71 IRQ_TYPE_LEVEL_HIGH>;
611 interrupt-controller;
612 #interrupt-cells = <2>;
615 gpio4: gpio@20a8000 {
616 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
617 reg = <0x020a8000 0x4000>;
618 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
619 <0 73 IRQ_TYPE_LEVEL_HIGH>;
622 interrupt-controller;
623 #interrupt-cells = <2>;
626 gpio5: gpio@20ac000 {
627 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
628 reg = <0x020ac000 0x4000>;
629 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
630 <0 75 IRQ_TYPE_LEVEL_HIGH>;
633 interrupt-controller;
634 #interrupt-cells = <2>;
637 gpio6: gpio@20b0000 {
638 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
639 reg = <0x020b0000 0x4000>;
640 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
641 <0 77 IRQ_TYPE_LEVEL_HIGH>;
644 interrupt-controller;
645 #interrupt-cells = <2>;
648 gpio7: gpio@20b4000 {
649 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
650 reg = <0x020b4000 0x4000>;
651 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
652 <0 79 IRQ_TYPE_LEVEL_HIGH>;
655 interrupt-controller;
656 #interrupt-cells = <2>;
659 kpp: keypad@20b8000 {
660 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
661 reg = <0x020b8000 0x4000>;
662 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&clks IMX6QDL_CLK_IPG>;
667 wdog1: watchdog@20bc000 {
668 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
669 reg = <0x020bc000 0x4000>;
670 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&clks IMX6QDL_CLK_IPG>;
674 wdog2: watchdog@20c0000 {
675 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
676 reg = <0x020c0000 0x4000>;
677 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&clks IMX6QDL_CLK_IPG>;
682 clks: clock-controller@20c4000 {
683 compatible = "fsl,imx6q-ccm";
684 reg = <0x020c4000 0x4000>;
685 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
686 <0 88 IRQ_TYPE_LEVEL_HIGH>;
690 anatop: anatop@20c8000 {
691 compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
692 reg = <0x020c8000 0x1000>;
693 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
694 <0 54 IRQ_TYPE_LEVEL_HIGH>,
695 <0 127 IRQ_TYPE_LEVEL_HIGH>;
697 reg_vdd1p1: regulator-1p1 {
698 compatible = "fsl,anatop-regulator";
699 regulator-name = "vdd1p1";
700 regulator-min-microvolt = <1000000>;
701 regulator-max-microvolt = <1200000>;
703 anatop-reg-offset = <0x110>;
704 anatop-vol-bit-shift = <8>;
705 anatop-vol-bit-width = <5>;
706 anatop-min-bit-val = <4>;
707 anatop-min-voltage = <800000>;
708 anatop-max-voltage = <1375000>;
709 anatop-enable-bit = <0>;
712 reg_vdd3p0: regulator-3p0 {
713 compatible = "fsl,anatop-regulator";
714 regulator-name = "vdd3p0";
715 regulator-min-microvolt = <2800000>;
716 regulator-max-microvolt = <3150000>;
718 anatop-reg-offset = <0x120>;
719 anatop-vol-bit-shift = <8>;
720 anatop-vol-bit-width = <5>;
721 anatop-min-bit-val = <0>;
722 anatop-min-voltage = <2625000>;
723 anatop-max-voltage = <3400000>;
724 anatop-enable-bit = <0>;
727 reg_vdd2p5: regulator-2p5 {
728 compatible = "fsl,anatop-regulator";
729 regulator-name = "vdd2p5";
730 regulator-min-microvolt = <2250000>;
731 regulator-max-microvolt = <2750000>;
733 anatop-reg-offset = <0x130>;
734 anatop-vol-bit-shift = <8>;
735 anatop-vol-bit-width = <5>;
736 anatop-min-bit-val = <0>;
737 anatop-min-voltage = <2100000>;
738 anatop-max-voltage = <2875000>;
739 anatop-enable-bit = <0>;
742 reg_arm: regulator-vddcore {
743 compatible = "fsl,anatop-regulator";
744 regulator-name = "vddarm";
745 regulator-min-microvolt = <725000>;
746 regulator-max-microvolt = <1450000>;
748 anatop-reg-offset = <0x140>;
749 anatop-vol-bit-shift = <0>;
750 anatop-vol-bit-width = <5>;
751 anatop-delay-reg-offset = <0x170>;
752 anatop-delay-bit-shift = <24>;
753 anatop-delay-bit-width = <2>;
754 anatop-min-bit-val = <1>;
755 anatop-min-voltage = <725000>;
756 anatop-max-voltage = <1450000>;
759 reg_pu: regulator-vddpu {
760 compatible = "fsl,anatop-regulator";
761 regulator-name = "vddpu";
762 regulator-min-microvolt = <725000>;
763 regulator-max-microvolt = <1450000>;
764 regulator-enable-ramp-delay = <380>;
765 anatop-reg-offset = <0x140>;
766 anatop-vol-bit-shift = <9>;
767 anatop-vol-bit-width = <5>;
768 anatop-delay-reg-offset = <0x170>;
769 anatop-delay-bit-shift = <26>;
770 anatop-delay-bit-width = <2>;
771 anatop-min-bit-val = <1>;
772 anatop-min-voltage = <725000>;
773 anatop-max-voltage = <1450000>;
776 reg_soc: regulator-vddsoc {
777 compatible = "fsl,anatop-regulator";
778 regulator-name = "vddsoc";
779 regulator-min-microvolt = <725000>;
780 regulator-max-microvolt = <1450000>;
782 anatop-reg-offset = <0x140>;
783 anatop-vol-bit-shift = <18>;
784 anatop-vol-bit-width = <5>;
785 anatop-delay-reg-offset = <0x170>;
786 anatop-delay-bit-shift = <28>;
787 anatop-delay-bit-width = <2>;
788 anatop-min-bit-val = <1>;
789 anatop-min-voltage = <725000>;
790 anatop-max-voltage = <1450000>;
794 compatible = "fsl,imx6q-tempmon";
795 interrupt-parent = <&gpc>;
796 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
797 fsl,tempmon = <&anatop>;
798 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
799 nvmem-cell-names = "calib", "temp_grade";
800 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
801 #thermal-sensor-cells = <0>;
805 usbphy1: usbphy@20c9000 {
806 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
807 reg = <0x020c9000 0x1000>;
808 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
809 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
810 fsl,anatop = <&anatop>;
813 usbphy2: usbphy@20ca000 {
814 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
815 reg = <0x020ca000 0x1000>;
816 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
817 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
818 fsl,anatop = <&anatop>;
822 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
823 reg = <0x020cc000 0x4000>;
825 snvs_rtc: snvs-rtc-lp {
826 compatible = "fsl,sec-v4.0-mon-rtc-lp";
829 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
830 <0 20 IRQ_TYPE_LEVEL_HIGH>;
833 snvs_poweroff: snvs-poweroff {
834 compatible = "syscon-poweroff";
842 snvs_pwrkey: snvs-powerkey {
843 compatible = "fsl,sec-v4.0-pwrkey";
845 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
846 linux,keycode = <KEY_POWER>;
851 snvs_lpgpr: snvs-lpgpr {
852 compatible = "fsl,imx6q-snvs-lpgpr";
856 epit1: epit@20d0000 { /* EPIT1 */
857 reg = <0x020d0000 0x4000>;
858 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
861 epit2: epit@20d4000 { /* EPIT2 */
862 reg = <0x020d4000 0x4000>;
863 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
866 src: reset-controller@20d8000 {
867 compatible = "fsl,imx6q-src", "fsl,imx51-src";
868 reg = <0x020d8000 0x4000>;
869 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
870 <0 96 IRQ_TYPE_LEVEL_HIGH>;
875 compatible = "fsl,imx6q-gpc";
876 reg = <0x020dc000 0x4000>;
877 interrupt-controller;
878 #interrupt-cells = <3>;
879 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
880 interrupt-parent = <&intc>;
881 clocks = <&clks IMX6QDL_CLK_IPG>;
885 #address-cells = <1>;
890 #power-domain-cells = <0>;
892 pd_pu: power-domain@1 {
894 #power-domain-cells = <0>;
895 power-supply = <®_pu>;
896 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
897 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
898 <&clks IMX6QDL_CLK_GPU2D_CORE>,
899 <&clks IMX6QDL_CLK_GPU2D_AXI>,
900 <&clks IMX6QDL_CLK_OPENVG_AXI>,
901 <&clks IMX6QDL_CLK_VPU_AXI>;
906 gpr: iomuxc-gpr@20e0000 {
907 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
908 reg = <0x20e0000 0x38>;
910 mux: mux-controller {
911 compatible = "mmio-mux";
912 #mux-control-cells = <1>;
916 iomuxc: pinctrl@20e0000 {
917 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
918 reg = <0x20e0000 0x4000>;
921 dcic1: dcic@20e4000 {
922 reg = <0x020e4000 0x4000>;
923 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
926 dcic2: dcic@20e8000 {
927 reg = <0x020e8000 0x4000>;
928 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
931 sdma: dma-controller@20ec000 {
932 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
933 reg = <0x020ec000 0x4000>;
934 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&clks IMX6QDL_CLK_IPG>,
936 <&clks IMX6QDL_CLK_SDMA>;
937 clock-names = "ipg", "ahb";
939 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
943 aips2: bus@2100000 { /* AIPS2 */
944 compatible = "fsl,aips-bus", "simple-bus";
945 #address-cells = <1>;
947 reg = <0x02100000 0x100000>;
950 crypto: crypto@2100000 {
951 compatible = "fsl,sec-v4.0";
952 #address-cells = <1>;
954 reg = <0x2100000 0x10000>;
955 ranges = <0 0x2100000 0x10000>;
956 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
957 <&clks IMX6QDL_CLK_CAAM_ACLK>,
958 <&clks IMX6QDL_CLK_CAAM_IPG>,
959 <&clks IMX6QDL_CLK_EIM_SLOW>;
960 clock-names = "mem", "aclk", "ipg", "emi_slow";
963 compatible = "fsl,sec-v4.0-job-ring";
964 reg = <0x1000 0x1000>;
965 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
969 compatible = "fsl,sec-v4.0-job-ring";
970 reg = <0x2000 0x1000>;
971 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
975 aipstz@217c000 { /* AIPSTZ2 */
976 reg = <0x0217c000 0x4000>;
979 usbotg: usb@2184000 {
980 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
981 reg = <0x02184000 0x200>;
982 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&clks IMX6QDL_CLK_USBOH3>;
984 fsl,usbphy = <&usbphy1>;
985 fsl,usbmisc = <&usbmisc 0>;
986 ahb-burst-config = <0x0>;
987 tx-burst-size-dword = <0x10>;
988 rx-burst-size-dword = <0x10>;
993 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
994 reg = <0x02184200 0x200>;
995 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&clks IMX6QDL_CLK_USBOH3>;
997 fsl,usbphy = <&usbphy2>;
998 fsl,usbmisc = <&usbmisc 1>;
1000 ahb-burst-config = <0x0>;
1001 tx-burst-size-dword = <0x10>;
1002 rx-burst-size-dword = <0x10>;
1003 status = "disabled";
1006 usbh2: usb@2184400 {
1007 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1008 reg = <0x02184400 0x200>;
1009 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1011 fsl,usbphy = <&usbphynop1>;
1013 fsl,usbmisc = <&usbmisc 2>;
1015 ahb-burst-config = <0x0>;
1016 tx-burst-size-dword = <0x10>;
1017 rx-burst-size-dword = <0x10>;
1018 status = "disabled";
1021 usbh3: usb@2184600 {
1022 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1023 reg = <0x02184600 0x200>;
1024 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1025 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1026 fsl,usbphy = <&usbphynop2>;
1028 fsl,usbmisc = <&usbmisc 3>;
1030 ahb-burst-config = <0x0>;
1031 tx-burst-size-dword = <0x10>;
1032 rx-burst-size-dword = <0x10>;
1033 status = "disabled";
1036 usbmisc: usbmisc@2184800 {
1038 compatible = "fsl,imx6q-usbmisc";
1039 reg = <0x02184800 0x200>;
1040 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1043 fec: ethernet@2188000 {
1044 compatible = "fsl,imx6q-fec";
1045 reg = <0x02188000 0x4000>;
1046 interrupt-names = "int0", "pps";
1047 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
1048 <0 119 IRQ_TYPE_LEVEL_HIGH>;
1049 clocks = <&clks IMX6QDL_CLK_ENET>,
1050 <&clks IMX6QDL_CLK_ENET>,
1051 <&clks IMX6QDL_CLK_ENET_REF>,
1052 <&clks IMX6QDL_CLK_ENET_REF_SEL>;
1053 clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
1054 fsl,stop-mode = <&gpr 0x34 27>;
1055 nvmem-cells = <&fec_mac_addr>;
1056 nvmem-cell-names = "mac-address";
1057 status = "disabled";
1061 reg = <0x0218c000 0x4000>;
1062 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1063 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1064 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1067 usdhc1: mmc@2190000 {
1068 compatible = "fsl,imx6q-usdhc";
1069 reg = <0x02190000 0x4000>;
1070 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1071 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1072 <&clks IMX6QDL_CLK_USDHC1>,
1073 <&clks IMX6QDL_CLK_USDHC1>;
1074 clock-names = "ipg", "ahb", "per";
1076 status = "disabled";
1079 usdhc2: mmc@2194000 {
1080 compatible = "fsl,imx6q-usdhc";
1081 reg = <0x02194000 0x4000>;
1082 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1083 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1084 <&clks IMX6QDL_CLK_USDHC2>,
1085 <&clks IMX6QDL_CLK_USDHC2>;
1086 clock-names = "ipg", "ahb", "per";
1088 status = "disabled";
1091 usdhc3: mmc@2198000 {
1092 compatible = "fsl,imx6q-usdhc";
1093 reg = <0x02198000 0x4000>;
1094 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1095 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1096 <&clks IMX6QDL_CLK_USDHC3>,
1097 <&clks IMX6QDL_CLK_USDHC3>;
1098 clock-names = "ipg", "ahb", "per";
1100 status = "disabled";
1103 usdhc4: mmc@219c000 {
1104 compatible = "fsl,imx6q-usdhc";
1105 reg = <0x0219c000 0x4000>;
1106 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1107 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1108 <&clks IMX6QDL_CLK_USDHC4>,
1109 <&clks IMX6QDL_CLK_USDHC4>;
1110 clock-names = "ipg", "ahb", "per";
1112 status = "disabled";
1116 #address-cells = <1>;
1118 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1119 reg = <0x021a0000 0x4000>;
1120 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1121 clocks = <&clks IMX6QDL_CLK_I2C1>;
1122 status = "disabled";
1126 #address-cells = <1>;
1128 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1129 reg = <0x021a4000 0x4000>;
1130 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1131 clocks = <&clks IMX6QDL_CLK_I2C2>;
1132 status = "disabled";
1136 #address-cells = <1>;
1138 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1139 reg = <0x021a8000 0x4000>;
1140 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1141 clocks = <&clks IMX6QDL_CLK_I2C3>;
1142 status = "disabled";
1146 reg = <0x021ac000 0x4000>;
1149 mmdc0: memory-controller@21b0000 { /* MMDC0 */
1150 compatible = "fsl,imx6q-mmdc";
1151 reg = <0x021b0000 0x4000>;
1152 clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
1155 mmdc1: memory-controller@21b4000 { /* MMDC1 */
1156 compatible = "fsl,imx6q-mmdc";
1157 reg = <0x021b4000 0x4000>;
1158 status = "disabled";
1161 weim: weim@21b8000 {
1162 #address-cells = <2>;
1164 compatible = "fsl,imx6q-weim";
1165 reg = <0x021b8000 0x4000>;
1166 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1167 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1168 fsl,weim-cs-gpr = <&gpr>;
1169 status = "disabled";
1172 ocotp: efuse@21bc000 {
1173 compatible = "fsl,imx6q-ocotp", "syscon";
1174 reg = <0x021bc000 0x4000>;
1175 clocks = <&clks IMX6QDL_CLK_IIM>;
1176 #address-cells = <1>;
1179 cpu_speed_grade: speed-grade@10 {
1183 tempmon_calib: calib@38 {
1187 tempmon_temp_grade: temp-grade@20 {
1191 fec_mac_addr: mac-addr@88 {
1196 tzasc@21d0000 { /* TZASC1 */
1197 reg = <0x021d0000 0x4000>;
1198 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1201 tzasc@21d4000 { /* TZASC2 */
1202 reg = <0x021d4000 0x4000>;
1203 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1206 audmux: audmux@21d8000 {
1207 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1208 reg = <0x021d8000 0x4000>;
1209 status = "disabled";
1212 mipi_csi: mipi@21dc000 {
1213 compatible = "fsl,imx6-mipi-csi2";
1214 reg = <0x021dc000 0x4000>;
1215 #address-cells = <1>;
1217 interrupts = <0 100 0x04>, <0 101 0x04>;
1218 clocks = <&clks IMX6QDL_CLK_HSI_TX>,
1219 <&clks IMX6QDL_CLK_VIDEO_27M>,
1220 <&clks IMX6QDL_CLK_EIM_PODF>;
1221 clock-names = "dphy", "ref", "pix";
1222 status = "disabled";
1225 mipi_dsi: mipi@21e0000 {
1226 reg = <0x021e0000 0x4000>;
1227 status = "disabled";
1230 #address-cells = <1>;
1236 mipi_mux_0: endpoint {
1237 remote-endpoint = <&ipu1_di0_mipi>;
1244 mipi_mux_1: endpoint {
1245 remote-endpoint = <&ipu1_di1_mipi>;
1252 compatible = "fsl,imx6q-vdoa";
1253 reg = <0x021e4000 0x4000>;
1254 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1255 clocks = <&clks IMX6QDL_CLK_VDOA>;
1258 uart2: serial@21e8000 {
1259 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1260 reg = <0x021e8000 0x4000>;
1261 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1263 <&clks IMX6QDL_CLK_UART_SERIAL>;
1264 clock-names = "ipg", "per";
1265 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1266 dma-names = "rx", "tx";
1267 status = "disabled";
1270 uart3: serial@21ec000 {
1271 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1272 reg = <0x021ec000 0x4000>;
1273 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1274 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1275 <&clks IMX6QDL_CLK_UART_SERIAL>;
1276 clock-names = "ipg", "per";
1277 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1278 dma-names = "rx", "tx";
1279 status = "disabled";
1282 uart4: serial@21f0000 {
1283 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1284 reg = <0x021f0000 0x4000>;
1285 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1286 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1287 <&clks IMX6QDL_CLK_UART_SERIAL>;
1288 clock-names = "ipg", "per";
1289 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1290 dma-names = "rx", "tx";
1291 status = "disabled";
1294 uart5: serial@21f4000 {
1295 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1296 reg = <0x021f4000 0x4000>;
1297 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1298 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1299 <&clks IMX6QDL_CLK_UART_SERIAL>;
1300 clock-names = "ipg", "per";
1301 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1302 dma-names = "rx", "tx";
1303 status = "disabled";
1308 #address-cells = <1>;
1310 compatible = "fsl,imx6q-ipu";
1311 reg = <0x02400000 0x400000>;
1312 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1313 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1314 clocks = <&clks IMX6QDL_CLK_IPU1>,
1315 <&clks IMX6QDL_CLK_IPU1_DI0>,
1316 <&clks IMX6QDL_CLK_IPU1_DI1>;
1317 clock-names = "bus", "di0", "di1";
1323 ipu1_csi0_from_ipu1_csi0_mux: endpoint {
1324 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1333 #address-cells = <1>;
1337 ipu1_di0_disp0: endpoint@0 {
1341 ipu1_di0_hdmi: endpoint@1 {
1343 remote-endpoint = <&hdmi_mux_0>;
1346 ipu1_di0_mipi: endpoint@2 {
1348 remote-endpoint = <&mipi_mux_0>;
1351 ipu1_di0_lvds0: endpoint@3 {
1353 remote-endpoint = <&lvds0_mux_0>;
1356 ipu1_di0_lvds1: endpoint@4 {
1358 remote-endpoint = <&lvds1_mux_0>;
1363 #address-cells = <1>;
1367 ipu1_di1_disp1: endpoint@0 {
1371 ipu1_di1_hdmi: endpoint@1 {
1373 remote-endpoint = <&hdmi_mux_1>;
1376 ipu1_di1_mipi: endpoint@2 {
1378 remote-endpoint = <&mipi_mux_1>;
1381 ipu1_di1_lvds0: endpoint@3 {
1383 remote-endpoint = <&lvds0_mux_1>;
1386 ipu1_di1_lvds1: endpoint@4 {
1388 remote-endpoint = <&lvds1_mux_1>;