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Squashed 'dts/upstream/' content from commit aaba2d45dc2a
[thirdparty/u-boot.git] / src / arm / nxp / imx / imx6sx.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright 2014 Freescale Semiconductor, Inc.
4
5 #include <dt-bindings/clock/imx6sx-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6sx-pinfunc.h"
10
11 / {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 /*
15 * The decompressor and also some bootloaders rely on a
16 * pre-existing /chosen node to be available to insert the
17 * command line and merge other ATAGS info.
18 */
19 chosen {};
20
21 aliases {
22 can0 = &flexcan1;
23 can1 = &flexcan2;
24 ethernet0 = &fec1;
25 ethernet1 = &fec2;
26 gpio0 = &gpio1;
27 gpio1 = &gpio2;
28 gpio2 = &gpio3;
29 gpio3 = &gpio4;
30 gpio4 = &gpio5;
31 gpio5 = &gpio6;
32 gpio6 = &gpio7;
33 i2c0 = &i2c1;
34 i2c1 = &i2c2;
35 i2c2 = &i2c3;
36 i2c3 = &i2c4;
37 mmc0 = &usdhc1;
38 mmc1 = &usdhc2;
39 mmc2 = &usdhc3;
40 mmc3 = &usdhc4;
41 serial0 = &uart1;
42 serial1 = &uart2;
43 serial2 = &uart3;
44 serial3 = &uart4;
45 serial4 = &uart5;
46 serial5 = &uart6;
47 spi0 = &ecspi1;
48 spi1 = &ecspi2;
49 spi2 = &ecspi3;
50 spi3 = &ecspi4;
51 spi4 = &ecspi5;
52 usb0 = &usbotg1;
53 usb1 = &usbotg2;
54 usb2 = &usbh;
55 usbphy0 = &usbphy1;
56 usbphy1 = &usbphy2;
57 };
58
59 cpus {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 cpu0: cpu@0 {
64 compatible = "arm,cortex-a9";
65 device_type = "cpu";
66 reg = <0>;
67 next-level-cache = <&L2>;
68 operating-points = <
69 /* kHz uV */
70 996000 1250000
71 792000 1175000
72 396000 1075000
73 198000 975000
74 >;
75 fsl,soc-operating-points = <
76 /* ARM kHz SOC uV */
77 996000 1175000
78 792000 1175000
79 396000 1175000
80 198000 1175000
81 >;
82 clock-latency = <61036>; /* two CLK32 periods */
83 #cooling-cells = <2>;
84 clocks = <&clks IMX6SX_CLK_ARM>,
85 <&clks IMX6SX_CLK_PLL2_PFD2>,
86 <&clks IMX6SX_CLK_STEP>,
87 <&clks IMX6SX_CLK_PLL1_SW>,
88 <&clks IMX6SX_CLK_PLL1_SYS>;
89 clock-names = "arm", "pll2_pfd2_396m", "step",
90 "pll1_sw", "pll1_sys";
91 arm-supply = <&reg_arm>;
92 soc-supply = <&reg_soc>;
93 nvmem-cells = <&cpu_speed_grade>;
94 nvmem-cell-names = "speed_grade";
95 };
96 };
97
98 ckil: clock-ckil {
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
103 };
104
105 osc: clock-osc {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <24000000>;
109 clock-output-names = "osc";
110 };
111
112 ipp_di0: clock-ipp-di0 {
113 compatible = "fixed-clock";
114 #clock-cells = <0>;
115 clock-frequency = <0>;
116 clock-output-names = "ipp_di0";
117 };
118
119 ipp_di1: clock-ipp-di1 {
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <0>;
123 clock-output-names = "ipp_di1";
124 };
125
126 anaclk1: clock-anaclk1 {
127 compatible = "fixed-clock";
128 #clock-cells = <0>;
129 clock-frequency = <0>;
130 clock-output-names = "anaclk1";
131 };
132
133 anaclk2: clock-anaclk2 {
134 compatible = "fixed-clock";
135 #clock-cells = <0>;
136 clock-frequency = <0>;
137 clock-output-names = "anaclk2";
138 };
139
140 mqs: mqs {
141 compatible = "fsl,imx6sx-mqs";
142 gpr = <&gpr>;
143 status = "disabled";
144 };
145
146 pmu {
147 compatible = "arm,cortex-a9-pmu";
148 interrupt-parent = <&gpc>;
149 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
150 };
151
152 usbphynop1: usbphynop1 {
153 compatible = "usb-nop-xceiv";
154 #phy-cells = <0>;
155 };
156
157 soc: soc {
158 #address-cells = <1>;
159 #size-cells = <1>;
160 compatible = "simple-bus";
161 interrupt-parent = <&gpc>;
162 ranges;
163
164 ocram_s: sram@8f8000 {
165 compatible = "mmio-sram";
166 reg = <0x008f8000 0x4000>;
167 ranges = <0 0x008f8000 0x4000>;
168 #address-cells = <1>;
169 #size-cells = <1>;
170 clocks = <&clks IMX6SX_CLK_OCRAM_S>;
171 };
172
173 ocram: sram@900000 {
174 compatible = "mmio-sram";
175 reg = <0x00900000 0x20000>;
176 ranges = <0 0x00900000 0x20000>;
177 #address-cells = <1>;
178 #size-cells = <1>;
179 clocks = <&clks IMX6SX_CLK_OCRAM>;
180 };
181
182 intc: interrupt-controller@a01000 {
183 compatible = "arm,cortex-a9-gic";
184 #interrupt-cells = <3>;
185 interrupt-controller;
186 reg = <0x00a01000 0x1000>,
187 <0x00a00100 0x100>;
188 interrupt-parent = <&intc>;
189 };
190
191 L2: cache-controller@a02000 {
192 compatible = "arm,pl310-cache";
193 reg = <0x00a02000 0x1000>;
194 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
195 cache-unified;
196 cache-level = <2>;
197 arm,tag-latency = <4 2 3>;
198 arm,data-latency = <4 2 3>;
199 };
200
201 gpu: gpu@1800000 {
202 compatible = "vivante,gc";
203 reg = <0x01800000 0x4000>;
204 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&clks IMX6SX_CLK_GPU>,
206 <&clks IMX6SX_CLK_GPU>,
207 <&clks IMX6SX_CLK_GPU>;
208 clock-names = "bus", "core", "shader";
209 power-domains = <&pd_pu>;
210 };
211
212 dma_apbh: dma-controller@1804000 {
213 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
214 reg = <0x01804000 0x2000>;
215 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
219 #dma-cells = <1>;
220 dma-channels = <4>;
221 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
222 };
223
224 gpmi: nand-controller@1806000 {
225 compatible = "fsl,imx6sx-gpmi-nand";
226 #address-cells = <1>;
227 #size-cells = <1>;
228 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
229 reg-names = "gpmi-nand", "bch";
230 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
231 interrupt-names = "bch";
232 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
233 <&clks IMX6SX_CLK_GPMI_APB>,
234 <&clks IMX6SX_CLK_GPMI_BCH>,
235 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
236 <&clks IMX6SX_CLK_PER1_BCH>;
237 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
238 "gpmi_bch_apb", "per1_bch";
239 dmas = <&dma_apbh 0>;
240 dma-names = "rx-tx";
241 status = "disabled";
242 };
243
244 aips1: bus@2000000 {
245 compatible = "fsl,aips-bus", "simple-bus";
246 #address-cells = <1>;
247 #size-cells = <1>;
248 reg = <0x02000000 0x100000>;
249 ranges;
250
251 spba-bus@2000000 {
252 compatible = "fsl,spba-bus", "simple-bus";
253 #address-cells = <1>;
254 #size-cells = <1>;
255 reg = <0x02000000 0x40000>;
256 ranges;
257
258 spdif: spdif@2004000 {
259 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
260 reg = <0x02004000 0x4000>;
261 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
262 dmas = <&sdma 14 18 0>,
263 <&sdma 15 18 0>;
264 dma-names = "rx", "tx";
265 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
266 <&clks IMX6SX_CLK_OSC>,
267 <&clks IMX6SX_CLK_SPDIF>,
268 <&clks 0>, <&clks 0>, <&clks 0>,
269 <&clks IMX6SX_CLK_IPG>,
270 <&clks 0>, <&clks 0>,
271 <&clks IMX6SX_CLK_SPBA>;
272 clock-names = "core", "rxtx0",
273 "rxtx1", "rxtx2",
274 "rxtx3", "rxtx4",
275 "rxtx5", "rxtx6",
276 "rxtx7", "spba";
277 status = "disabled";
278 };
279
280 ecspi1: spi@2008000 {
281 #address-cells = <1>;
282 #size-cells = <0>;
283 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
284 reg = <0x02008000 0x4000>;
285 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&clks IMX6SX_CLK_ECSPI1>,
287 <&clks IMX6SX_CLK_ECSPI1>;
288 clock-names = "ipg", "per";
289 status = "disabled";
290 };
291
292 ecspi2: spi@200c000 {
293 #address-cells = <1>;
294 #size-cells = <0>;
295 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
296 reg = <0x0200c000 0x4000>;
297 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&clks IMX6SX_CLK_ECSPI2>,
299 <&clks IMX6SX_CLK_ECSPI2>;
300 clock-names = "ipg", "per";
301 status = "disabled";
302 };
303
304 ecspi3: spi@2010000 {
305 #address-cells = <1>;
306 #size-cells = <0>;
307 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
308 reg = <0x02010000 0x4000>;
309 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&clks IMX6SX_CLK_ECSPI3>,
311 <&clks IMX6SX_CLK_ECSPI3>;
312 clock-names = "ipg", "per";
313 status = "disabled";
314 };
315
316 ecspi4: spi@2014000 {
317 #address-cells = <1>;
318 #size-cells = <0>;
319 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
320 reg = <0x02014000 0x4000>;
321 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&clks IMX6SX_CLK_ECSPI4>,
323 <&clks IMX6SX_CLK_ECSPI4>;
324 clock-names = "ipg", "per";
325 status = "disabled";
326 };
327
328 uart1: serial@2020000 {
329 compatible = "fsl,imx6sx-uart",
330 "fsl,imx6q-uart", "fsl,imx21-uart";
331 reg = <0x02020000 0x4000>;
332 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&clks IMX6SX_CLK_UART_IPG>,
334 <&clks IMX6SX_CLK_UART_SERIAL>;
335 clock-names = "ipg", "per";
336 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
337 dma-names = "rx", "tx";
338 status = "disabled";
339 };
340
341 esai: esai@2024000 {
342 compatible = "fsl,imx6sx-esai", "fsl,imx35-esai";
343 reg = <0x02024000 0x4000>;
344 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
346 <&clks IMX6SX_CLK_ESAI_MEM>,
347 <&clks IMX6SX_CLK_ESAI_EXTAL>,
348 <&clks IMX6SX_CLK_ESAI_IPG>,
349 <&clks IMX6SX_CLK_SPBA>;
350 clock-names = "core", "mem", "extal",
351 "fsys", "spba";
352 dmas = <&sdma 23 21 0>,
353 <&sdma 24 21 0>;
354 dma-names = "rx", "tx";
355 status = "disabled";
356 };
357
358 ssi1: ssi@2028000 {
359 #sound-dai-cells = <0>;
360 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
361 reg = <0x02028000 0x4000>;
362 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
364 <&clks IMX6SX_CLK_SSI1>;
365 clock-names = "ipg", "baud";
366 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
367 dma-names = "rx", "tx";
368 fsl,fifo-depth = <15>;
369 status = "disabled";
370 };
371
372 ssi2: ssi@202c000 {
373 #sound-dai-cells = <0>;
374 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
375 reg = <0x0202c000 0x4000>;
376 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
378 <&clks IMX6SX_CLK_SSI2>;
379 clock-names = "ipg", "baud";
380 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
381 dma-names = "rx", "tx";
382 fsl,fifo-depth = <15>;
383 status = "disabled";
384 };
385
386 ssi3: ssi@2030000 {
387 #sound-dai-cells = <0>;
388 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
389 reg = <0x02030000 0x4000>;
390 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
392 <&clks IMX6SX_CLK_SSI3>;
393 clock-names = "ipg", "baud";
394 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
395 dma-names = "rx", "tx";
396 fsl,fifo-depth = <15>;
397 status = "disabled";
398 };
399
400 asrc: asrc@2034000 {
401 compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
402 reg = <0x02034000 0x4000>;
403 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
405 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
406 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
407 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
408 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
409 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
410 <&clks IMX6SX_CLK_SPBA>;
411 clock-names = "mem", "ipg", "asrck_0",
412 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
413 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
414 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
415 "asrck_d", "asrck_e", "asrck_f", "spba";
416 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>,
417 <&sdma 19 23 1>, <&sdma 20 23 1>,
418 <&sdma 21 23 1>, <&sdma 22 23 1>;
419 dma-names = "rxa", "rxb", "rxc",
420 "txa", "txb", "txc";
421 fsl,asrc-rate = <48000>;
422 fsl,asrc-width = <16>;
423 status = "okay";
424 };
425 };
426
427 pwm1: pwm@2080000 {
428 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
429 reg = <0x02080000 0x4000>;
430 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&clks IMX6SX_CLK_PWM1>,
432 <&clks IMX6SX_CLK_PWM1>;
433 clock-names = "ipg", "per";
434 #pwm-cells = <3>;
435 };
436
437 pwm2: pwm@2084000 {
438 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
439 reg = <0x02084000 0x4000>;
440 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&clks IMX6SX_CLK_PWM2>,
442 <&clks IMX6SX_CLK_PWM2>;
443 clock-names = "ipg", "per";
444 #pwm-cells = <3>;
445 };
446
447 pwm3: pwm@2088000 {
448 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
449 reg = <0x02088000 0x4000>;
450 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&clks IMX6SX_CLK_PWM3>,
452 <&clks IMX6SX_CLK_PWM3>;
453 clock-names = "ipg", "per";
454 #pwm-cells = <3>;
455 };
456
457 pwm4: pwm@208c000 {
458 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
459 reg = <0x0208c000 0x4000>;
460 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&clks IMX6SX_CLK_PWM4>,
462 <&clks IMX6SX_CLK_PWM4>;
463 clock-names = "ipg", "per";
464 #pwm-cells = <3>;
465 };
466
467 flexcan1: can@2090000 {
468 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
469 reg = <0x02090000 0x4000>;
470 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
472 <&clks IMX6SX_CLK_CAN1_SERIAL>;
473 clock-names = "ipg", "per";
474 fsl,stop-mode = <&gpr 0x10 1>;
475 status = "disabled";
476 };
477
478 flexcan2: can@2094000 {
479 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
480 reg = <0x02094000 0x4000>;
481 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
483 <&clks IMX6SX_CLK_CAN2_SERIAL>;
484 clock-names = "ipg", "per";
485 fsl,stop-mode = <&gpr 0x10 2>;
486 status = "disabled";
487 };
488
489 gpt: timer@2098000 {
490 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
491 reg = <0x02098000 0x4000>;
492 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
494 <&clks IMX6SX_CLK_GPT_3M>;
495 clock-names = "ipg", "per";
496 };
497
498 gpio1: gpio@209c000 {
499 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
500 reg = <0x0209c000 0x4000>;
501 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
503 gpio-controller;
504 #gpio-cells = <2>;
505 interrupt-controller;
506 #interrupt-cells = <2>;
507 gpio-ranges = <&iomuxc 0 5 26>;
508 };
509
510 gpio2: gpio@20a0000 {
511 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
512 reg = <0x020a0000 0x4000>;
513 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
515 gpio-controller;
516 #gpio-cells = <2>;
517 interrupt-controller;
518 #interrupt-cells = <2>;
519 gpio-ranges = <&iomuxc 0 31 20>;
520 };
521
522 gpio3: gpio@20a4000 {
523 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
524 reg = <0x020a4000 0x4000>;
525 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
527 gpio-controller;
528 #gpio-cells = <2>;
529 interrupt-controller;
530 #interrupt-cells = <2>;
531 gpio-ranges = <&iomuxc 0 51 29>;
532 };
533
534 gpio4: gpio@20a8000 {
535 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
536 reg = <0x020a8000 0x4000>;
537 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
539 gpio-controller;
540 #gpio-cells = <2>;
541 interrupt-controller;
542 #interrupt-cells = <2>;
543 gpio-ranges = <&iomuxc 0 80 32>;
544 };
545
546 gpio5: gpio@20ac000 {
547 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
548 reg = <0x020ac000 0x4000>;
549 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
551 gpio-controller;
552 #gpio-cells = <2>;
553 interrupt-controller;
554 #interrupt-cells = <2>;
555 gpio-ranges = <&iomuxc 0 112 24>;
556 };
557
558 gpio6: gpio@20b0000 {
559 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
560 reg = <0x020b0000 0x4000>;
561 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
563 gpio-controller;
564 #gpio-cells = <2>;
565 interrupt-controller;
566 #interrupt-cells = <2>;
567 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
568 };
569
570 gpio7: gpio@20b4000 {
571 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
572 reg = <0x020b4000 0x4000>;
573 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
575 gpio-controller;
576 #gpio-cells = <2>;
577 interrupt-controller;
578 #interrupt-cells = <2>;
579 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
580 };
581
582 kpp: keypad@20b8000 {
583 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
584 reg = <0x020b8000 0x4000>;
585 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&clks IMX6SX_CLK_IPG>;
587 status = "disabled";
588 };
589
590 wdog1: watchdog@20bc000 {
591 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
592 reg = <0x020bc000 0x4000>;
593 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&clks IMX6SX_CLK_IPG>;
595 };
596
597 wdog2: watchdog@20c0000 {
598 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
599 reg = <0x020c0000 0x4000>;
600 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&clks IMX6SX_CLK_IPG>;
602 status = "disabled";
603 };
604
605 clks: clock-controller@20c4000 {
606 compatible = "fsl,imx6sx-ccm";
607 reg = <0x020c4000 0x4000>;
608 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
610 #clock-cells = <1>;
611 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
612 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
613 };
614
615 anatop: anatop@20c8000 {
616 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
617 "syscon", "simple-mfd";
618 reg = <0x020c8000 0x1000>;
619 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
622
623 reg_vdd1p1: regulator-1p1 {
624 compatible = "fsl,anatop-regulator";
625 regulator-name = "vdd1p1";
626 regulator-min-microvolt = <1000000>;
627 regulator-max-microvolt = <1200000>;
628 regulator-always-on;
629 anatop-reg-offset = <0x110>;
630 anatop-vol-bit-shift = <8>;
631 anatop-vol-bit-width = <5>;
632 anatop-min-bit-val = <4>;
633 anatop-min-voltage = <800000>;
634 anatop-max-voltage = <1375000>;
635 anatop-enable-bit = <0>;
636 };
637
638 reg_vdd3p0: regulator-3p0 {
639 compatible = "fsl,anatop-regulator";
640 regulator-name = "vdd3p0";
641 regulator-min-microvolt = <2800000>;
642 regulator-max-microvolt = <3150000>;
643 regulator-always-on;
644 anatop-reg-offset = <0x120>;
645 anatop-vol-bit-shift = <8>;
646 anatop-vol-bit-width = <5>;
647 anatop-min-bit-val = <0>;
648 anatop-min-voltage = <2625000>;
649 anatop-max-voltage = <3400000>;
650 anatop-enable-bit = <0>;
651 };
652
653 reg_vdd2p5: regulator-2p5 {
654 compatible = "fsl,anatop-regulator";
655 regulator-name = "vdd2p5";
656 regulator-min-microvolt = <2250000>;
657 regulator-max-microvolt = <2750000>;
658 regulator-always-on;
659 anatop-reg-offset = <0x130>;
660 anatop-vol-bit-shift = <8>;
661 anatop-vol-bit-width = <5>;
662 anatop-min-bit-val = <0>;
663 anatop-min-voltage = <2100000>;
664 anatop-max-voltage = <2875000>;
665 anatop-enable-bit = <0>;
666 };
667
668 reg_arm: regulator-vddcore {
669 compatible = "fsl,anatop-regulator";
670 regulator-name = "vddarm";
671 regulator-min-microvolt = <725000>;
672 regulator-max-microvolt = <1450000>;
673 regulator-always-on;
674 anatop-reg-offset = <0x140>;
675 anatop-vol-bit-shift = <0>;
676 anatop-vol-bit-width = <5>;
677 anatop-delay-reg-offset = <0x170>;
678 anatop-delay-bit-shift = <24>;
679 anatop-delay-bit-width = <2>;
680 anatop-min-bit-val = <1>;
681 anatop-min-voltage = <725000>;
682 anatop-max-voltage = <1450000>;
683 };
684
685 reg_pcie: regulator-vddpcie {
686 compatible = "fsl,anatop-regulator";
687 regulator-name = "vddpcie";
688 regulator-min-microvolt = <725000>;
689 regulator-max-microvolt = <1450000>;
690 anatop-reg-offset = <0x140>;
691 anatop-vol-bit-shift = <9>;
692 anatop-vol-bit-width = <5>;
693 anatop-delay-reg-offset = <0x170>;
694 anatop-delay-bit-shift = <26>;
695 anatop-delay-bit-width = <2>;
696 anatop-min-bit-val = <1>;
697 anatop-min-voltage = <725000>;
698 anatop-max-voltage = <1450000>;
699 };
700
701 reg_soc: regulator-vddsoc {
702 compatible = "fsl,anatop-regulator";
703 regulator-name = "vddsoc";
704 regulator-min-microvolt = <725000>;
705 regulator-max-microvolt = <1450000>;
706 regulator-always-on;
707 anatop-reg-offset = <0x140>;
708 anatop-vol-bit-shift = <18>;
709 anatop-vol-bit-width = <5>;
710 anatop-delay-reg-offset = <0x170>;
711 anatop-delay-bit-shift = <28>;
712 anatop-delay-bit-width = <2>;
713 anatop-min-bit-val = <1>;
714 anatop-min-voltage = <725000>;
715 anatop-max-voltage = <1450000>;
716 };
717
718 tempmon: tempmon {
719 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
720 interrupt-parent = <&gpc>;
721 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
722 fsl,tempmon = <&anatop>;
723 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
724 nvmem-cell-names = "calib", "temp_grade";
725 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
726 };
727 };
728
729 usbphy1: usbphy@20c9000 {
730 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
731 reg = <0x020c9000 0x1000>;
732 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&clks IMX6SX_CLK_USBPHY1>;
734 fsl,anatop = <&anatop>;
735 };
736
737 usbphy2: usbphy@20ca000 {
738 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
739 reg = <0x020ca000 0x1000>;
740 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&clks IMX6SX_CLK_USBPHY2>;
742 fsl,anatop = <&anatop>;
743 };
744
745 snvs: snvs@20cc000 {
746 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
747 reg = <0x020cc000 0x4000>;
748
749 snvs_rtc: snvs-rtc-lp {
750 compatible = "fsl,sec-v4.0-mon-rtc-lp";
751 regmap = <&snvs>;
752 offset = <0x34>;
753 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
754 };
755
756 snvs_poweroff: snvs-poweroff {
757 compatible = "syscon-poweroff";
758 regmap = <&snvs>;
759 offset = <0x38>;
760 value = <0x60>;
761 mask = <0x60>;
762 status = "disabled";
763 };
764
765 snvs_pwrkey: snvs-powerkey {
766 compatible = "fsl,sec-v4.0-pwrkey";
767 regmap = <&snvs>;
768 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
769 linux,keycode = <KEY_POWER>;
770 wakeup-source;
771 status = "disabled";
772 };
773 };
774
775 epit1: epit@20d0000 {
776 reg = <0x020d0000 0x4000>;
777 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
778 };
779
780 epit2: epit@20d4000 {
781 reg = <0x020d4000 0x4000>;
782 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
783 };
784
785 src: reset-controller@20d8000 {
786 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
787 reg = <0x020d8000 0x4000>;
788 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
790 #reset-cells = <1>;
791 };
792
793 gpc: gpc@20dc000 {
794 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
795 reg = <0x020dc000 0x4000>;
796 interrupt-controller;
797 #interrupt-cells = <3>;
798 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
799 interrupt-parent = <&intc>;
800 clocks = <&clks IMX6SX_CLK_IPG>;
801 clock-names = "ipg";
802
803 pgc {
804 #address-cells = <1>;
805 #size-cells = <0>;
806
807 power-domain@0 {
808 reg = <0>;
809 #power-domain-cells = <0>;
810 };
811
812 pd_pu: power-domain@1 {
813 reg = <1>;
814 #power-domain-cells = <0>;
815 power-supply = <&reg_soc>;
816 clocks = <&clks IMX6SX_CLK_GPU>;
817 };
818
819 pd_disp: power-domain@2 {
820 reg = <2>;
821 #power-domain-cells = <0>;
822 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
823 <&clks IMX6SX_CLK_DISPLAY_AXI>,
824 <&clks IMX6SX_CLK_LCDIF1_PIX>,
825 <&clks IMX6SX_CLK_LCDIF_APB>,
826 <&clks IMX6SX_CLK_LCDIF2_PIX>,
827 <&clks IMX6SX_CLK_CSI>,
828 <&clks IMX6SX_CLK_VADC>;
829 };
830
831 pd_pci: power-domain@3 {
832 reg = <3>;
833 #power-domain-cells = <0>;
834 power-supply = <&reg_pcie>;
835 };
836 };
837 };
838
839 iomuxc: pinctrl@20e0000 {
840 compatible = "fsl,imx6sx-iomuxc";
841 reg = <0x020e0000 0x4000>;
842 };
843
844 gpr: syscon@20e4000 {
845 compatible = "fsl,imx6sx-iomuxc-gpr",
846 "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
847 #address-cells = <1>;
848 #size-cells = <1>;
849 reg = <0x020e4000 0x4000>;
850
851 lvds_bridge: bridge@18 {
852 compatible = "fsl,imx6sx-ldb";
853 reg = <0x18 0x4>;
854 clocks = <&clks IMX6SX_CLK_LDB_DI0>;
855 clock-names = "ldb";
856 status = "disabled";
857
858 ports {
859 #address-cells = <1>;
860 #size-cells = <0>;
861
862 port@0 {
863 reg = <0>;
864
865 ldb_from_lcdif1: endpoint {
866 };
867 };
868
869 port@1 {
870 reg = <1>;
871
872 ldb_lvds_ch0: endpoint {
873 };
874 };
875 };
876 };
877 };
878
879 sdma: dma-controller@20ec000 {
880 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
881 reg = <0x020ec000 0x4000>;
882 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
883 clocks = <&clks IMX6SX_CLK_IPG>,
884 <&clks IMX6SX_CLK_SDMA>;
885 clock-names = "ipg", "ahb";
886 #dma-cells = <3>;
887 /* imx6sx reuses imx6q sdma firmware */
888 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
889 };
890 };
891
892 aips2: bus@2100000 {
893 compatible = "fsl,aips-bus", "simple-bus";
894 #address-cells = <1>;
895 #size-cells = <1>;
896 reg = <0x02100000 0x100000>;
897 ranges;
898
899 crypto: crypto@2100000 {
900 compatible = "fsl,sec-v4.0";
901 #address-cells = <1>;
902 #size-cells = <1>;
903 reg = <0x2100000 0x10000>;
904 ranges = <0 0x2100000 0x10000>;
905 interrupt-parent = <&intc>;
906 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
907 <&clks IMX6SX_CLK_CAAM_ACLK>,
908 <&clks IMX6SX_CLK_CAAM_IPG>,
909 <&clks IMX6SX_CLK_EIM_SLOW>;
910 clock-names = "mem", "aclk", "ipg", "emi_slow";
911
912 sec_jr0: jr@1000 {
913 compatible = "fsl,sec-v4.0-job-ring";
914 reg = <0x1000 0x1000>;
915 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
916 };
917
918 sec_jr1: jr@2000 {
919 compatible = "fsl,sec-v4.0-job-ring";
920 reg = <0x2000 0x1000>;
921 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
922 };
923 };
924
925 usbotg1: usb@2184000 {
926 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
927 reg = <0x02184000 0x200>;
928 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&clks IMX6SX_CLK_USBOH3>;
930 fsl,usbphy = <&usbphy1>;
931 fsl,usbmisc = <&usbmisc 0>;
932 fsl,anatop = <&anatop>;
933 ahb-burst-config = <0x0>;
934 tx-burst-size-dword = <0x10>;
935 rx-burst-size-dword = <0x10>;
936 status = "disabled";
937 };
938
939 usbotg2: usb@2184200 {
940 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
941 reg = <0x02184200 0x200>;
942 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
943 clocks = <&clks IMX6SX_CLK_USBOH3>;
944 fsl,usbphy = <&usbphy2>;
945 fsl,usbmisc = <&usbmisc 1>;
946 ahb-burst-config = <0x0>;
947 tx-burst-size-dword = <0x10>;
948 rx-burst-size-dword = <0x10>;
949 status = "disabled";
950 };
951
952 usbh: usb@2184400 {
953 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
954 reg = <0x02184400 0x200>;
955 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&clks IMX6SX_CLK_USBOH3>;
957 fsl,usbphy = <&usbphynop1>;
958 fsl,usbmisc = <&usbmisc 2>;
959 phy_type = "hsic";
960 fsl,anatop = <&anatop>;
961 dr_mode = "host";
962 ahb-burst-config = <0x0>;
963 tx-burst-size-dword = <0x10>;
964 rx-burst-size-dword = <0x10>;
965 status = "disabled";
966 };
967
968 usbmisc: usbmisc@2184800 {
969 #index-cells = <1>;
970 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
971 reg = <0x02184800 0x200>;
972 clocks = <&clks IMX6SX_CLK_USBOH3>;
973 };
974
975 fec1: ethernet@2188000 {
976 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
977 reg = <0x02188000 0x4000>;
978 interrupt-names = "int0", "pps";
979 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&clks IMX6SX_CLK_ENET>,
982 <&clks IMX6SX_CLK_ENET_AHB>,
983 <&clks IMX6SX_CLK_ENET_PTP>,
984 <&clks IMX6SX_CLK_ENET_REF>,
985 <&clks IMX6SX_CLK_ENET_PTP>;
986 clock-names = "ipg", "ahb", "ptp",
987 "enet_clk_ref", "enet_out";
988 fsl,num-tx-queues = <3>;
989 fsl,num-rx-queues = <3>;
990 fsl,stop-mode = <&gpr 0x10 3>;
991 status = "disabled";
992 };
993
994 mlb: mlb@218c000 {
995 reg = <0x0218c000 0x4000>;
996 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
999 clocks = <&clks IMX6SX_CLK_MLB>;
1000 status = "disabled";
1001 };
1002
1003 usdhc1: mmc@2190000 {
1004 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1005 reg = <0x02190000 0x4000>;
1006 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1007 clocks = <&clks IMX6SX_CLK_USDHC1>,
1008 <&clks IMX6SX_CLK_USDHC1>,
1009 <&clks IMX6SX_CLK_USDHC1>;
1010 clock-names = "ipg", "ahb", "per";
1011 bus-width = <4>;
1012 fsl,tuning-start-tap = <20>;
1013 fsl,tuning-step= <2>;
1014 status = "disabled";
1015 };
1016
1017 usdhc2: mmc@2194000 {
1018 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1019 reg = <0x02194000 0x4000>;
1020 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&clks IMX6SX_CLK_USDHC2>,
1022 <&clks IMX6SX_CLK_USDHC2>,
1023 <&clks IMX6SX_CLK_USDHC2>;
1024 clock-names = "ipg", "ahb", "per";
1025 bus-width = <4>;
1026 fsl,tuning-start-tap = <20>;
1027 fsl,tuning-step= <2>;
1028 status = "disabled";
1029 };
1030
1031 usdhc3: mmc@2198000 {
1032 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1033 reg = <0x02198000 0x4000>;
1034 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1035 clocks = <&clks IMX6SX_CLK_USDHC3>,
1036 <&clks IMX6SX_CLK_USDHC3>,
1037 <&clks IMX6SX_CLK_USDHC3>;
1038 clock-names = "ipg", "ahb", "per";
1039 bus-width = <4>;
1040 fsl,tuning-start-tap = <20>;
1041 fsl,tuning-step= <2>;
1042 status = "disabled";
1043 };
1044
1045 usdhc4: mmc@219c000 {
1046 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1047 reg = <0x0219c000 0x4000>;
1048 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1049 clocks = <&clks IMX6SX_CLK_USDHC4>,
1050 <&clks IMX6SX_CLK_USDHC4>,
1051 <&clks IMX6SX_CLK_USDHC4>;
1052 clock-names = "ipg", "ahb", "per";
1053 bus-width = <4>;
1054 status = "disabled";
1055 };
1056
1057 i2c1: i2c@21a0000 {
1058 #address-cells = <1>;
1059 #size-cells = <0>;
1060 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1061 reg = <0x021a0000 0x4000>;
1062 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1063 clocks = <&clks IMX6SX_CLK_I2C1>;
1064 status = "disabled";
1065 };
1066
1067 i2c2: i2c@21a4000 {
1068 #address-cells = <1>;
1069 #size-cells = <0>;
1070 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1071 reg = <0x021a4000 0x4000>;
1072 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&clks IMX6SX_CLK_I2C2>;
1074 status = "disabled";
1075 };
1076
1077 i2c3: i2c@21a8000 {
1078 #address-cells = <1>;
1079 #size-cells = <0>;
1080 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1081 reg = <0x021a8000 0x4000>;
1082 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1083 clocks = <&clks IMX6SX_CLK_I2C3>;
1084 status = "disabled";
1085 };
1086
1087 memory-controller@21b0000 {
1088 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1089 reg = <0x021b0000 0x4000>;
1090 clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;
1091 };
1092
1093 fec2: ethernet@21b4000 {
1094 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1095 reg = <0x021b4000 0x4000>;
1096 interrupt-names = "int0", "pps";
1097 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1098 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1099 clocks = <&clks IMX6SX_CLK_ENET>,
1100 <&clks IMX6SX_CLK_ENET_AHB>,
1101 <&clks IMX6SX_CLK_ENET_PTP>,
1102 <&clks IMX6SX_CLK_ENET2_REF_125M>,
1103 <&clks IMX6SX_CLK_ENET_PTP>;
1104 clock-names = "ipg", "ahb", "ptp",
1105 "enet_clk_ref", "enet_out";
1106 fsl,stop-mode = <&gpr 0x10 4>;
1107 status = "disabled";
1108 };
1109
1110 weim: weim@21b8000 {
1111 #address-cells = <2>;
1112 #size-cells = <1>;
1113 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1114 reg = <0x021b8000 0x4000>;
1115 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1116 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1117 fsl,weim-cs-gpr = <&gpr>;
1118 status = "disabled";
1119 };
1120
1121 ocotp: efuse@21bc000 {
1122 #address-cells = <1>;
1123 #size-cells = <1>;
1124 compatible = "fsl,imx6sx-ocotp", "syscon";
1125 reg = <0x021bc000 0x4000>;
1126 clocks = <&clks IMX6SX_CLK_OCOTP>;
1127
1128 cpu_speed_grade: speed-grade@10 {
1129 reg = <0x10 4>;
1130 };
1131
1132 tempmon_calib: calib@38 {
1133 reg = <0x38 4>;
1134 };
1135
1136 tempmon_temp_grade: temp-grade@20 {
1137 reg = <0x20 4>;
1138 };
1139 };
1140
1141 sai1: sai@21d4000 {
1142 compatible = "fsl,imx6sx-sai";
1143 reg = <0x021d4000 0x4000>;
1144 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1145 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1146 <&clks IMX6SX_CLK_SAI1>,
1147 <&clks 0>, <&clks 0>;
1148 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1149 dma-names = "rx", "tx";
1150 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1151 status = "disabled";
1152 };
1153
1154 audmux: audmux@21d8000 {
1155 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1156 reg = <0x021d8000 0x4000>;
1157 status = "disabled";
1158 };
1159
1160 sai2: sai@21dc000 {
1161 compatible = "fsl,imx6sx-sai";
1162 reg = <0x021dc000 0x4000>;
1163 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1164 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1165 <&clks IMX6SX_CLK_SAI2>,
1166 <&clks 0>, <&clks 0>;
1167 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1168 dma-names = "rx", "tx";
1169 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1170 status = "disabled";
1171 };
1172
1173 qspi1: spi@21e0000 {
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1176 compatible = "fsl,imx6sx-qspi";
1177 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1178 reg-names = "QuadSPI", "QuadSPI-memory";
1179 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1180 clocks = <&clks IMX6SX_CLK_QSPI1>,
1181 <&clks IMX6SX_CLK_QSPI1>;
1182 clock-names = "qspi_en", "qspi";
1183 status = "disabled";
1184 };
1185
1186 qspi2: spi@21e4000 {
1187 #address-cells = <1>;
1188 #size-cells = <0>;
1189 compatible = "fsl,imx6sx-qspi";
1190 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1191 reg-names = "QuadSPI", "QuadSPI-memory";
1192 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&clks IMX6SX_CLK_QSPI2>,
1194 <&clks IMX6SX_CLK_QSPI2>;
1195 clock-names = "qspi_en", "qspi";
1196 status = "disabled";
1197 };
1198
1199 uart2: serial@21e8000 {
1200 compatible = "fsl,imx6sx-uart",
1201 "fsl,imx6q-uart", "fsl,imx21-uart";
1202 reg = <0x021e8000 0x4000>;
1203 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1204 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1205 <&clks IMX6SX_CLK_UART_SERIAL>;
1206 clock-names = "ipg", "per";
1207 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1208 dma-names = "rx", "tx";
1209 status = "disabled";
1210 };
1211
1212 uart3: serial@21ec000 {
1213 compatible = "fsl,imx6sx-uart",
1214 "fsl,imx6q-uart", "fsl,imx21-uart";
1215 reg = <0x021ec000 0x4000>;
1216 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1217 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1218 <&clks IMX6SX_CLK_UART_SERIAL>;
1219 clock-names = "ipg", "per";
1220 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1221 dma-names = "rx", "tx";
1222 status = "disabled";
1223 };
1224
1225 uart4: serial@21f0000 {
1226 compatible = "fsl,imx6sx-uart",
1227 "fsl,imx6q-uart", "fsl,imx21-uart";
1228 reg = <0x021f0000 0x4000>;
1229 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1230 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1231 <&clks IMX6SX_CLK_UART_SERIAL>;
1232 clock-names = "ipg", "per";
1233 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1234 dma-names = "rx", "tx";
1235 status = "disabled";
1236 };
1237
1238 uart5: serial@21f4000 {
1239 compatible = "fsl,imx6sx-uart",
1240 "fsl,imx6q-uart", "fsl,imx21-uart";
1241 reg = <0x021f4000 0x4000>;
1242 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1243 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1244 <&clks IMX6SX_CLK_UART_SERIAL>;
1245 clock-names = "ipg", "per";
1246 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1247 dma-names = "rx", "tx";
1248 status = "disabled";
1249 };
1250
1251 i2c4: i2c@21f8000 {
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1254 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1255 reg = <0x021f8000 0x4000>;
1256 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1257 clocks = <&clks IMX6SX_CLK_I2C4>;
1258 status = "disabled";
1259 };
1260 };
1261
1262 aips3: bus@2200000 {
1263 compatible = "fsl,aips-bus", "simple-bus";
1264 #address-cells = <1>;
1265 #size-cells = <1>;
1266 reg = <0x02200000 0x100000>;
1267 ranges;
1268
1269 spba-bus@2240000 {
1270 compatible = "fsl,spba-bus", "simple-bus";
1271 #address-cells = <1>;
1272 #size-cells = <1>;
1273 reg = <0x02240000 0x40000>;
1274 ranges;
1275
1276 csi1: csi@2214000 {
1277 reg = <0x02214000 0x4000>;
1278 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1279 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1280 <&clks IMX6SX_CLK_CSI>,
1281 <&clks IMX6SX_CLK_DCIC1>;
1282 clock-names = "disp-axi", "csi_mclk", "dcic";
1283 status = "disabled";
1284 };
1285
1286 pxp: pxp@2218000 {
1287 compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
1288 reg = <0x02218000 0x4000>;
1289 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1290 clocks = <&clks IMX6SX_CLK_PXP_AXI>;
1291 clock-names = "axi";
1292 power-domains = <&pd_disp>;
1293 status = "disabled";
1294 };
1295
1296 csi2: csi@221c000 {
1297 reg = <0x0221c000 0x4000>;
1298 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1299 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1300 <&clks IMX6SX_CLK_CSI>,
1301 <&clks IMX6SX_CLK_DCIC2>;
1302 clock-names = "disp-axi", "csi_mclk", "dcic";
1303 status = "disabled";
1304 };
1305
1306 lcdif1: lcdif@2220000 {
1307 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1308 reg = <0x02220000 0x4000>;
1309 interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1310 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1311 <&clks IMX6SX_CLK_LCDIF_APB>,
1312 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1313 clock-names = "pix", "axi", "disp_axi";
1314 assigned-clocks = <&clks IMX6SX_CLK_LCDIF1_PRE_SEL>,
1315 <&clks IMX6SX_CLK_LCDIF1_SEL>;
1316 assigned-clock-parents = <&clks IMX6SX_CLK_PLL5_VIDEO_DIV>,
1317 <&clks IMX6SX_CLK_LCDIF1_PODF>;
1318 power-domains = <&pd_disp>;
1319 status = "disabled";
1320
1321 port {
1322 lcdif1_to_ldb: endpoint {
1323 };
1324 };
1325 };
1326
1327 lcdif2: lcdif@2224000 {
1328 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1329 reg = <0x02224000 0x4000>;
1330 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1331 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1332 <&clks IMX6SX_CLK_LCDIF_APB>,
1333 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1334 clock-names = "pix", "axi", "disp_axi";
1335 power-domains = <&pd_disp>;
1336 status = "disabled";
1337 };
1338
1339 vadc: vadc@2228000 {
1340 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1341 reg-names = "vadc-vafe", "vadc-vdec";
1342 clocks = <&clks IMX6SX_CLK_VADC>,
1343 <&clks IMX6SX_CLK_CSI>;
1344 clock-names = "vadc", "csi";
1345 power-domains = <&pd_disp>;
1346 status = "disabled";
1347 };
1348 };
1349
1350 adc1: adc@2280000 {
1351 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1352 reg = <0x02280000 0x4000>;
1353 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1354 clocks = <&clks IMX6SX_CLK_IPG>;
1355 clock-names = "adc";
1356 fsl,adck-max-frequency = <30000000>, <40000000>,
1357 <20000000>;
1358 status = "disabled";
1359 };
1360
1361 adc2: adc@2284000 {
1362 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1363 reg = <0x02284000 0x4000>;
1364 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1365 clocks = <&clks IMX6SX_CLK_IPG>;
1366 clock-names = "adc";
1367 fsl,adck-max-frequency = <30000000>, <40000000>,
1368 <20000000>;
1369 status = "disabled";
1370 };
1371
1372 wdog3: watchdog@2288000 {
1373 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1374 reg = <0x02288000 0x4000>;
1375 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1376 clocks = <&clks IMX6SX_CLK_IPG>;
1377 status = "disabled";
1378 };
1379
1380 ecspi5: spi@228c000 {
1381 #address-cells = <1>;
1382 #size-cells = <0>;
1383 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1384 reg = <0x0228c000 0x4000>;
1385 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1386 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1387 <&clks IMX6SX_CLK_ECSPI5>;
1388 clock-names = "ipg", "per";
1389 status = "disabled";
1390 };
1391
1392 uart6: serial@22a0000 {
1393 compatible = "fsl,imx6sx-uart",
1394 "fsl,imx6q-uart", "fsl,imx21-uart";
1395 reg = <0x022a0000 0x4000>;
1396 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1398 <&clks IMX6SX_CLK_UART_SERIAL>;
1399 clock-names = "ipg", "per";
1400 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1401 dma-names = "rx", "tx";
1402 status = "disabled";
1403 };
1404
1405 pwm5: pwm@22a4000 {
1406 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1407 reg = <0x022a4000 0x4000>;
1408 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1409 clocks = <&clks IMX6SX_CLK_PWM5>,
1410 <&clks IMX6SX_CLK_PWM5>;
1411 clock-names = "ipg", "per";
1412 #pwm-cells = <3>;
1413 };
1414
1415 pwm6: pwm@22a8000 {
1416 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1417 reg = <0x022a8000 0x4000>;
1418 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1419 clocks = <&clks IMX6SX_CLK_PWM6>,
1420 <&clks IMX6SX_CLK_PWM6>;
1421 clock-names = "ipg", "per";
1422 #pwm-cells = <3>;
1423 };
1424
1425 pwm7: pwm@22ac000 {
1426 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1427 reg = <0x022ac000 0x4000>;
1428 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1429 clocks = <&clks IMX6SX_CLK_PWM7>,
1430 <&clks IMX6SX_CLK_PWM7>;
1431 clock-names = "ipg", "per";
1432 #pwm-cells = <3>;
1433 };
1434
1435 pwm8: pwm@22b0000 {
1436 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1437 reg = <0x022b0000 0x4000>;
1438 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1439 clocks = <&clks IMX6SX_CLK_PWM8>,
1440 <&clks IMX6SX_CLK_PWM8>;
1441 clock-names = "ipg", "per";
1442 #pwm-cells = <3>;
1443 };
1444 };
1445
1446 pcie: pcie@8ffc000 {
1447 compatible = "fsl,imx6sx-pcie";
1448 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1449 reg-names = "dbi", "config";
1450 #address-cells = <3>;
1451 #size-cells = <2>;
1452 device_type = "pci";
1453 bus-range = <0x00 0xff>;
1454 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000>, /* downstream I/O */
1455 <0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1456 num-lanes = <1>;
1457 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1458 interrupt-names = "msi";
1459 #interrupt-cells = <1>;
1460 interrupt-map-mask = <0 0 0 0x7>;
1461 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1462 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1463 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1464 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1465 clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
1466 <&clks IMX6SX_CLK_LVDS1_OUT>,
1467 <&clks IMX6SX_CLK_PCIE_REF_125M>,
1468 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1469 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1470 power-domains = <&pd_disp>, <&pd_pci>;
1471 power-domain-names = "pcie", "pcie_phy";
1472 status = "disabled";
1473 };
1474 };
1475 };
"Das U-Boot" Source Tree