src/arm/nxp/imx/imx6ul-prti6g.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /*
   3  * Copyright (c) 2016 Protonic Holland
   4  * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
   5  */
   6
   7 /dts-v1/;
   8 #include "imx6ul.dtsi"
   9 #include <dt-bindings/gpio/gpio.h>
  10
  11 / {
  12         model = "Protonic PRTI6G Board";
  13         compatible = "prt,prti6g", "fsl,imx6ul";
  14
  15         chosen {
  16                 stdout-path = &uart1;
  17         };
  18
  19         clock_ksz8081_in: clock-ksz8081-in {
  20                 compatible = "fixed-clock";
  21                 #clock-cells = <0>;
  22                 clock-frequency = <25000000>;
  23         };
  24
  25         clock_ksz8081_out: clock-ksz8081-out {
  26                 compatible = "fixed-clock";
  27                 #clock-cells = <0>;
  28                 clock-frequency = <50000000>;
  29                 clock-output-names = "enet1_ref_pad";
  30         };
  31
  32         leds {
  33                 compatible = "gpio-leds";
  34                 pinctrl-names = "default";
  35                 pinctrl-0 = <&pinctrl_leds>;
  36
  37                 led-0 {
  38                         label = "debug0";
  39                         gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
  40                         linux,default-trigger = "heartbeat";
  41                 };
  42         };
  43
  44         reg_3v2: regulator-3v2 {
  45                 compatible = "regulator-fixed";
  46                 regulator-name = "3v2";
  47                 regulator-min-microvolt = <3200000>;
  48                 regulator-max-microvolt = <3200000>;
  49         };
  50 };
  51
  52 &can1 {
  53         pinctrl-names = "default";
  54         pinctrl-0 = <&pinctrl_can1>;
  55         status = "okay";
  56 };
  57
  58 &can2 {
  59         pinctrl-names = "default";
  60         pinctrl-0 = <&pinctrl_can2>;
  61         status = "okay";
  62 };
  63
  64 &clks {
  65         clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&clock_ksz8081_out>;
  66         clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "enet1_ref_pad";
  67         assigned-clocks = <&clks IMX6UL_CLK_ENET1_REF_SEL>;
  68         assigned-clock-parents = <&clock_ksz8081_out>;
  69 };
  70
  71 &ecspi1 {
  72         cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
  73         pinctrl-names = "default";
  74         pinctrl-0 = <&pinctrl_ecspi1>;
  75         status = "okay";
  76
  77         flash@0 {
  78                 compatible = "jedec,spi-nor";
  79                 reg = <0>;
  80                 spi-max-frequency = <20000000>;
  81         };
  82 };
  83
  84 &ecspi2 {
  85         cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
  86         pinctrl-names = "default";
  87         pinctrl-0 = <&pinctrl_ecspi2>;
  88         status = "okay";
  89 };
  90
  91 &fec1 {
  92         pinctrl-names = "default";
  93         pinctrl-0 = <&pinctrl_eth1>;
  94         phy-mode = "rmii";
  95         phy-handle = <&rmii_phy>;
  96         status = "okay";
  97
  98         mdio {
  99                 #address-cells = <1>;
 100                 #size-cells = <0>;
 101
 102                 /* Microchip KSZ8081RNA PHY */
 103                 rmii_phy: ethernet-phy@0 {
 104                         reg = <0>;
 105                         interrupts-extended = <&gpio5 1 IRQ_TYPE_LEVEL_LOW>;
 106                         reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 107                         reset-assert-us = <10000>;
 108                         reset-deassert-us = <300>;
 109                         clocks = <&clock_ksz8081_in>;
 110                         clock-names = "rmii-ref";
 111                 };
 112         };
 113 };
 114
 115 &i2c1 {
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&pinctrl_i2c1>;
 118         clock-frequency = <100000>;
 119         status = "okay";
 120
 121         /* additional i2c devices are added automatically by the boot loader */
 122 };
 123
 124 &i2c2 {
 125         pinctrl-names = "default";
 126         pinctrl-0 = <&pinctrl_i2c2>;
 127         clock-frequency = <100000>;
 128         status = "okay";
 129
 130         adc@49 {
 131                 compatible = "ti,ads1015";
 132                 reg = <0x49>;
 133                 #address-cells = <1>;
 134                 #size-cells = <0>;
 135
 136                 channel@4 {
 137                         reg = <4>;
 138                         ti,gain = <3>;
 139                         ti,datarate = <3>;
 140                 };
 141
 142                 channel@5 {
 143                         reg = <5>;
 144                         ti,gain = <3>;
 145                         ti,datarate = <3>;
 146                 };
 147
 148                 channel@6 {
 149                         reg = <6>;
 150                         ti,gain = <3>;
 151                         ti,datarate = <3>;
 152                 };
 153
 154                 channel@7 {
 155                         reg = <7>;
 156                         ti,gain = <3>;
 157                         ti,datarate = <3>;
 158                 };
 159         };
 160
 161         rtc@51 {
 162                 compatible = "nxp,pcf8563";
 163                 reg = <0x51>;
 164         };
 165
 166         temperature-sensor@70 {
 167                 compatible = "ti,tmp103";
 168                 reg = <0x70>;
 169         };
 170 };
 171
 172 &uart1 {
 173         pinctrl-names = "default";
 174         pinctrl-0 = <&pinctrl_uart1>;
 175         status = "okay";
 176 };
 177
 178 &usbotg1 {
 179         dr_mode = "host";
 180         over-current-active-low;
 181         status = "okay";
 182 };
 183
 184 &usdhc1 {
 185         pinctrl-names = "default";
 186         pinctrl-0 = <&pinctrl_usdhc1>;
 187         cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
 188         vmmc-supply = <&reg_3v2>;
 189         no-1-8-v;
 190         disable-wp;
 191         cap-sd-highspeed;
 192         no-mmc;
 193         no-sdio;
 194         status = "okay";
 195 };
 196
 197 &usdhc2 {
 198         pinctrl-names = "default";
 199         pinctrl-0 = <&pinctrl_usdhc2>;
 200         bus-width = <8>;
 201         no-1-8-v;
 202         non-removable;
 203         no-sd;
 204         no-sdio;
 205         status = "okay";
 206 };
 207
 208 &iomuxc {
 209         pinctrl-names = "default";
 210         pinctrl-0 = <&pinctrl_hog>;
 211
 212         pinctrl_can1: can1grp {
 213                 fsl,pins = <
 214                         MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX              0x0b0b0
 215                         MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX              0x0b0b0
 216                         /* SR */
 217                         MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03              0x0b0b0
 218                         /* TERM */
 219                         MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04              0x0b0b0
 220                         /* nSMBALERT */
 221                         MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02              0x0b0b0
 222                 >;
 223         };
 224
 225         pinctrl_can2: can2grp {
 226                 fsl,pins = <
 227                         MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX              0x0b0b0
 228                         MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX              0x0b0b0
 229                         /* SR */
 230                         MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05              0x0b0b0
 231                 >;
 232         };
 233
 234         pinctrl_ecspi1: ecspi1grp {
 235                 fsl,pins = <
 236                         MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK               0x0b0b0
 237                         MX6UL_PAD_CSI_DATA05__GPIO4_IO26                0x000b1
 238                         MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI               0x0b0b0
 239                         MX6UL_PAD_CSI_DATA07__ECSPI1_MISO               0x0b0b0
 240                 >;
 241         };
 242
 243         pinctrl_ecspi2: ecspi2grp {
 244                 fsl,pins = <
 245                         MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK               0x0b0b0
 246                         MX6UL_PAD_CSI_DATA01__GPIO4_IO22                0x000b1
 247                         MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI               0x0b0b0
 248                         MX6UL_PAD_CSI_DATA03__ECSPI2_MISO               0x0b0b0
 249                 >;
 250         };
 251
 252         pinctrl_eth1: eth1grp {
 253                 fsl,pins = <
 254                         MX6UL_PAD_GPIO1_IO07__ENET1_MDC                 0x1b0b0
 255                         MX6UL_PAD_GPIO1_IO06__ENET1_MDIO                0x100b0
 256                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00         0x1b0b0
 257                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01         0x1b0b0
 258                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN              0x100b0
 259                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER              0x1b0b0
 260                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN              0x1b0b0
 261                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00         0x1b0b0
 262                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01         0x1b0b0
 263                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1          0x1b000
 264                         /* PHY ENET1_RST */
 265                         MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00              0x00880
 266                         /* PHY ENET1_IRQ */
 267                         MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01              0x00880
 268                 >;
 269         };
 270
 271         pinctrl_hog: hoggrp {
 272                 fsl,pins = <
 273                         /* HW revision detect */
 274                         /* REV_ID0 */
 275                         MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08            0x1b0b0
 276                         /* REV_ID1 */
 277                         MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09            0x1b0b0
 278                         /* REV_ID2 */
 279                         MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10               0x1b0b0
 280                         /* REV_ID3 */
 281                         MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11            0x1b0b0
 282                         /* BOARD_ID0 */
 283                         MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13               0x1b0b0
 284                         /* BOARD_ID1 */
 285                         MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14              0x1b0b0
 286                         /* BOARD_ID2 */
 287                         MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15               0x1b0b0
 288                         /* BOARD_ID3 */
 289                         MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12            0x1b0b0
 290                         /* Safety controller IO */
 291                         /* WAKE_SC */
 292                         MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06              0x1b0b0
 293                         /* PROGRAM_SC */
 294                         MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07              0x1b0b0
 295                 >;
 296         };
 297
 298         pinctrl_i2c1: i2c1grp {
 299                 fsl,pins = <
 300                         MX6UL_PAD_CSI_MCLK__I2C1_SDA            0x4001b8b0
 301                         MX6UL_PAD_CSI_PIXCLK__I2C1_SCL          0x4001b8b0
 302                 >;
 303         };
 304
 305         pinctrl_i2c2: i2c2grp {
 306                 fsl,pins = <
 307                         MX6UL_PAD_CSI_VSYNC__I2C2_SDA           0x4001b8b0
 308                         MX6UL_PAD_CSI_HSYNC__I2C2_SCL           0x4001b8b0
 309                 >;
 310         };
 311
 312         pinctrl_leds: ledsgrp {
 313                 fsl,pins = <
 314                         MX6UL_PAD_NAND_DQS__GPIO4_IO16                  0x1b0b0
 315                 >;
 316         };
 317
 318         pinctrl_uart1: uart1grp {
 319                 fsl,pins = <
 320                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX           0x1b0b1
 321                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX           0x1b0b1
 322                 >;
 323         };
 324
 325         pinctrl_usdhc1: usdhc1grp {
 326                 fsl,pins = <
 327                         MX6UL_PAD_SD1_CMD__USDHC1_CMD                   0x070b1
 328                         MX6UL_PAD_SD1_CLK__USDHC1_CLK                   0x07099
 329                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0               0x070b1
 330                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1               0x070b1
 331                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2               0x070b1
 332                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3               0x070b1
 333                         /* SD1 CD */
 334                         MX6UL_PAD_NAND_READY_B__GPIO4_IO12              0x170b0
 335                 >;
 336         };
 337
 338         pinctrl_usdhc2: usdhc2grp {
 339                 fsl,pins = <
 340                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD                 0x170f9
 341                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK                 0x100f9
 342                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0             0x170f9
 343                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1             0x170f9
 344                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2             0x170f9
 345                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3             0x170f9
 346                         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4             0x170f9
 347                         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5             0x170f9
 348                         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6             0x170f9
 349                         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7             0x170f9
 350                         MX6UL_PAD_NAND_ALE__USDHC2_RESET_B              0x170b0
 351                 >;
 352         };
 353 };