1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Device Tree Include file for TQ-Systems TQMa7x boards with full mounted PCB.
5 * Copyright (C) 2016 TQ-Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
7 * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
12 device_type = "memory";
13 /* 512 MB - default configuration */
14 reg = <0x80000000 0x20000000>;
19 cpu-supply = <&sw1a_reg>;
23 /* Configured as pullup by QSPI pin group */
26 gpios = <4 GPIO_ACTIVE_LOW>;
28 line-name = "qspi-reset";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_i2c1>;
35 clock-frequency = <100000>;
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_pmic1>;
41 compatible = "fsl,pfuze3000";
46 regulator-min-microvolt = <700000>;
47 regulator-max-microvolt = <3300000>;
50 regulator-ramp-delay = <6250>;
53 /* use sw1c_reg to align with pfuze100/pfuze200 */
55 regulator-min-microvolt = <700000>;
56 regulator-max-microvolt = <1475000>;
59 regulator-ramp-delay = <6250>;
63 regulator-min-microvolt = <1500000>;
64 regulator-max-microvolt = <1850000>;
70 regulator-min-microvolt = <900000>;
71 regulator-max-microvolt = <1650000>;
77 regulator-min-microvolt = <5000000>;
78 regulator-max-microvolt = <5150000>;
82 regulator-min-microvolt = <1000000>;
83 regulator-max-microvolt = <3000000>;
94 regulator-min-microvolt = <1800000>;
95 regulator-max-microvolt = <3300000>;
100 regulator-min-microvolt = <800000>;
101 regulator-max-microvolt = <1550000>;
106 regulator-min-microvolt = <2850000>;
107 regulator-max-microvolt = <3300000>;
112 regulator-min-microvolt = <2850000>;
113 regulator-max-microvolt = <3300000>;
118 regulator-min-microvolt = <1800000>;
119 regulator-max-microvolt = <3300000>;
124 regulator-min-microvolt = <1800000>;
125 regulator-max-microvolt = <3300000>;
131 /* NXP SE97BTP with temperature sensor + eeprom */
132 se97b: temperature-sensor-eeprom@1e {
133 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
140 compatible = "atmel,24c64";
147 compatible = "atmel,24c02";
154 compatible = "dallas,ds1339";
160 pinctrl_i2c1: i2c1grp {
162 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078
163 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078
167 pinctrl_pmic1: pmic1grp {
169 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C
173 pinctrl_qspi: qspigrp {
175 MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A
176 MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A
177 MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A
178 MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A
179 MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11
180 MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54
181 MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54
185 pinctrl_qspi_reset: qspi_resetgrp {
188 MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52
192 pinctrl_usdhc3: usdhc3grp {
194 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
195 MX7D_PAD_SD3_CLK__SD3_CLK 0x56
196 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
197 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
198 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
199 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
200 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
201 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
202 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
203 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
204 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
208 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
210 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
211 MX7D_PAD_SD3_CLK__SD3_CLK 0x51
212 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
213 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
214 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
215 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
216 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
217 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
218 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
219 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
220 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
224 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
226 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
227 MX7D_PAD_SD3_CLK__SD3_CLK 0x51
228 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
229 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
230 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
231 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
232 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
233 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
234 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
235 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
236 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
242 pinctrl_wdog1: wdog1grp {
244 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_qspi &pinctrl_qspi_reset>;
255 compatible = "jedec,spi-nor";
257 spi-max-frequency = <29000000>;
258 spi-rx-bus-width = <4>;
259 spi-tx-bus-width = <4>;
268 pinctrl-names = "default", "state_100mhz", "state_200mhz";
269 pinctrl-0 = <&pinctrl_usdhc3>;
270 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
271 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
272 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
273 assigned-clock-rates = <400000000>;
276 vmmc-supply = <&vgen4_reg>;
277 vqmmc-supply = <&sw2_reg>;
282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_wdog1>;
286 * WDOG reset needs to run with WDOG_RESET_B signal enabled.
287 * X1-51 (WDOG1#) signal needs carrier board handling to reset
288 * TQMa7 on X1-22 (RESET_IN#).
290 fsl,ext-reset-output;