src/arm/nxp/imx/imx7d-pico.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 //
   3 // Copyright 2017 NXP
   4
   5 /dts-v1/;
   6
   7 #include "imx7d.dtsi"
   8
   9 / {
  10         backlight: backlight {
  11                 compatible = "pwm-backlight";
  12                 pwms = <&pwm4 0 50000 0>;
  13                 brightness-levels = <0 36 72 108 144 180 216 255>;
  14                 default-brightness-level = <6>;
  15         };
  16
  17         /* Will be filled by the bootloader */
  18         memory@80000000 {
  19                 device_type = "memory";
  20                 reg = <0x80000000 0>;
  21         };
  22
  23         panel {
  24                 compatible = "vxt,vl050-8048nt-c01";
  25                 backlight = <&backlight>;
  26                 power-supply = <&reg_lcd_3v3>;
  27
  28                 port {
  29                         panel_in: endpoint {
  30                                 remote-endpoint = <&display_out>;
  31                         };
  32                 };
  33         };
  34
  35         reg_lcd_3v3: regulator-lcd-3v3 {
  36                 compatible = "regulator-fixed";
  37                 pinctrl-names = "default";
  38                 pinctrl-0 = <&pinctrl_reg_lcdreg_on>;
  39                 regulator-name = "lcd-3v3";
  40                 regulator-min-microvolt = <3300000>;
  41                 regulator-max-microvolt = <3300000>;
  42                 gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
  43                 enable-active-high;
  44         };
  45
  46         reg_wlreg_on: regulator-wlreg_on {
  47                 compatible = "regulator-fixed";
  48                 pinctrl-names = "default";
  49                 pinctrl-0 = <&pinctrl_reg_wlreg_on>;
  50                 regulator-name = "wlreg_on";
  51                 regulator-min-microvolt = <3300000>;
  52                 regulator-max-microvolt = <3300000>;
  53                 gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
  54                 enable-active-high;
  55         };
  56
  57         reg_2p5v: regulator-2p5v {
  58                 compatible = "regulator-fixed";
  59                 regulator-name = "2P5V";
  60                 regulator-min-microvolt = <2500000>;
  61                 regulator-max-microvolt = <2500000>;
  62                 regulator-always-on;
  63         };
  64
  65         reg_3p3v: regulator-3p3v {
  66                 compatible = "regulator-fixed";
  67                 regulator-name = "3P3V";
  68                 regulator-min-microvolt = <3300000>;
  69                 regulator-max-microvolt = <3300000>;
  70                 regulator-always-on;
  71         };
  72
  73         reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  74                 pinctrl-names = "default";
  75                 pinctrl-0 = <&pinctrl_usbotg1_pwr>;
  76                 compatible = "regulator-fixed";
  77                 regulator-name = "usb_otg1_vbus";
  78                 regulator-min-microvolt = <5000000>;
  79                 regulator-max-microvolt = <5000000>;
  80                 gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
  81         };
  82
  83         reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
  84                 compatible = "regulator-fixed";
  85                 regulator-name = "usb_otg2_vbus";
  86                 regulator-min-microvolt = <5000000>;
  87                 regulator-max-microvolt = <5000000>;
  88         };
  89
  90         reg_vref_1v8: regulator-vref-1v8 {
  91                 compatible = "regulator-fixed";
  92                 regulator-name = "vref-1v8";
  93                 regulator-min-microvolt = <1800000>;
  94                 regulator-max-microvolt = <1800000>;
  95         };
  96
  97         usdhc2_pwrseq: usdhc2_pwrseq {
  98                 compatible = "mmc-pwrseq-simple";
  99                 clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
 100                 clock-names = "ext_clock";
 101         };
 102 };
 103
 104 &clks {
 105         assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
 106                           <&clks IMX7D_CLKO2_ROOT_DIV>;
 107         assigned-clock-parents = <&clks IMX7D_CKIL>;
 108         assigned-clock-rates = <0>, <32768>;
 109 };
 110
 111 &ecspi3 {
 112         cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
 113         pinctrl-names = "default";
 114         pinctrl-0 = <&pinctrl_ecspi3>;
 115         status = "okay";
 116 };
 117
 118 &fec1 {
 119         pinctrl-names = "default";
 120         pinctrl-0 = <&pinctrl_enet1>;
 121         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
 122                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 123         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 124         assigned-clock-rates = <0>, <100000000>;
 125         phy-mode = "rgmii-id";
 126         phy-handle = <&ethphy0>;
 127         fsl,magic-packet;
 128         phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
 129         status = "okay";
 130
 131         mdio {
 132                 #address-cells = <1>;
 133                 #size-cells = <0>;
 134
 135                 ethphy0: ethernet-phy@1 {
 136                         compatible = "ethernet-phy-ieee802.3-c22";
 137                         reg = <1>;
 138                         status = "okay";
 139                 };
 140         };
 141 };
 142
 143 &flexcan1 {
 144         pinctrl-names = "default";
 145         pinctrl-0 = <&pinctrl_can1>;
 146         status = "okay";
 147 };
 148
 149 &flexcan2 {
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&pinctrl_can2>;
 152         status = "okay";
 153 };
 154
 155 &i2c1 {
 156         clock-frequency = <100000>;
 157         pinctrl-names = "default";
 158         pinctrl-0 = <&pinctrl_i2c1>;
 159         status = "okay";
 160 };
 161
 162 &i2c2 {
 163         pinctrl-names = "default";
 164         pinctrl-0 = <&pinctrl_i2c2>;
 165         status = "okay";
 166 };
 167
 168 &i2c4 {
 169         pinctrl-names = "default";
 170         pinctrl-0 = <&pinctrl_i2c4>;
 171         status = "okay";
 172
 173         pmic: pmic@8 {
 174                 compatible = "fsl,pfuze3000";
 175                 reg = <0x08>;
 176
 177                 regulators {
 178                         sw1a_reg: sw1a {
 179                                 regulator-min-microvolt = <700000>;
 180                                 regulator-max-microvolt = <3300000>;
 181                                 regulator-boot-on;
 182                                 regulator-always-on;
 183                                 regulator-ramp-delay = <6250>;
 184                         };
 185                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 186                         sw1c_reg: sw1b {
 187                                 regulator-min-microvolt = <700000>;
 188                                 regulator-max-microvolt = <1475000>;
 189                                 regulator-boot-on;
 190                                 regulator-always-on;
 191                                 regulator-ramp-delay = <6250>;
 192                         };
 193
 194                         sw2_reg: sw2 {
 195                                 regulator-min-microvolt = <1800000>;
 196                                 regulator-max-microvolt = <1850000>;
 197                                 regulator-boot-on;
 198                                 regulator-always-on;
 199                         };
 200
 201                         sw3a_reg: sw3 {
 202                                 regulator-min-microvolt = <900000>;
 203                                 regulator-max-microvolt = <1650000>;
 204                                 regulator-boot-on;
 205                                 regulator-always-on;
 206                         };
 207
 208                         swbst_reg: swbst {
 209                                 regulator-min-microvolt = <5000000>;
 210                                 regulator-max-microvolt = <5150000>;
 211                         };
 212
 213                         snvs_reg: vsnvs {
 214                                 regulator-min-microvolt = <1000000>;
 215                                 regulator-max-microvolt = <3000000>;
 216                                 regulator-boot-on;
 217                                 regulator-always-on;
 218                         };
 219
 220                         vref_reg: vrefddr {
 221                                 regulator-boot-on;
 222                                 regulator-always-on;
 223                         };
 224
 225                         vgen1_reg: vldo1 {
 226                                 regulator-min-microvolt = <1800000>;
 227                                 regulator-max-microvolt = <3300000>;
 228                                 regulator-always-on;
 229                         };
 230
 231                         vgen2_reg: vldo2 {
 232                                 regulator-min-microvolt = <800000>;
 233                                 regulator-max-microvolt = <1550000>;
 234                         };
 235
 236                         vgen3_reg: vccsd {
 237                                 regulator-min-microvolt = <2850000>;
 238                                 regulator-max-microvolt = <3300000>;
 239                                 regulator-always-on;
 240                         };
 241
 242                         vgen4_reg: v33 {
 243                                 regulator-min-microvolt = <2850000>;
 244                                 regulator-max-microvolt = <3300000>;
 245                                 regulator-always-on;
 246                         };
 247
 248                         vgen5_reg: vldo3 {
 249                                 regulator-min-microvolt = <1800000>;
 250                                 regulator-max-microvolt = <3300000>;
 251                                 regulator-always-on;
 252                         };
 253
 254                         vgen6_reg: vldo4 {
 255                                 regulator-min-microvolt = <1800000>;
 256                                 regulator-max-microvolt = <3300000>;
 257                                 regulator-always-on;
 258                         };
 259                 };
 260         };
 261 };
 262
 263 &lcdif {
 264         pinctrl-names = "default";
 265         pinctrl-0 = <&pinctrl_lcdif>;
 266         status = "okay";
 267
 268         port {
 269                 display_out: endpoint {
 270                         remote-endpoint = <&panel_in>;
 271                 };
 272         };
 273 };
 274
 275 &sai1 {
 276         pinctrl-names = "default";
 277         pinctrl-0 = <&pinctrl_sai1>;
 278         assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
 279                           <&clks IMX7D_SAI1_ROOT_CLK>;
 280         assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
 281         assigned-clock-rates = <0>, <24576000>;
 282         status = "okay";
 283 };
 284
 285
 286 &pwm1 {
 287         pinctrl-names = "default";
 288         pinctrl-0 = <&pinctrl_pwm1>;
 289         status = "okay";
 290 };
 291
 292 &pwm2 {
 293         pinctrl-names = "default";
 294         pinctrl-0 = <&pinctrl_pwm2>;
 295         status = "okay";
 296 };
 297
 298 &pwm3 {
 299         pinctrl-names = "default";
 300         pinctrl-0 = <&pinctrl_pwm3>;
 301         status = "okay";
 302 };
 303
 304 &pwm4 { /* Backlight */
 305         pinctrl-names = "default";
 306         pinctrl-0 = <&pinctrl_pwm4>;
 307         status = "okay";
 308 };
 309
 310 &uart5 {
 311         pinctrl-names = "default";
 312         pinctrl-0 = <&pinctrl_uart5>;
 313         assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
 314         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 315         status = "okay";
 316 };
 317
 318 &uart6 {
 319         pinctrl-names = "default";
 320         pinctrl-0 = <&pinctrl_uart6>;
 321         assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
 322         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 323         uart-has-rtscts;
 324         status = "okay";
 325 };
 326
 327 &uart7 { /* Bluetooth */
 328         pinctrl-names = "default";
 329         pinctrl-0 = <&pinctrl_uart7>;
 330         assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
 331         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 332         uart-has-rtscts;
 333         status = "okay";
 334 };
 335
 336 &usbotg1 {
 337         vbus-supply = <&reg_usb_otg1_vbus>;
 338         status = "okay";
 339 };
 340
 341 &usbotg2 {
 342         vbus-supply = <&reg_usb_otg2_vbus>;
 343         dr_mode = "host";
 344         status = "okay";
 345 };
 346
 347 &usdhc1 {
 348         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 349         pinctrl-0 = <&pinctrl_usdhc1>;
 350         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 351         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 352         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 353         bus-width = <4>;
 354         fsl,tuning-step = <2>;
 355         vmmc-supply = <&reg_3p3v>;
 356         wakeup-source;
 357         no-1-8-v;
 358         keep-power-in-suspend;
 359         status = "okay";
 360 };
 361
 362 &usdhc2 { /* Wifi SDIO */
 363         pinctrl-names = "default";
 364         pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>;
 365         no-1-8-v;
 366         non-removable;
 367         keep-power-in-suspend;
 368         wakeup-source;
 369         vmmc-supply = <&reg_wlreg_on>;
 370         mmc-pwrseq = <&usdhc2_pwrseq>;
 371         status = "okay";
 372 };
 373
 374 &usdhc3 {
 375         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 376         pinctrl-0 = <&pinctrl_usdhc3>;
 377         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 378         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 379         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 380         assigned-clock-rates = <400000000>;
 381         bus-width = <8>;
 382         no-1-8-v;
 383         fsl,tuning-step = <2>;
 384         non-removable;
 385         status = "okay";
 386 };
 387
 388 &wdog1 {
 389         pinctrl-names = "default";
 390         pinctrl-0 = <&pinctrl_wdog>;
 391         fsl,ext-reset-output;
 392         status = "okay";
 393 };
 394
 395 &iomuxc {
 396         pinctrl_ecspi3: ecspi3grp {
 397                 fsl,pins = <
 398                         MX7D_PAD_I2C1_SCL__ECSPI3_MISO          0x2
 399                         MX7D_PAD_I2C1_SDA__ECSPI3_MOSI          0x2
 400                         MX7D_PAD_I2C2_SCL__ECSPI3_SCLK          0x2
 401                         MX7D_PAD_I2C2_SDA__GPIO4_IO11           0x14
 402                 >;
 403         };
 404
 405         pinctrl_i2c1: i2c1grp {
 406                 fsl,pins = <
 407                         MX7D_PAD_UART1_TX_DATA__I2C1_SDA        0x4000007f
 408                         MX7D_PAD_UART1_RX_DATA__I2C1_SCL        0x4000007f
 409                 >;
 410         };
 411
 412         pinctrl_i2c2: i2c2grp {
 413                 fsl,pins = <
 414                         MX7D_PAD_UART2_TX_DATA__I2C2_SDA        0x4000007f
 415                         MX7D_PAD_UART2_RX_DATA__I2C2_SCL        0x4000007f
 416                 >;
 417         };
 418
 419         pinctrl_enet1: enet1grp {
 420                 fsl,pins = <
 421                         MX7D_PAD_SD2_CD_B__ENET1_MDIO                   0x3
 422                         MX7D_PAD_SD2_WP__ENET1_MDC                      0x3
 423                         MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x1
 424                         MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x1
 425                         MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x1
 426                         MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x1
 427                         MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x1
 428                         MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
 429                         MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x1
 430                         MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x1
 431                         MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x1
 432                         MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x1
 433                         MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x1
 434                         MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
 435                         MX7D_PAD_SD3_RESET_B__GPIO6_IO11                0x1  /* Ethernet reset */
 436                 >;
 437         };
 438
 439         pinctrl_can1: can1frp {
 440                 fsl,pins = <
 441                         MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX      0x59
 442                         MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX      0x59
 443                 >;
 444         };
 445
 446         pinctrl_can2: can2frp {
 447                 fsl,pins = <
 448                         MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX      0x59
 449                         MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX      0x59
 450                 >;
 451         };
 452
 453         pinctrl_i2c4: i2c4grp {
 454                 fsl,pins = <
 455                         MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA         0x4000007f
 456                         MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL         0x4000007f
 457                 >;
 458         };
 459
 460         pinctrl_lcdif: lcdifgrp {
 461                 fsl,pins = <
 462                         MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
 463                         MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
 464                         MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
 465                         MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
 466                         MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
 467                         MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
 468                         MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
 469                         MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
 470                         MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
 471                         MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
 472                         MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
 473                         MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
 474                         MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
 475                         MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
 476                         MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
 477                         MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
 478                         MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
 479                         MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
 480                         MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
 481                         MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
 482                         MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
 483                         MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
 484                         MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
 485                         MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
 486                         MX7D_PAD_LCD_CLK__LCD_CLK               0x79
 487                         MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x78
 488                         MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x78
 489                         MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x78
 490                         MX7D_PAD_LCD_RESET__GPIO3_IO4           0x14
 491                 >;
 492         };
 493
 494         pinctrl_pwm1: pwm1 {
 495                 fsl,pins = <
 496                         MX7D_PAD_GPIO1_IO08__PWM1_OUT   0x7f
 497                 >;
 498         };
 499
 500         pinctrl_pwm2: pwm2 {
 501                 fsl,pins = <
 502                         MX7D_PAD_GPIO1_IO09__PWM2_OUT   0x7f
 503                 >;
 504         };
 505
 506         pinctrl_pwm3: pwm3 {
 507                 fsl,pins = <
 508                         MX7D_PAD_GPIO1_IO10__PWM3_OUT   0x7f
 509                 >;
 510         };
 511
 512         pinctrl_pwm4: pwm4grp {
 513                 fsl,pins = <
 514                         MX7D_PAD_GPIO1_IO11__PWM4_OUT   0x7f
 515                 >;
 516         };
 517
 518         pinctrl_reg_wlreg_on: regregongrp {
 519                 fsl,pins = <
 520                         MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16        0x59
 521                 >;
 522         };
 523
 524         pinctrl_sai1: sai1grp {
 525                 fsl,pins = <
 526                         MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK     0x1f
 527                         MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC        0x1f
 528                         MX7D_PAD_ENET1_COL__SAI1_TX_DATA0       0x30
 529                         MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0    0x1f
 530                 >;
 531         };
 532
 533         pinctrl_uart5: uart5grp {
 534                 fsl,pins = <
 535                         MX7D_PAD_I2C4_SDA__UART5_DCE_TX         0x79
 536                         MX7D_PAD_I2C4_SCL__UART5_DCE_RX         0x79
 537                 >;
 538         };
 539
 540         pinctrl_uart6: uart6grp {
 541                 fsl,pins = <
 542                         MX7D_PAD_EPDC_DATA08__UART6_DCE_RX      0x79
 543                         MX7D_PAD_EPDC_DATA09__UART6_DCE_TX      0x79
 544                         MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS     0x79
 545                         MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS     0x79
 546                 >;
 547         };
 548
 549         pinctrl_uart7: uart7grp {
 550                 fsl,pins = <
 551                         MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX      0x79
 552                         MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX      0x79
 553                         MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS      0x79
 554                         MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS     0x79
 555                 >;
 556         };
 557
 558         pinctrl_usbotg1_pwr: usbotg_pwr {
 559                 fsl,pins = <
 560                         MX7D_PAD_UART3_TX_DATA__GPIO4_IO5       0x14
 561                 >;
 562         };
 563
 564         pinctrl_usdhc1: usdhc1grp {
 565                 fsl,pins = <
 566                         MX7D_PAD_SD1_CMD__SD1_CMD               0x59
 567                         MX7D_PAD_SD1_CLK__SD1_CLK               0x19
 568                         MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
 569                         MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
 570                         MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
 571                         MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
 572                         MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x15
 573                 >;
 574         };
 575
 576         pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
 577                 fsl,pins = <
 578                         MX7D_PAD_SD1_CMD__SD1_CMD               0x5a
 579                         MX7D_PAD_SD1_CLK__SD1_CLK               0x1a
 580                         MX7D_PAD_SD1_DATA0__SD1_DATA0           0x5a
 581                         MX7D_PAD_SD1_DATA1__SD1_DATA1           0x5a
 582                         MX7D_PAD_SD1_DATA2__SD1_DATA2           0x5a
 583                         MX7D_PAD_SD1_DATA3__SD1_DATA3           0x5a
 584                         MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x15
 585                 >;
 586         };
 587
 588         pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
 589                 fsl,pins = <
 590                         MX7D_PAD_SD1_CMD__SD1_CMD               0x5b
 591                         MX7D_PAD_SD1_CLK__SD1_CLK               0x1b
 592                         MX7D_PAD_SD1_DATA0__SD1_DATA0           0x5b
 593                         MX7D_PAD_SD1_DATA1__SD1_DATA1           0x5b
 594                         MX7D_PAD_SD1_DATA2__SD1_DATA2           0x5b
 595                         MX7D_PAD_SD1_DATA3__SD1_DATA3           0x5b
 596                         MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x15
 597                 >;
 598         };
 599
 600         pinctrl_usdhc2: usdhc2grp {
 601                 fsl,pins = <
 602                         MX7D_PAD_SD2_CMD__SD2_CMD               0x59
 603                         MX7D_PAD_SD2_CLK__SD2_CLK               0x19
 604                         MX7D_PAD_SD2_DATA0__SD2_DATA0           0x59
 605                         MX7D_PAD_SD2_DATA1__SD2_DATA1           0x59
 606                         MX7D_PAD_SD2_DATA2__SD2_DATA2           0x59
 607                         MX7D_PAD_SD2_DATA3__SD2_DATA3           0x59
 608                 >;
 609         };
 610
 611         pinctrl_usdhc3: usdhc3grp {
 612                 fsl,pins = <
 613                         MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 614                         MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 615                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 616                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 617                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 618                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 619                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 620                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 621                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 622                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 623                 >;
 624         };
 625
 626         pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 627                 fsl,pins = <
 628                         MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
 629                         MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
 630                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
 631                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
 632                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
 633                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
 634                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
 635                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
 636                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
 637                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
 638                 >;
 639         };
 640
 641         pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 642                 fsl,pins = <
 643                         MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
 644                         MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
 645                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
 646                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
 647                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
 648                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
 649                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
 650                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
 651                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
 652                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
 653                 >;
 654         };
 655 };
 656
 657 &iomuxc_lpsr {
 658         pinctrl_wifi_clk: wificlkgrp {
 659                 fsl,pins = <
 660                         MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2     0x7d
 661                 >;
 662         };
 663
 664         pinctrl_reg_lcdreg_on: reglcdongrp {
 665         fsl,pins = <
 666                         MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6     0x59
 667                 >;
 668         };
 669
 670         pinctrl_wdog: wdoggrp {
 671                 fsl,pins = <
 672                         MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B  0x74
 673                 >;
 674         };
 675 };