src/arm/nxp/vf/vf610-bk4.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2018
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  */
   6
   7 /dts-v1/;
   8 #include "vf610.dtsi"
   9
  10 / {
  11         model = "Liebherr BK4 controller";
  12         compatible = "lwn,bk4", "fsl,vf610";
  13
  14         chosen {
  15                 stdout-path = &uart1;
  16         };
  17
  18         memory@80000000 {
  19                 device_type = "memory";
  20                 reg = <0x80000000 0x8000000>;
  21         };
  22
  23         audio_ext: oscillator-audio {
  24                 compatible = "fixed-clock";
  25                 #clock-cells = <0>;
  26                 clock-frequency = <24576000>;
  27         };
  28
  29         enet_ext: oscillator-ethernet {
  30                 compatible = "fixed-clock";
  31                 #clock-cells = <0>;
  32                 clock-frequency = <50000000>;
  33         };
  34
  35         leds {
  36                 compatible = "gpio-leds";
  37                 pinctrl-names = "default";
  38                 pinctrl-0 = <&pinctrl_gpio_leds>;
  39
  40                 /* LED D5 */
  41                 led0: led-heartbeat {
  42                         label = "heartbeat";
  43                         gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
  44                         default-state = "on";
  45                         linux,default-trigger = "heartbeat";
  46                 };
  47         };
  48
  49         reg_3p3v: regulator-3p3v {
  50                 compatible = "regulator-fixed";
  51                 regulator-name = "3P3V";
  52                 regulator-min-microvolt = <3300000>;
  53                 regulator-max-microvolt = <3300000>;
  54                 regulator-always-on;
  55         };
  56
  57         reg_vcc_3v3_mcu: regulator-vcc3v3mcu {
  58                 compatible = "regulator-fixed";
  59                 regulator-name = "vcc_3v3_mcu";
  60                 regulator-min-microvolt = <3300000>;
  61                 regulator-max-microvolt = <3300000>;
  62         };
  63
  64         spi {
  65                 compatible = "spi-gpio";
  66                 pinctrl-0 = <&pinctrl_gpio_spi>;
  67                 pinctrl-names = "default";
  68                 #address-cells = <1>;
  69                 #size-cells = <0>;
  70                 /* PTD12 ->RPIO[91] */
  71                 sck-gpios  = <&gpio2 27 GPIO_ACTIVE_LOW>;
  72                 /* PTD10 ->RPIO[89] */
  73                 miso-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
  74                 num-chipselects = <0>;
  75
  76                 gpio@0 {
  77                         compatible = "pisosr-gpio";
  78                         reg = <0>;
  79                         gpio-controller;
  80                         #gpio-cells = <2>;
  81                         /* PTB18 -> RGPIO[40] */
  82                         load-gpios  = <&gpio1 8 GPIO_ACTIVE_LOW>;
  83                         spi-max-frequency = <100000>;
  84                 };
  85         };
  86 };
  87
  88 &adc0 {
  89         vref-supply = <&reg_vcc_3v3_mcu>;
  90         status = "okay";
  91 };
  92
  93 &adc1 {
  94         vref-supply = <&reg_vcc_3v3_mcu>;
  95         status = "okay";
  96 };
  97
  98 &can0 {
  99         pinctrl-names = "default";
 100         pinctrl-0 = <&pinctrl_can0>;
 101         status = "okay";
 102 };
 103
 104 &can1 {
 105         pinctrl-names = "default";
 106         pinctrl-0 = <&pinctrl_can1>;
 107         status = "okay";
 108 };
 109
 110 &clks {
 111         clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
 112         clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
 113 };
 114
 115 &dspi0 {
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&pinctrl_dspi0>;
 118         bus-num = <0>;
 119         status = "okay";
 120
 121         spidev0@0 {
 122                 compatible = "lwn,bk4";
 123                 spi-max-frequency = <30000000>;
 124                 reg = <0>;
 125                 fsl,spi-cs-sck-delay = <200>;
 126                 fsl,spi-sck-cs-delay = <400>;
 127         };
 128 };
 129
 130 &dspi3 {
 131         pinctrl-names = "default";
 132         pinctrl-0 = <&pinctrl_dspi3>;
 133         bus-num = <3>;
 134         status = "okay";
 135         spi-slave;
 136         #address-cells = <0>;
 137
 138         slave {
 139                 compatible = "lwn,bk4";
 140                 spi-max-frequency = <30000000>;
 141         };
 142 };
 143
 144 &edma0 {
 145         status = "okay";
 146 };
 147
 148 &edma1 {
 149         status = "okay";
 150 };
 151
 152 &esdhc1 {
 153         pinctrl-names = "default";
 154         pinctrl-0 = <&pinctrl_esdhc1>;
 155         bus-width = <4>;
 156         cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
 157         status = "okay";
 158 };
 159
 160 &fec0 {
 161         phy-mode = "rmii";
 162         phy-handle = <&ethphy0>;
 163         pinctrl-names = "default";
 164         pinctrl-0 = <&pinctrl_fec0>;
 165         status = "okay";
 166
 167         mdio {
 168                 #address-cells = <1>;
 169                 #size-cells = <0>;
 170
 171                 ethphy0: ethernet-phy@1 {
 172                         reg = <1>;
 173                         clocks = <&clks VF610_CLK_ENET_50M>;
 174                         clock-names = "rmii-ref";
 175                 };
 176         };
 177 };
 178
 179 &fec1 {
 180         phy-mode = "rmii";
 181         phy-handle = <&ethphy1>;
 182         pinctrl-names = "default";
 183         pinctrl-0 = <&pinctrl_fec1>;
 184         status = "okay";
 185
 186         mdio {
 187                 #address-cells = <1>;
 188                 #size-cells = <0>;
 189
 190                 ethphy1: ethernet-phy@1 {
 191                         reg = <1>;
 192                         clocks = <&clks VF610_CLK_ENET_50M>;
 193                         clock-names = "rmii-ref";
 194                 };
 195         };
 196 };
 197
 198 &i2c2 {
 199         clock-frequency = <400000>;
 200         pinctrl-names = "default";
 201         pinctrl-0 = <&pinctrl_i2c2>;
 202         status = "okay";
 203
 204         at24c256: eeprom@50 {
 205                 compatible = "atmel,24c256";
 206                 reg = <0x50>;
 207         };
 208
 209         m41t62: rtc@68 {
 210                 compatible = "st,m41t62";
 211                 reg = <0x68>;
 212         };
 213 };
 214
 215 &nfc {
 216         assigned-clocks = <&clks VF610_CLK_NFC>;
 217         assigned-clock-rates = <33000000>;
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&pinctrl_nfc>;
 220         status = "okay";
 221
 222         nand@0 {
 223                 compatible = "fsl,vf610-nfc-nandcs";
 224                 reg = <0>;
 225                 #address-cells = <1>;
 226                 #size-cells = <1>;
 227                 nand-bus-width = <16>;
 228                 nand-ecc-mode = "hw";
 229                 nand-ecc-strength = <24>;
 230                 nand-ecc-step-size = <2048>;
 231                 nand-on-flash-bbt;
 232         };
 233 };
 234
 235 &qspi0 {
 236         pinctrl-names = "default";
 237         pinctrl-0 = <&pinctrl_qspi0>;
 238         status = "okay";
 239
 240         n25q128a13_4: flash@0 {
 241                 compatible = "n25q128a13", "jedec,spi-nor";
 242                 #address-cells = <1>;
 243                 #size-cells = <1>;
 244                 spi-max-frequency = <66000000>;
 245                 spi-rx-bus-width = <4>;
 246                 reg = <0>;
 247         };
 248
 249         n25q128a13_2: flash@2 {
 250                 compatible = "n25q128a13", "jedec,spi-nor";
 251                 #address-cells = <1>;
 252                 #size-cells = <1>;
 253                 spi-max-frequency = <66000000>;
 254                 spi-rx-bus-width = <2>;
 255                 reg = <2>;
 256         };
 257 };
 258
 259 &uart0 {
 260         pinctrl-names = "default";
 261         pinctrl-0 = <&pinctrl_uart0>;
 262         /delete-property/dma-names;
 263         status = "okay";
 264 };
 265
 266 &uart1 {
 267         pinctrl-names = "default";
 268         pinctrl-0 = <&pinctrl_uart1>;
 269         /delete-property/dma-names;
 270         status = "okay";
 271 };
 272
 273 &uart2 {
 274         pinctrl-names = "default";
 275         pinctrl-0 = <&pinctrl_uart2>;
 276         /delete-property/dma-names;
 277         status = "okay";
 278 };
 279
 280 &uart3 {
 281         pinctrl-names = "default";
 282         pinctrl-0 = <&pinctrl_uart3>;
 283         /delete-property/dma-names;
 284         status = "okay";
 285 };
 286
 287 &usbdev0 {
 288         disable-over-current;
 289         status = "okay";
 290 };
 291
 292 &usbh1 {
 293         disable-over-current;
 294         status = "okay";
 295 };
 296
 297 &usbmisc0 {
 298         status = "okay";
 299 };
 300
 301 &usbmisc1 {
 302         status = "okay";
 303 };
 304
 305 &usbphy0 {
 306         status = "okay";
 307 };
 308
 309 &usbphy1 {
 310         status = "okay";
 311 };
 312
 313 &iomuxc {
 314         pinctrl-names = "default";
 315         pinctrl-0 = <&pinctrl_hog>;
 316
 317         pinctrl_hog: hoggrp {
 318                 fsl,pins = <
 319                         /* One_Wire_PSU_EN */
 320                         VF610_PAD_PTC29__GPIO_102               0x1183
 321                         /* SPI ENABLE */
 322                         VF610_PAD_PTB26__GPIO_96                0x1183
 323                         /* EB control */
 324                         VF610_PAD_PTE14__GPIO_119               0x1183
 325                         VF610_PAD_PTE4__GPIO_109                0x1181
 326                         /* Feedback_Lines */
 327                         VF610_PAD_PTC31__GPIO_104               0x1181
 328                         VF610_PAD_PTA7__GPIO_134                0x1181
 329                         VF610_PAD_PTD9__GPIO_88         0x1181
 330                         VF610_PAD_PTE1__GPIO_106                0x1183
 331                         VF610_PAD_PTB2__GPIO_24         0x1181
 332                         VF610_PAD_PTB3__GPIO_25         0x1181
 333                         VF610_PAD_PTB1__GPIO_23         0x1181
 334                         /* SDHC Enable */
 335                         VF610_PAD_PTE19__GPIO_124               0x1183
 336                         /* SDHC Overcurrent */
 337                         VF610_PAD_PTB23__GPIO_93                0x1181
 338                         /* GPI */
 339                         VF610_PAD_PTE2__GPIO_107                0x1181
 340                         VF610_PAD_PTE3__GPIO_108                0x1181
 341                         VF610_PAD_PTE5__GPIO_110                0x1181
 342                         VF610_PAD_PTE6__GPIO_111                0x1181
 343                         /* GPO */
 344                         VF610_PAD_PTE0__GPIO_105                0x1183
 345                         VF610_PAD_PTE7__GPIO_112                0x1183
 346                         /* RS485 Control */
 347                         VF610_PAD_PTB8__GPIO_30         0x1183
 348                         VF610_PAD_PTB9__GPIO_31         0x1183
 349                         VF610_PAD_PTE8__GPIO_113                0x1183
 350                         /* MPBUS MPB_EN */
 351                         VF610_PAD_PTE28__GPIO_133               0x1183
 352                         /* MISC */
 353                         VF610_PAD_PTE10__GPIO_115               0x1183
 354                         VF610_PAD_PTE11__GPIO_116               0x1183
 355                         VF610_PAD_PTE17__GPIO_122               0x1183
 356                         VF610_PAD_PTC30__GPIO_103               0x1183
 357                         VF610_PAD_PTB0__GPIO_22         0x1181
 358                         /* RESETINFO */
 359                         VF610_PAD_PTE26__GPIO_131               0x1183
 360                         VF610_PAD_PTD6__GPIO_85         0x1181
 361                         VF610_PAD_PTE27__GPIO_132               0x1181
 362                         VF610_PAD_PTE13__GPIO_118               0x1181
 363                         VF610_PAD_PTE21__GPIO_126               0x1181
 364                         VF610_PAD_PTE22__GPIO_127               0x1181
 365                         /* EE_5V_EN */
 366                         VF610_PAD_PTE18__GPIO_123               0x1183
 367                         /* EE_5V_OC_N */
 368                         VF610_PAD_PTE25__GPIO_130               0x1181
 369                 >;
 370         };
 371
 372         pinctrl_can0: can0grp {
 373                 fsl,pins = <
 374                         VF610_PAD_PTB14__CAN0_RX                0x1181
 375                         VF610_PAD_PTB15__CAN0_TX                0x1182
 376                 >;
 377         };
 378
 379         pinctrl_can1: can1grp {
 380                 fsl,pins = <
 381                         VF610_PAD_PTB16__CAN1_RX                0x1181
 382                         VF610_PAD_PTB17__CAN1_TX                0x1182
 383                 >;
 384         };
 385
 386         pinctrl_dspi0: dspi0grp {
 387                 fsl,pins = <
 388                         VF610_PAD_PTB18__DSPI0_CS1              0x1182
 389                         VF610_PAD_PTB19__DSPI0_CS0              0x1182
 390                         VF610_PAD_PTB20__DSPI0_SIN              0x1181
 391                         VF610_PAD_PTB21__DSPI0_SOUT             0x1182
 392                         VF610_PAD_PTB22__DSPI0_SCK              0x1182
 393                 >;
 394         };
 395
 396         pinctrl_dspi3: dspi3grp {
 397                 fsl,pins = <
 398                         VF610_PAD_PTD10__DSPI3_CS0              0x1181
 399                         VF610_PAD_PTD11__DSPI3_SIN              0x1181
 400                         VF610_PAD_PTD12__DSPI3_SOUT             0x1182
 401                         VF610_PAD_PTD13__DSPI3_SCK              0x1181
 402                 >;
 403         };
 404
 405         pinctrl_esdhc1: esdhc1grp {
 406                 fsl,pins = <
 407                         VF610_PAD_PTA24__ESDHC1_CLK             0x31ef
 408                         VF610_PAD_PTA25__ESDHC1_CMD             0x31ef
 409                         VF610_PAD_PTA26__ESDHC1_DAT0            0x31ef
 410                         VF610_PAD_PTA27__ESDHC1_DAT1            0x31ef
 411                         VF610_PAD_PTA28__ESDHC1_DATA2           0x31ef
 412                         VF610_PAD_PTA29__ESDHC1_DAT3            0x31ef
 413                         VF610_PAD_PTB28__GPIO_98                0x219d
 414                 >;
 415         };
 416
 417         pinctrl_fec0: fec0grp {
 418                 fsl,pins = <
 419                         VF610_PAD_PTA6__RMII_CLKIN              0x30dd
 420                         VF610_PAD_PTC0__ENET_RMII0_MDC          0x30de
 421                         VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30df
 422                         VF610_PAD_PTC2__ENET_RMII0_CRS          0x30dd
 423                         VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30dd
 424                         VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30dd
 425                         VF610_PAD_PTC5__ENET_RMII0_RXER 0x30dd
 426                         VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30de
 427                         VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30de
 428                         VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30de
 429                 >;
 430         };
 431
 432         pinctrl_fec1: fec1grp {
 433                 fsl,pins = <
 434                         VF610_PAD_PTC9__ENET_RMII1_MDC          0x30de
 435                         VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30df
 436                         VF610_PAD_PTC11__ENET_RMII1_CRS 0x30dd
 437                         VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30dd
 438                         VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30dd
 439                         VF610_PAD_PTC14__ENET_RMII1_RXER        0x30dd
 440                         VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30de
 441                         VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30de
 442                         VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30de
 443                 >;
 444         };
 445
 446         pinctrl_gpio_leds: gpioledsgrp {
 447                 fsl,pins = <
 448                         /* Heart bit LED */
 449                         VF610_PAD_PTE12__GPIO_117       0x1183
 450                         /* LEDS */
 451                         VF610_PAD_PTE15__GPIO_120       0x1183
 452                         VF610_PAD_PTA12__GPIO_5 0x1183
 453                         VF610_PAD_PTA16__GPIO_6 0x1183
 454                         VF610_PAD_PTE9__GPIO_114        0x1183
 455                         VF610_PAD_PTE20__GPIO_125       0x1183
 456                         VF610_PAD_PTE23__GPIO_128       0x1183
 457                         VF610_PAD_PTE16__GPIO_121       0x1183
 458                 >;
 459         };
 460
 461         pinctrl_gpio_spi: pinctrl-gpio-spi {
 462                 fsl,pins = <
 463                         VF610_PAD_PTB18__GPIO_40        0x1183
 464                         VF610_PAD_PTD10__GPIO_89        0x1183
 465                         VF610_PAD_PTD12__GPIO_91        0x1183
 466                 >;
 467         };
 468
 469         pinctrl_i2c2: i2c2grp {
 470                 fsl,pins = <
 471                         VF610_PAD_PTA22__I2C2_SCL               0x34df
 472                         VF610_PAD_PTA23__I2C2_SDA               0x34df
 473                 >;
 474         };
 475
 476         pinctrl_nfc: nfcgrp {
 477                 fsl,pins = <
 478                         VF610_PAD_PTD23__NF_IO7         0x28df
 479                         VF610_PAD_PTD22__NF_IO6         0x28df
 480                         VF610_PAD_PTD21__NF_IO5         0x28df
 481                         VF610_PAD_PTD20__NF_IO4         0x28df
 482                         VF610_PAD_PTD19__NF_IO3         0x28df
 483                         VF610_PAD_PTD18__NF_IO2         0x28df
 484                         VF610_PAD_PTD17__NF_IO1         0x28df
 485                         VF610_PAD_PTD16__NF_IO0         0x28df
 486                         VF610_PAD_PTB24__NF_WE_B                0x28c2
 487                         VF610_PAD_PTB25__NF_CE0_B               0x28c2
 488                         VF610_PAD_PTB27__NF_RE_B                0x28c2
 489                         VF610_PAD_PTC26__NF_RB_B                0x283d
 490                         VF610_PAD_PTC27__NF_ALE         0x28c2
 491                         VF610_PAD_PTC28__NF_CLE         0x28c2
 492                 >;
 493         };
 494
 495         pinctrl_qspi0: qspi0grp {
 496                 fsl,pins = <
 497                         VF610_PAD_PTD0__QSPI0_A_QSCK    0x397f
 498                         VF610_PAD_PTD1__QSPI0_A_CS0     0x397f
 499                         VF610_PAD_PTD2__QSPI0_A_DATA3   0x397f
 500                         VF610_PAD_PTD3__QSPI0_A_DATA2   0x397f
 501                         VF610_PAD_PTD4__QSPI0_A_DATA1   0x397f
 502                         VF610_PAD_PTD5__QSPI0_A_DATA0   0x397f
 503                         VF610_PAD_PTD7__QSPI0_B_QSCK    0x397f
 504                         VF610_PAD_PTD8__QSPI0_B_CS0     0x397f
 505                         VF610_PAD_PTD11__QSPI0_B_DATA1  0x397f
 506                         VF610_PAD_PTD12__QSPI0_B_DATA0  0x397f
 507                 >;
 508         };
 509
 510         pinctrl_uart0: uart0grp {
 511                 fsl,pins = <
 512                         VF610_PAD_PTB10__UART0_TX               0x21a2
 513                         VF610_PAD_PTB11__UART0_RX               0x21a1
 514                 >;
 515         };
 516
 517         pinctrl_uart1: uart1grp {
 518                 fsl,pins = <
 519                         VF610_PAD_PTB4__UART1_TX                0x21a2
 520                         VF610_PAD_PTB5__UART1_RX                0x21a1
 521                 >;
 522         };
 523
 524         pinctrl_uart2: uart2grp {
 525                 fsl,pins = <
 526                         VF610_PAD_PTB6__UART2_TX                0x21a2
 527                         VF610_PAD_PTB7__UART2_RX                0x21a1
 528                 >;
 529         };
 530
 531         pinctrl_uart3: uart3grp {
 532                 fsl,pins = <
 533                         VF610_PAD_PTA20__UART3_TX               0x21a2
 534                         VF610_PAD_PTA21__UART3_RX               0x21a1
 535                 >;
 536         };
 537 };