1 // SPDX-License-Identifier: GPL-2.0
3 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
5 * Copyright (C) 2018 Renesas Electronics Europe Limited
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
13 compatible = "renesas,r9a06g032";
23 compatible = "arm,cortex-a7";
25 clocks = <&sysctrl R9A06G032_CLK_A7MP>;
30 compatible = "arm,cortex-a7";
32 clocks = <&sysctrl R9A06G032_CLK_A7MP>;
33 enable-method = "renesas,r9a06g032-smp";
34 cpu-release-addr = <0 0x4000c204>;
38 ext_jtag_clk: extjtagclk {
40 compatible = "fixed-clock";
41 clock-frequency = <0>;
46 compatible = "fixed-clock";
47 clock-frequency = <40000000>;
50 ext_rgmii_ref: extrgmiiref {
52 compatible = "fixed-clock";
53 clock-frequency = <0>;
56 ext_rtc_clk: extrtcclk {
58 compatible = "fixed-clock";
59 clock-frequency = <0>;
63 compatible = "simple-bus";
66 interrupt-parent = <&gic>;
70 compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
71 reg = <0x40006000 0x1000>;
72 interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
73 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
74 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
75 interrupt-names = "alarm", "timer", "pps";
76 clocks = <&sysctrl R9A06G032_HCLK_RTC>;
78 power-domains = <&sysctrl>;
82 wdt0: watchdog@40008000 {
83 compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
84 reg = <0x40008000 0x1000>;
85 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
86 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
90 wdt1: watchdog@40009000 {
91 compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
92 reg = <0x40009000 0x1000>;
93 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
94 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
98 sysctrl: system-controller@4000c000 {
99 compatible = "renesas,r9a06g032-sysctrl";
100 reg = <0x4000c000 0x1000>;
103 #power-domain-cells = <0>;
105 clocks = <&ext_mclk>, <&ext_rtc_clk>,
106 <&ext_jtag_clk>, <&ext_rgmii_ref>;
107 clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
108 #address-cells = <1>;
111 dmamux: dma-router@a0 {
112 compatible = "renesas,rzn1-dmamux";
116 dma-masters = <&dma0 &dma1>;
121 compatible = "renesas,r9a06g032-usbf", "renesas,rzn1-usbf";
122 reg = <0x4001e000 0x2000>;
123 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&sysctrl R9A06G032_HCLK_USBF>,
126 <&sysctrl R9A06G032_HCLK_USBPM>;
127 clock-names = "hclkf", "hclkpm";
128 power-domains = <&sysctrl>;
132 pci_usb: pci@40030000 {
133 compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
135 clocks = <&sysctrl R9A06G032_HCLK_USBH>,
136 <&sysctrl R9A06G032_HCLK_USBPM>,
137 <&sysctrl R9A06G032_CLK_PCI_USB>;
138 clock-names = "hclkh", "hclkpm", "pciclk";
139 power-domains = <&sysctrl>;
140 reg = <0x40030000 0xc00>,
142 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
146 #address-cells = <3>;
148 #interrupt-cells = <1>;
149 ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>;
150 /* Should map all possible DDR as inbound ranges, but
151 * the IP only supports a 256MB, 512MB, or 1GB window.
152 * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
154 dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
155 interrupt-map-mask = <0xf800 0 0 0x7>;
156 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
157 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
158 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
161 reg = <0x800 0 0 0 0>;
167 reg = <0x1000 0 0 0 0>;
173 uart0: serial@40060000 {
174 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
175 reg = <0x40060000 0x400>;
176 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
179 clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
180 clock-names = "baudclk", "apb_pclk";
184 uart1: serial@40061000 {
185 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
186 reg = <0x40061000 0x400>;
187 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
191 clock-names = "baudclk", "apb_pclk";
195 uart2: serial@40062000 {
196 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
197 reg = <0x40062000 0x400>;
198 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
202 clock-names = "baudclk", "apb_pclk";
206 uart3: serial@50000000 {
207 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
208 reg = <0x50000000 0x400>;
209 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
213 clock-names = "baudclk", "apb_pclk";
214 dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>;
215 dma-names = "rx", "tx";
219 uart4: serial@50001000 {
220 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
221 reg = <0x50001000 0x400>;
222 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
226 clock-names = "baudclk", "apb_pclk";
227 dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>;
228 dma-names = "rx", "tx";
232 uart5: serial@50002000 {
233 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
234 reg = <0x50002000 0x400>;
235 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
239 clock-names = "baudclk", "apb_pclk";
240 dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>;
241 dma-names = "rx", "tx";
245 uart6: serial@50003000 {
246 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
247 reg = <0x50003000 0x400>;
248 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
252 clock-names = "baudclk", "apb_pclk";
253 dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>;
254 dma-names = "rx", "tx";
258 uart7: serial@50004000 {
259 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
260 reg = <0x50004000 0x400>;
261 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
265 clock-names = "baudclk", "apb_pclk";
266 dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>;
267 dma-names = "rx", "tx";
271 pinctrl: pinctrl@40067000 {
272 compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
273 reg = <0x40067000 0x1000>, <0x51000000 0x480>;
274 clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
279 nand_controller: nand-controller@40102000 {
280 compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc";
281 reg = <0x40102000 0x2000>;
282 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
284 clock-names = "hclk", "eclk";
285 power-domains = <&sysctrl>;
286 #address-cells = <1>;
291 dma0: dma-controller@40104000 {
292 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
293 reg = <0x40104000 0x1000>;
294 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
295 clock-names = "hclk";
296 clocks = <&sysctrl R9A06G032_HCLK_DMA0>;
301 block_size = <0xfff>;
305 dma1: dma-controller@40105000 {
306 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
307 reg = <0x40105000 0x1000>;
308 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
309 clock-names = "hclk";
310 clocks = <&sysctrl R9A06G032_HCLK_DMA1>;
315 block_size = <0xfff>;
319 gmac2: ethernet@44002000 {
320 compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";
321 reg = <0x44002000 0x2000>;
322 interrupt-parent = <&gic>;
323 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
326 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
327 clocks = <&sysctrl R9A06G032_HCLK_GMAC1>;
328 clock-names = "stmmaceth";
329 power-domains = <&sysctrl>;
330 snps,multicast-filter-bins = <256>;
331 snps,perfect-filter-entries = <128>;
332 tx-fifo-depth = <2048>;
333 rx-fifo-depth = <4096>;
337 eth_miic: eth-miic@44030000 {
338 compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic";
339 #address-cells = <1>;
341 reg = <0x44030000 0x10000>;
342 clocks = <&sysctrl R9A06G032_CLK_MII_REF>,
343 <&sysctrl R9A06G032_CLK_RGMII_REF>,
344 <&sysctrl R9A06G032_CLK_RMII_REF>,
345 <&sysctrl R9A06G032_HCLK_SWITCH_RG>;
346 clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
347 power-domains = <&sysctrl>;
350 mii_conv1: mii-conv@1 {
355 mii_conv2: mii-conv@2 {
360 mii_conv3: mii-conv@3 {
365 mii_conv4: mii-conv@4 {
370 mii_conv5: mii-conv@5 {
376 switch: switch@44050000 {
377 compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";
378 reg = <0x44050000 0x10000>;
379 clocks = <&sysctrl R9A06G032_HCLK_SWITCH>,
380 <&sysctrl R9A06G032_CLK_SWITCH>;
381 clock-names = "hclk", "clk";
382 power-domains = <&sysctrl>;
386 #address-cells = <1>;
389 switch_port0: port@0 {
391 pcs-handle = <&mii_conv5>;
395 switch_port1: port@1 {
397 pcs-handle = <&mii_conv4>;
401 switch_port2: port@2 {
403 pcs-handle = <&mii_conv3>;
407 switch_port3: port@3 {
409 pcs-handle = <&mii_conv2>;
413 switch_port4: port@4 {
417 phy-mode = "internal";
427 gic: interrupt-controller@44101000 {
428 compatible = "arm,gic-400", "arm,cortex-a7-gic";
429 interrupt-controller;
430 #interrupt-cells = <3>;
431 reg = <0x44101000 0x1000>, /* Distributer */
432 <0x44102000 0x2000>, /* CPU interface */
433 <0x44104000 0x2000>, /* Virt interface control */
434 <0x44106000 0x2000>; /* Virt CPU interface */
436 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
440 compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
441 reg = <0x52104000 0x800>;
443 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&sysctrl R9A06G032_HCLK_CAN0>;
445 power-domains = <&sysctrl>;
450 compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
451 reg = <0x52105000 0x800>;
453 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&sysctrl R9A06G032_HCLK_CAN1>;
455 power-domains = <&sysctrl>;
461 compatible = "arm,armv7-timer";
462 interrupt-parent = <&gic>;
463 arm,cpu-registers-not-fw-configured;
466 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
467 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
468 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
469 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
474 compatible = "usb-nop-xceiv";