2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
48 #include "../armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
59 compatible = "fixed-clock";
60 clock-frequency = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
71 compatible = "fixed-clock";
72 clock-frequency = <32000>;
75 clk_i2s_ckin: i2s-ckin {
77 compatible = "fixed-clock";
78 clock-frequency = <0>;
83 romem: efuse@1fff7800 {
84 compatible = "st,stm32f4-otp";
85 reg = <0x1fff7800 0x400>;
96 timers2: timers@40000000 {
99 compatible = "st,stm32-timers";
100 reg = <0x40000000 0x400>;
101 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
106 compatible = "st,stm32-pwm";
112 compatible = "st,stm32-timer-trigger";
118 timers3: timers@40000400 {
119 #address-cells = <1>;
121 compatible = "st,stm32-timers";
122 reg = <0x40000400 0x400>;
123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
128 compatible = "st,stm32-pwm";
134 compatible = "st,stm32-timer-trigger";
140 timers4: timers@40000800 {
141 #address-cells = <1>;
143 compatible = "st,stm32-timers";
144 reg = <0x40000800 0x400>;
145 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
150 compatible = "st,stm32-pwm";
156 compatible = "st,stm32-timer-trigger";
162 timers5: timers@40000c00 {
163 #address-cells = <1>;
165 compatible = "st,stm32-timers";
166 reg = <0x40000C00 0x400>;
167 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
172 compatible = "st,stm32-pwm";
178 compatible = "st,stm32-timer-trigger";
184 timers6: timers@40001000 {
185 #address-cells = <1>;
187 compatible = "st,stm32-timers";
188 reg = <0x40001000 0x400>;
189 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
194 compatible = "st,stm32-timer-trigger";
200 timers7: timers@40001400 {
201 #address-cells = <1>;
203 compatible = "st,stm32-timers";
204 reg = <0x40001400 0x400>;
205 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
210 compatible = "st,stm32-timer-trigger";
216 timers12: timers@40001800 {
217 #address-cells = <1>;
219 compatible = "st,stm32-timers";
220 reg = <0x40001800 0x400>;
221 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
226 compatible = "st,stm32-pwm";
232 compatible = "st,stm32-timer-trigger";
238 timers13: timers@40001c00 {
239 compatible = "st,stm32-timers";
240 reg = <0x40001C00 0x400>;
241 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
246 compatible = "st,stm32-pwm";
252 timers14: timers@40002000 {
253 compatible = "st,stm32-timers";
254 reg = <0x40002000 0x400>;
255 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
260 compatible = "st,stm32-pwm";
267 compatible = "st,stm32-rtc";
268 reg = <0x40002800 0x400>;
269 clocks = <&rcc 1 CLK_RTC>;
270 assigned-clocks = <&rcc 1 CLK_RTC>;
271 assigned-clock-parents = <&rcc 1 CLK_LSE>;
272 interrupt-parent = <&exti>;
274 st,syscfg = <&pwrcfg 0x00 0x100>;
278 iwdg: watchdog@40003000 {
279 compatible = "st,stm32-iwdg";
280 reg = <0x40003000 0x400>;
287 #address-cells = <1>;
289 compatible = "st,stm32f4-spi";
290 reg = <0x40003800 0x400>;
292 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
297 #address-cells = <1>;
299 compatible = "st,stm32f4-spi";
300 reg = <0x40003c00 0x400>;
302 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
306 usart2: serial@40004400 {
307 compatible = "st,stm32-uart";
308 reg = <0x40004400 0x400>;
310 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
314 usart3: serial@40004800 {
315 compatible = "st,stm32-uart";
316 reg = <0x40004800 0x400>;
318 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
320 dmas = <&dma1 1 4 0x400 0x0>,
321 <&dma1 3 4 0x400 0x0>;
322 dma-names = "rx", "tx";
325 usart4: serial@40004c00 {
326 compatible = "st,stm32-uart";
327 reg = <0x40004c00 0x400>;
329 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
333 usart5: serial@40005000 {
334 compatible = "st,stm32-uart";
335 reg = <0x40005000 0x400>;
337 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
342 compatible = "st,stm32f4-i2c";
343 reg = <0x40005400 0x400>;
346 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
347 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
348 #address-cells = <1>;
354 compatible = "st,stm32f4-i2c";
355 reg = <0x40005c00 0x400>;
358 resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
359 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
360 #address-cells = <1>;
366 compatible = "st,stm32f4-bxcan";
367 reg = <0x40006400 0x200>;
368 interrupts = <19>, <20>, <21>, <22>;
369 interrupt-names = "tx", "rx0", "rx1", "sce";
370 resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
371 clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
377 gcan: gcan@40006600 {
378 compatible = "st,stm32f4-gcan", "syscon";
379 reg = <0x40006600 0x200>;
380 clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
384 compatible = "st,stm32f4-bxcan";
385 reg = <0x40006800 0x200>;
386 interrupts = <63>, <64>, <65>, <66>;
387 interrupt-names = "tx", "rx0", "rx1", "sce";
388 resets = <&rcc STM32F4_APB1_RESET(CAN2)>;
389 clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>;
396 compatible = "st,stm32f4-dac-core";
397 reg = <0x40007400 0x400>;
398 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
399 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
400 clock-names = "pclk";
401 #address-cells = <1>;
406 compatible = "st,stm32-dac";
407 #io-channel-cells = <1>;
413 compatible = "st,stm32-dac";
414 #io-channel-cells = <1>;
420 usart7: serial@40007800 {
421 compatible = "st,stm32-uart";
422 reg = <0x40007800 0x400>;
424 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
428 usart8: serial@40007c00 {
429 compatible = "st,stm32-uart";
430 reg = <0x40007c00 0x400>;
432 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
436 timers1: timers@40010000 {
437 #address-cells = <1>;
439 compatible = "st,stm32-timers";
440 reg = <0x40010000 0x400>;
441 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
446 compatible = "st,stm32-pwm";
452 compatible = "st,stm32-timer-trigger";
458 timers8: timers@40010400 {
459 #address-cells = <1>;
461 compatible = "st,stm32-timers";
462 reg = <0x40010400 0x400>;
463 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
468 compatible = "st,stm32-pwm";
474 compatible = "st,stm32-timer-trigger";
480 usart1: serial@40011000 {
481 compatible = "st,stm32-uart";
482 reg = <0x40011000 0x400>;
484 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
486 dmas = <&dma2 2 4 0x400 0x0>,
487 <&dma2 7 4 0x400 0x0>;
488 dma-names = "rx", "tx";
491 usart6: serial@40011400 {
492 compatible = "st,stm32-uart";
493 reg = <0x40011400 0x400>;
495 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
500 compatible = "st,stm32f4-adc-core";
501 reg = <0x40012000 0x400>;
503 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
505 interrupt-controller;
506 #interrupt-cells = <1>;
507 #address-cells = <1>;
512 compatible = "st,stm32f4-adc";
513 #io-channel-cells = <1>;
515 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
516 interrupt-parent = <&adc>;
518 dmas = <&dma2 0 0 0x400 0x0>;
524 compatible = "st,stm32f4-adc";
525 #io-channel-cells = <1>;
527 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
528 interrupt-parent = <&adc>;
530 dmas = <&dma2 3 1 0x400 0x0>;
536 compatible = "st,stm32f4-adc";
537 #io-channel-cells = <1>;
539 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
540 interrupt-parent = <&adc>;
542 dmas = <&dma2 1 2 0x400 0x0>;
549 compatible = "arm,pl180", "arm,primecell";
550 arm,primecell-periphid = <0x00880180>;
551 reg = <0x40012c00 0x400>;
552 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
553 clock-names = "apb_pclk";
555 max-frequency = <48000000>;
560 #address-cells = <1>;
562 compatible = "st,stm32f4-spi";
563 reg = <0x40013000 0x400>;
565 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
570 #address-cells = <1>;
572 compatible = "st,stm32f4-spi";
573 reg = <0x40013400 0x400>;
575 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
579 syscfg: syscon@40013800 {
580 compatible = "st,stm32-syscfg", "syscon";
581 reg = <0x40013800 0x400>;
584 exti: interrupt-controller@40013c00 {
585 compatible = "st,stm32-exti";
586 interrupt-controller;
587 #interrupt-cells = <2>;
588 reg = <0x40013C00 0x400>;
589 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
592 timers9: timers@40014000 {
593 #address-cells = <1>;
595 compatible = "st,stm32-timers";
596 reg = <0x40014000 0x400>;
597 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
602 compatible = "st,stm32-pwm";
608 compatible = "st,stm32-timer-trigger";
614 timers10: timers@40014400 {
615 compatible = "st,stm32-timers";
616 reg = <0x40014400 0x400>;
617 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
622 compatible = "st,stm32-pwm";
628 timers11: timers@40014800 {
629 compatible = "st,stm32-timers";
630 reg = <0x40014800 0x400>;
631 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
636 compatible = "st,stm32-pwm";
643 #address-cells = <1>;
645 compatible = "st,stm32f4-spi";
646 reg = <0x40015000 0x400>;
648 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
649 dmas = <&dma2 3 2 0x400 0x0>,
650 <&dma2 4 2 0x400 0x0>;
651 dma-names = "rx", "tx";
656 #address-cells = <1>;
658 compatible = "st,stm32f4-spi";
659 reg = <0x40015400 0x400>;
661 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
665 pwrcfg: power-config@40007000 {
666 compatible = "st,stm32-power-config", "syscon";
667 reg = <0x40007000 0x400>;
670 ltdc: display-controller@40016800 {
671 compatible = "st,stm32-ltdc";
672 reg = <0x40016800 0x200>;
673 interrupts = <88>, <89>;
674 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
675 clocks = <&rcc 1 CLK_LCD>;
681 compatible = "st,stm32f4-crc";
682 reg = <0x40023000 0x400>;
683 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
690 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
691 reg = <0x40023800 0x400>;
692 clocks = <&clk_hse>, <&clk_i2s_ckin>;
693 st,syscfg = <&pwrcfg>;
694 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
695 assigned-clock-rates = <1000000>;
698 dma1: dma-controller@40026000 {
699 compatible = "st,stm32-dma";
700 reg = <0x40026000 0x400>;
709 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
713 dma2: dma-controller@40026400 {
714 compatible = "st,stm32-dma";
715 reg = <0x40026400 0x400>;
724 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
729 mac: ethernet@40028000 {
730 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
731 reg = <0x40028000 0x8000>;
732 reg-names = "stmmaceth";
734 interrupt-names = "macirq";
735 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
736 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
737 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
738 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
739 st,syscon = <&syscfg 0x4>;
745 dma2d: dma2d@4002b000 {
746 compatible = "st,stm32-dma2d";
747 reg = <0x4002b000 0xc00>;
749 resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
750 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
751 clock-names = "dma2d";
755 usbotg_hs: usb@40040000 {
756 compatible = "snps,dwc2";
757 reg = <0x40040000 0x40000>;
759 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
764 usbotg_fs: usb@50000000 {
765 compatible = "st,stm32f4x9-fsotg";
766 reg = <0x50000000 0x40000>;
768 clocks = <&rcc 0 39>;
773 dcmi: dcmi@50050000 {
774 compatible = "st,stm32-dcmi";
775 reg = <0x50050000 0x400>;
777 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
778 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
779 clock-names = "mclk";
780 pinctrl-names = "default";
781 pinctrl-0 = <&dcmi_pins>;
782 dmas = <&dma2 1 1 0x414 0x3>;
788 compatible = "st,stm32-rng";
789 reg = <0x50060800 0x400>;
790 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
797 clocks = <&rcc 1 SYSTICK>;