]> git.ipfire.org Git - thirdparty/u-boot.git/blob - src/arm/st/stm32mp151.dtsi
projects / thirdparty / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Squashed 'dts/upstream/' changes from aaba2d45dc2a..b35b9bd1d4ee
[thirdparty/u-boot.git] / src / arm / st / stm32mp151.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
9
10 / {
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a7";
20 clock-frequency = <650000000>;
21 device_type = "cpu";
22 reg = <0>;
23 };
24 };
25
26 arm-pmu {
27 compatible = "arm,cortex-a7-pmu";
28 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
29 interrupt-affinity = <&cpu0>;
30 interrupt-parent = <&intc>;
31 };
32
33 psci {
34 compatible = "arm,psci-1.0";
35 method = "smc";
36 };
37
38 intc: interrupt-controller@a0021000 {
39 compatible = "arm,cortex-a7-gic";
40 #interrupt-cells = <3>;
41 interrupt-controller;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
44 };
45
46 timer {
47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&intc>;
53 };
54
55 clocks {
56 clk_hse: clk-hse {
57 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <24000000>;
60 };
61
62 clk_hsi: clk-hsi {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <64000000>;
66 };
67
68 clk_lse: clk-lse {
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
71 clock-frequency = <32768>;
72 };
73
74 clk_lsi: clk-lsi {
75 #clock-cells = <0>;
76 compatible = "fixed-clock";
77 clock-frequency = <32000>;
78 };
79
80 clk_csi: clk-csi {
81 #clock-cells = <0>;
82 compatible = "fixed-clock";
83 clock-frequency = <4000000>;
84 };
85 };
86
87 thermal-zones {
88 cpu_thermal: cpu-thermal {
89 polling-delay-passive = <0>;
90 polling-delay = <0>;
91 thermal-sensors = <&dts>;
92
93 trips {
94 cpu_alert1: cpu-alert1 {
95 temperature = <85000>;
96 hysteresis = <0>;
97 type = "passive";
98 };
99
100 cpu-crit {
101 temperature = <120000>;
102 hysteresis = <0>;
103 type = "critical";
104 };
105 };
106
107 cooling-maps {
108 };
109 };
110 };
111
112 booster: regulator-booster {
113 compatible = "st,stm32mp1-booster";
114 st,syscfg = <&syscfg>;
115 status = "disabled";
116 };
117
118 soc {
119 compatible = "simple-bus";
120 #address-cells = <1>;
121 #size-cells = <1>;
122 interrupt-parent = <&intc>;
123 ranges;
124
125 timers2: timer@40000000 {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 compatible = "st,stm32-timers";
129 reg = <0x40000000 0x400>;
130 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
131 interrupt-names = "global";
132 clocks = <&rcc TIM2_K>;
133 clock-names = "int";
134 dmas = <&dmamux1 18 0x400 0x1>,
135 <&dmamux1 19 0x400 0x1>,
136 <&dmamux1 20 0x400 0x1>,
137 <&dmamux1 21 0x400 0x1>,
138 <&dmamux1 22 0x400 0x1>;
139 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
140 status = "disabled";
141
142 pwm {
143 compatible = "st,stm32-pwm";
144 #pwm-cells = <3>;
145 status = "disabled";
146 };
147
148 timer@1 {
149 compatible = "st,stm32h7-timer-trigger";
150 reg = <1>;
151 status = "disabled";
152 };
153
154 counter {
155 compatible = "st,stm32-timer-counter";
156 status = "disabled";
157 };
158 };
159
160 timers3: timer@40001000 {
161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "st,stm32-timers";
164 reg = <0x40001000 0x400>;
165 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
166 interrupt-names = "global";
167 clocks = <&rcc TIM3_K>;
168 clock-names = "int";
169 dmas = <&dmamux1 23 0x400 0x1>,
170 <&dmamux1 24 0x400 0x1>,
171 <&dmamux1 25 0x400 0x1>,
172 <&dmamux1 26 0x400 0x1>,
173 <&dmamux1 27 0x400 0x1>,
174 <&dmamux1 28 0x400 0x1>;
175 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
176 status = "disabled";
177
178 pwm {
179 compatible = "st,stm32-pwm";
180 #pwm-cells = <3>;
181 status = "disabled";
182 };
183
184 timer@2 {
185 compatible = "st,stm32h7-timer-trigger";
186 reg = <2>;
187 status = "disabled";
188 };
189
190 counter {
191 compatible = "st,stm32-timer-counter";
192 status = "disabled";
193 };
194 };
195
196 timers4: timer@40002000 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "st,stm32-timers";
200 reg = <0x40002000 0x400>;
201 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-names = "global";
203 clocks = <&rcc TIM4_K>;
204 clock-names = "int";
205 dmas = <&dmamux1 29 0x400 0x1>,
206 <&dmamux1 30 0x400 0x1>,
207 <&dmamux1 31 0x400 0x1>,
208 <&dmamux1 32 0x400 0x1>;
209 dma-names = "ch1", "ch2", "ch3", "ch4";
210 status = "disabled";
211
212 pwm {
213 compatible = "st,stm32-pwm";
214 #pwm-cells = <3>;
215 status = "disabled";
216 };
217
218 timer@3 {
219 compatible = "st,stm32h7-timer-trigger";
220 reg = <3>;
221 status = "disabled";
222 };
223
224 counter {
225 compatible = "st,stm32-timer-counter";
226 status = "disabled";
227 };
228 };
229
230 timers5: timer@40003000 {
231 #address-cells = <1>;
232 #size-cells = <0>;
233 compatible = "st,stm32-timers";
234 reg = <0x40003000 0x400>;
235 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
236 interrupt-names = "global";
237 clocks = <&rcc TIM5_K>;
238 clock-names = "int";
239 dmas = <&dmamux1 55 0x400 0x1>,
240 <&dmamux1 56 0x400 0x1>,
241 <&dmamux1 57 0x400 0x1>,
242 <&dmamux1 58 0x400 0x1>,
243 <&dmamux1 59 0x400 0x1>,
244 <&dmamux1 60 0x400 0x1>;
245 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
246 status = "disabled";
247
248 pwm {
249 compatible = "st,stm32-pwm";
250 #pwm-cells = <3>;
251 status = "disabled";
252 };
253
254 timer@4 {
255 compatible = "st,stm32h7-timer-trigger";
256 reg = <4>;
257 status = "disabled";
258 };
259
260 counter {
261 compatible = "st,stm32-timer-counter";
262 status = "disabled";
263 };
264 };
265
266 timers6: timer@40004000 {
267 #address-cells = <1>;
268 #size-cells = <0>;
269 compatible = "st,stm32-timers";
270 reg = <0x40004000 0x400>;
271 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
272 interrupt-names = "global";
273 clocks = <&rcc TIM6_K>;
274 clock-names = "int";
275 dmas = <&dmamux1 69 0x400 0x1>;
276 dma-names = "up";
277 status = "disabled";
278
279 timer@5 {
280 compatible = "st,stm32h7-timer-trigger";
281 reg = <5>;
282 status = "disabled";
283 };
284 };
285
286 timers7: timer@40005000 {
287 #address-cells = <1>;
288 #size-cells = <0>;
289 compatible = "st,stm32-timers";
290 reg = <0x40005000 0x400>;
291 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
292 interrupt-names = "global";
293 clocks = <&rcc TIM7_K>;
294 clock-names = "int";
295 dmas = <&dmamux1 70 0x400 0x1>;
296 dma-names = "up";
297 status = "disabled";
298
299 timer@6 {
300 compatible = "st,stm32h7-timer-trigger";
301 reg = <6>;
302 status = "disabled";
303 };
304 };
305
306 timers12: timer@40006000 {
307 #address-cells = <1>;
308 #size-cells = <0>;
309 compatible = "st,stm32-timers";
310 reg = <0x40006000 0x400>;
311 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
312 interrupt-names = "global";
313 clocks = <&rcc TIM12_K>;
314 clock-names = "int";
315 status = "disabled";
316
317 pwm {
318 compatible = "st,stm32-pwm";
319 #pwm-cells = <3>;
320 status = "disabled";
321 };
322
323 timer@11 {
324 compatible = "st,stm32h7-timer-trigger";
325 reg = <11>;
326 status = "disabled";
327 };
328 };
329
330 timers13: timer@40007000 {
331 #address-cells = <1>;
332 #size-cells = <0>;
333 compatible = "st,stm32-timers";
334 reg = <0x40007000 0x400>;
335 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
336 interrupt-names = "global";
337 clocks = <&rcc TIM13_K>;
338 clock-names = "int";
339 status = "disabled";
340
341 pwm {
342 compatible = "st,stm32-pwm";
343 #pwm-cells = <3>;
344 status = "disabled";
345 };
346
347 timer@12 {
348 compatible = "st,stm32h7-timer-trigger";
349 reg = <12>;
350 status = "disabled";
351 };
352 };
353
354 timers14: timer@40008000 {
355 #address-cells = <1>;
356 #size-cells = <0>;
357 compatible = "st,stm32-timers";
358 reg = <0x40008000 0x400>;
359 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
360 interrupt-names = "global";
361 clocks = <&rcc TIM14_K>;
362 clock-names = "int";
363 status = "disabled";
364
365 pwm {
366 compatible = "st,stm32-pwm";
367 #pwm-cells = <3>;
368 status = "disabled";
369 };
370
371 timer@13 {
372 compatible = "st,stm32h7-timer-trigger";
373 reg = <13>;
374 status = "disabled";
375 };
376 };
377
378 lptimer1: timer@40009000 {
379 #address-cells = <1>;
380 #size-cells = <0>;
381 compatible = "st,stm32-lptimer";
382 reg = <0x40009000 0x400>;
383 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&rcc LPTIM1_K>;
385 clock-names = "mux";
386 wakeup-source;
387 status = "disabled";
388
389 pwm {
390 compatible = "st,stm32-pwm-lp";
391 #pwm-cells = <3>;
392 status = "disabled";
393 };
394
395 trigger@0 {
396 compatible = "st,stm32-lptimer-trigger";
397 reg = <0>;
398 status = "disabled";
399 };
400
401 counter {
402 compatible = "st,stm32-lptimer-counter";
403 status = "disabled";
404 };
405 };
406
407 spi2: spi@4000b000 {
408 #address-cells = <1>;
409 #size-cells = <0>;
410 compatible = "st,stm32h7-spi";
411 reg = <0x4000b000 0x400>;
412 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&rcc SPI2_K>;
414 resets = <&rcc SPI2_R>;
415 dmas = <&dmamux1 39 0x400 0x05>,
416 <&dmamux1 40 0x400 0x05>;
417 dma-names = "rx", "tx";
418 status = "disabled";
419 };
420
421 i2s2: audio-controller@4000b000 {
422 compatible = "st,stm32h7-i2s";
423 #sound-dai-cells = <0>;
424 reg = <0x4000b000 0x400>;
425 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
426 dmas = <&dmamux1 39 0x400 0x01>,
427 <&dmamux1 40 0x400 0x01>;
428 dma-names = "rx", "tx";
429 status = "disabled";
430 };
431
432 spi3: spi@4000c000 {
433 #address-cells = <1>;
434 #size-cells = <0>;
435 compatible = "st,stm32h7-spi";
436 reg = <0x4000c000 0x400>;
437 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&rcc SPI3_K>;
439 resets = <&rcc SPI3_R>;
440 dmas = <&dmamux1 61 0x400 0x05>,
441 <&dmamux1 62 0x400 0x05>;
442 dma-names = "rx", "tx";
443 status = "disabled";
444 };
445
446 i2s3: audio-controller@4000c000 {
447 compatible = "st,stm32h7-i2s";
448 #sound-dai-cells = <0>;
449 reg = <0x4000c000 0x400>;
450 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
451 dmas = <&dmamux1 61 0x400 0x01>,
452 <&dmamux1 62 0x400 0x01>;
453 dma-names = "rx", "tx";
454 status = "disabled";
455 };
456
457 spdifrx: audio-controller@4000d000 {
458 compatible = "st,stm32h7-spdifrx";
459 #sound-dai-cells = <0>;
460 reg = <0x4000d000 0x400>;
461 clocks = <&rcc SPDIF_K>;
462 clock-names = "kclk";
463 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
464 dmas = <&dmamux1 93 0x400 0x01>,
465 <&dmamux1 94 0x400 0x01>;
466 dma-names = "rx", "rx-ctrl";
467 status = "disabled";
468 };
469
470 usart2: serial@4000e000 {
471 compatible = "st,stm32h7-uart";
472 reg = <0x4000e000 0x400>;
473 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&rcc USART2_K>;
475 wakeup-source;
476 dmas = <&dmamux1 43 0x400 0x15>,
477 <&dmamux1 44 0x400 0x11>;
478 dma-names = "rx", "tx";
479 status = "disabled";
480 };
481
482 usart3: serial@4000f000 {
483 compatible = "st,stm32h7-uart";
484 reg = <0x4000f000 0x400>;
485 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&rcc USART3_K>;
487 wakeup-source;
488 dmas = <&dmamux1 45 0x400 0x15>,
489 <&dmamux1 46 0x400 0x11>;
490 dma-names = "rx", "tx";
491 status = "disabled";
492 };
493
494 uart4: serial@40010000 {
495 compatible = "st,stm32h7-uart";
496 reg = <0x40010000 0x400>;
497 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&rcc UART4_K>;
499 wakeup-source;
500 dmas = <&dmamux1 63 0x400 0x15>,
501 <&dmamux1 64 0x400 0x11>;
502 dma-names = "rx", "tx";
503 status = "disabled";
504 };
505
506 uart5: serial@40011000 {
507 compatible = "st,stm32h7-uart";
508 reg = <0x40011000 0x400>;
509 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&rcc UART5_K>;
511 wakeup-source;
512 dmas = <&dmamux1 65 0x400 0x15>,
513 <&dmamux1 66 0x400 0x11>;
514 dma-names = "rx", "tx";
515 status = "disabled";
516 };
517
518 i2c1: i2c@40012000 {
519 compatible = "st,stm32mp15-i2c";
520 reg = <0x40012000 0x400>;
521 interrupt-names = "event", "error";
522 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&rcc I2C1_K>;
525 resets = <&rcc I2C1_R>;
526 #address-cells = <1>;
527 #size-cells = <0>;
528 st,syscfg-fmp = <&syscfg 0x4 0x1>;
529 wakeup-source;
530 i2c-analog-filter;
531 status = "disabled";
532 };
533
534 i2c2: i2c@40013000 {
535 compatible = "st,stm32mp15-i2c";
536 reg = <0x40013000 0x400>;
537 interrupt-names = "event", "error";
538 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&rcc I2C2_K>;
541 resets = <&rcc I2C2_R>;
542 #address-cells = <1>;
543 #size-cells = <0>;
544 st,syscfg-fmp = <&syscfg 0x4 0x2>;
545 wakeup-source;
546 i2c-analog-filter;
547 status = "disabled";
548 };
549
550 i2c3: i2c@40014000 {
551 compatible = "st,stm32mp15-i2c";
552 reg = <0x40014000 0x400>;
553 interrupt-names = "event", "error";
554 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&rcc I2C3_K>;
557 resets = <&rcc I2C3_R>;
558 #address-cells = <1>;
559 #size-cells = <0>;
560 st,syscfg-fmp = <&syscfg 0x4 0x4>;
561 wakeup-source;
562 i2c-analog-filter;
563 status = "disabled";
564 };
565
566 i2c5: i2c@40015000 {
567 compatible = "st,stm32mp15-i2c";
568 reg = <0x40015000 0x400>;
569 interrupt-names = "event", "error";
570 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&rcc I2C5_K>;
573 resets = <&rcc I2C5_R>;
574 #address-cells = <1>;
575 #size-cells = <0>;
576 st,syscfg-fmp = <&syscfg 0x4 0x10>;
577 wakeup-source;
578 i2c-analog-filter;
579 status = "disabled";
580 };
581
582 cec: cec@40016000 {
583 compatible = "st,stm32-cec";
584 reg = <0x40016000 0x400>;
585 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&rcc CEC_K>, <&rcc CEC>;
587 clock-names = "cec", "hdmi-cec";
588 status = "disabled";
589 };
590
591 dac: dac@40017000 {
592 compatible = "st,stm32h7-dac-core";
593 reg = <0x40017000 0x400>;
594 clocks = <&rcc DAC12>;
595 clock-names = "pclk";
596 #address-cells = <1>;
597 #size-cells = <0>;
598 status = "disabled";
599
600 dac1: dac@1 {
601 compatible = "st,stm32-dac";
602 #io-channel-cells = <1>;
603 reg = <1>;
604 status = "disabled";
605 };
606
607 dac2: dac@2 {
608 compatible = "st,stm32-dac";
609 #io-channel-cells = <1>;
610 reg = <2>;
611 status = "disabled";
612 };
613 };
614
615 uart7: serial@40018000 {
616 compatible = "st,stm32h7-uart";
617 reg = <0x40018000 0x400>;
618 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&rcc UART7_K>;
620 wakeup-source;
621 dmas = <&dmamux1 79 0x400 0x15>,
622 <&dmamux1 80 0x400 0x11>;
623 dma-names = "rx", "tx";
624 status = "disabled";
625 };
626
627 uart8: serial@40019000 {
628 compatible = "st,stm32h7-uart";
629 reg = <0x40019000 0x400>;
630 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&rcc UART8_K>;
632 wakeup-source;
633 dmas = <&dmamux1 81 0x400 0x15>,
634 <&dmamux1 82 0x400 0x11>;
635 dma-names = "rx", "tx";
636 status = "disabled";
637 };
638
639 timers1: timer@44000000 {
640 #address-cells = <1>;
641 #size-cells = <0>;
642 compatible = "st,stm32-timers";
643 reg = <0x44000000 0x400>;
644 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
648 interrupt-names = "brk", "up", "trg-com", "cc";
649 clocks = <&rcc TIM1_K>;
650 clock-names = "int";
651 dmas = <&dmamux1 11 0x400 0x1>,
652 <&dmamux1 12 0x400 0x1>,
653 <&dmamux1 13 0x400 0x1>,
654 <&dmamux1 14 0x400 0x1>,
655 <&dmamux1 15 0x400 0x1>,
656 <&dmamux1 16 0x400 0x1>,
657 <&dmamux1 17 0x400 0x1>;
658 dma-names = "ch1", "ch2", "ch3", "ch4",
659 "up", "trig", "com";
660 status = "disabled";
661
662 pwm {
663 compatible = "st,stm32-pwm";
664 #pwm-cells = <3>;
665 status = "disabled";
666 };
667
668 timer@0 {
669 compatible = "st,stm32h7-timer-trigger";
670 reg = <0>;
671 status = "disabled";
672 };
673
674 counter {
675 compatible = "st,stm32-timer-counter";
676 status = "disabled";
677 };
678 };
679
680 timers8: timer@44001000 {
681 #address-cells = <1>;
682 #size-cells = <0>;
683 compatible = "st,stm32-timers";
684 reg = <0x44001000 0x400>;
685 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
689 interrupt-names = "brk", "up", "trg-com", "cc";
690 clocks = <&rcc TIM8_K>;
691 clock-names = "int";
692 dmas = <&dmamux1 47 0x400 0x1>,
693 <&dmamux1 48 0x400 0x1>,
694 <&dmamux1 49 0x400 0x1>,
695 <&dmamux1 50 0x400 0x1>,
696 <&dmamux1 51 0x400 0x1>,
697 <&dmamux1 52 0x400 0x1>,
698 <&dmamux1 53 0x400 0x1>;
699 dma-names = "ch1", "ch2", "ch3", "ch4",
700 "up", "trig", "com";
701 status = "disabled";
702
703 pwm {
704 compatible = "st,stm32-pwm";
705 #pwm-cells = <3>;
706 status = "disabled";
707 };
708
709 timer@7 {
710 compatible = "st,stm32h7-timer-trigger";
711 reg = <7>;
712 status = "disabled";
713 };
714
715 counter {
716 compatible = "st,stm32-timer-counter";
717 status = "disabled";
718 };
719 };
720
721 usart6: serial@44003000 {
722 compatible = "st,stm32h7-uart";
723 reg = <0x44003000 0x400>;
724 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&rcc USART6_K>;
726 wakeup-source;
727 dmas = <&dmamux1 71 0x400 0x15>,
728 <&dmamux1 72 0x400 0x11>;
729 dma-names = "rx", "tx";
730 status = "disabled";
731 };
732
733 spi1: spi@44004000 {
734 #address-cells = <1>;
735 #size-cells = <0>;
736 compatible = "st,stm32h7-spi";
737 reg = <0x44004000 0x400>;
738 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&rcc SPI1_K>;
740 resets = <&rcc SPI1_R>;
741 dmas = <&dmamux1 37 0x400 0x05>,
742 <&dmamux1 38 0x400 0x05>;
743 dma-names = "rx", "tx";
744 status = "disabled";
745 };
746
747 i2s1: audio-controller@44004000 {
748 compatible = "st,stm32h7-i2s";
749 #sound-dai-cells = <0>;
750 reg = <0x44004000 0x400>;
751 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
752 dmas = <&dmamux1 37 0x400 0x01>,
753 <&dmamux1 38 0x400 0x01>;
754 dma-names = "rx", "tx";
755 status = "disabled";
756 };
757
758 spi4: spi@44005000 {
759 #address-cells = <1>;
760 #size-cells = <0>;
761 compatible = "st,stm32h7-spi";
762 reg = <0x44005000 0x400>;
763 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&rcc SPI4_K>;
765 resets = <&rcc SPI4_R>;
766 dmas = <&dmamux1 83 0x400 0x05>,
767 <&dmamux1 84 0x400 0x05>;
768 dma-names = "rx", "tx";
769 status = "disabled";
770 };
771
772 timers15: timer@44006000 {
773 #address-cells = <1>;
774 #size-cells = <0>;
775 compatible = "st,stm32-timers";
776 reg = <0x44006000 0x400>;
777 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
778 interrupt-names = "global";
779 clocks = <&rcc TIM15_K>;
780 clock-names = "int";
781 dmas = <&dmamux1 105 0x400 0x1>,
782 <&dmamux1 106 0x400 0x1>,
783 <&dmamux1 107 0x400 0x1>,
784 <&dmamux1 108 0x400 0x1>;
785 dma-names = "ch1", "up", "trig", "com";
786 status = "disabled";
787
788 pwm {
789 compatible = "st,stm32-pwm";
790 #pwm-cells = <3>;
791 status = "disabled";
792 };
793
794 timer@14 {
795 compatible = "st,stm32h7-timer-trigger";
796 reg = <14>;
797 status = "disabled";
798 };
799 };
800
801 timers16: timer@44007000 {
802 #address-cells = <1>;
803 #size-cells = <0>;
804 compatible = "st,stm32-timers";
805 reg = <0x44007000 0x400>;
806 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
807 interrupt-names = "global";
808 clocks = <&rcc TIM16_K>;
809 clock-names = "int";
810 dmas = <&dmamux1 109 0x400 0x1>,
811 <&dmamux1 110 0x400 0x1>;
812 dma-names = "ch1", "up";
813 status = "disabled";
814
815 pwm {
816 compatible = "st,stm32-pwm";
817 #pwm-cells = <3>;
818 status = "disabled";
819 };
820 timer@15 {
821 compatible = "st,stm32h7-timer-trigger";
822 reg = <15>;
823 status = "disabled";
824 };
825 };
826
827 timers17: timer@44008000 {
828 #address-cells = <1>;
829 #size-cells = <0>;
830 compatible = "st,stm32-timers";
831 reg = <0x44008000 0x400>;
832 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
833 interrupt-names = "global";
834 clocks = <&rcc TIM17_K>;
835 clock-names = "int";
836 dmas = <&dmamux1 111 0x400 0x1>,
837 <&dmamux1 112 0x400 0x1>;
838 dma-names = "ch1", "up";
839 status = "disabled";
840
841 pwm {
842 compatible = "st,stm32-pwm";
843 #pwm-cells = <3>;
844 status = "disabled";
845 };
846
847 timer@16 {
848 compatible = "st,stm32h7-timer-trigger";
849 reg = <16>;
850 status = "disabled";
851 };
852 };
853
854 spi5: spi@44009000 {
855 #address-cells = <1>;
856 #size-cells = <0>;
857 compatible = "st,stm32h7-spi";
858 reg = <0x44009000 0x400>;
859 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
860 clocks = <&rcc SPI5_K>;
861 resets = <&rcc SPI5_R>;
862 dmas = <&dmamux1 85 0x400 0x05>,
863 <&dmamux1 86 0x400 0x05>;
864 dma-names = "rx", "tx";
865 status = "disabled";
866 };
867
868 sai1: sai@4400a000 {
869 compatible = "st,stm32h7-sai";
870 #address-cells = <1>;
871 #size-cells = <1>;
872 ranges = <0 0x4400a000 0x400>;
873 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
874 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
875 resets = <&rcc SAI1_R>;
876 status = "disabled";
877
878 sai1a: audio-controller@4400a004 {
879 #sound-dai-cells = <0>;
880
881 compatible = "st,stm32-sai-sub-a";
882 reg = <0x4 0x20>;
883 clocks = <&rcc SAI1_K>;
884 clock-names = "sai_ck";
885 dmas = <&dmamux1 87 0x400 0x01>;
886 status = "disabled";
887 };
888
889 sai1b: audio-controller@4400a024 {
890 #sound-dai-cells = <0>;
891 compatible = "st,stm32-sai-sub-b";
892 reg = <0x24 0x20>;
893 clocks = <&rcc SAI1_K>;
894 clock-names = "sai_ck";
895 dmas = <&dmamux1 88 0x400 0x01>;
896 status = "disabled";
897 };
898 };
899
900 sai2: sai@4400b000 {
901 compatible = "st,stm32h7-sai";
902 #address-cells = <1>;
903 #size-cells = <1>;
904 ranges = <0 0x4400b000 0x400>;
905 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
906 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
907 resets = <&rcc SAI2_R>;
908 status = "disabled";
909
910 sai2a: audio-controller@4400b004 {
911 #sound-dai-cells = <0>;
912 compatible = "st,stm32-sai-sub-a";
913 reg = <0x4 0x20>;
914 clocks = <&rcc SAI2_K>;
915 clock-names = "sai_ck";
916 dmas = <&dmamux1 89 0x400 0x01>;
917 status = "disabled";
918 };
919
920 sai2b: audio-controller@4400b024 {
921 #sound-dai-cells = <0>;
922 compatible = "st,stm32-sai-sub-b";
923 reg = <0x24 0x20>;
924 clocks = <&rcc SAI2_K>;
925 clock-names = "sai_ck";
926 dmas = <&dmamux1 90 0x400 0x01>;
927 status = "disabled";
928 };
929 };
930
931 sai3: sai@4400c000 {
932 compatible = "st,stm32h7-sai";
933 #address-cells = <1>;
934 #size-cells = <1>;
935 ranges = <0 0x4400c000 0x400>;
936 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
937 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
938 resets = <&rcc SAI3_R>;
939 status = "disabled";
940
941 sai3a: audio-controller@4400c004 {
942 #sound-dai-cells = <0>;
943 compatible = "st,stm32-sai-sub-a";
944 reg = <0x04 0x20>;
945 clocks = <&rcc SAI3_K>;
946 clock-names = "sai_ck";
947 dmas = <&dmamux1 113 0x400 0x01>;
948 status = "disabled";
949 };
950
951 sai3b: audio-controller@4400c024 {
952 #sound-dai-cells = <0>;
953 compatible = "st,stm32-sai-sub-b";
954 reg = <0x24 0x20>;
955 clocks = <&rcc SAI3_K>;
956 clock-names = "sai_ck";
957 dmas = <&dmamux1 114 0x400 0x01>;
958 status = "disabled";
959 };
960 };
961
962 dfsdm: dfsdm@4400d000 {
963 compatible = "st,stm32mp1-dfsdm";
964 reg = <0x4400d000 0x800>;
965 clocks = <&rcc DFSDM_K>;
966 clock-names = "dfsdm";
967 #address-cells = <1>;
968 #size-cells = <0>;
969 status = "disabled";
970
971 dfsdm0: filter@0 {
972 compatible = "st,stm32-dfsdm-adc";
973 #io-channel-cells = <1>;
974 reg = <0>;
975 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
976 dmas = <&dmamux1 101 0x400 0x01>;
977 dma-names = "rx";
978 status = "disabled";
979 };
980
981 dfsdm1: filter@1 {
982 compatible = "st,stm32-dfsdm-adc";
983 #io-channel-cells = <1>;
984 reg = <1>;
985 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
986 dmas = <&dmamux1 102 0x400 0x01>;
987 dma-names = "rx";
988 status = "disabled";
989 };
990
991 dfsdm2: filter@2 {
992 compatible = "st,stm32-dfsdm-adc";
993 #io-channel-cells = <1>;
994 reg = <2>;
995 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
996 dmas = <&dmamux1 103 0x400 0x01>;
997 dma-names = "rx";
998 status = "disabled";
999 };
1000
1001 dfsdm3: filter@3 {
1002 compatible = "st,stm32-dfsdm-adc";
1003 #io-channel-cells = <1>;
1004 reg = <3>;
1005 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1006 dmas = <&dmamux1 104 0x400 0x01>;
1007 dma-names = "rx";
1008 status = "disabled";
1009 };
1010
1011 dfsdm4: filter@4 {
1012 compatible = "st,stm32-dfsdm-adc";
1013 #io-channel-cells = <1>;
1014 reg = <4>;
1015 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1016 dmas = <&dmamux1 91 0x400 0x01>;
1017 dma-names = "rx";
1018 status = "disabled";
1019 };
1020
1021 dfsdm5: filter@5 {
1022 compatible = "st,stm32-dfsdm-adc";
1023 #io-channel-cells = <1>;
1024 reg = <5>;
1025 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1026 dmas = <&dmamux1 92 0x400 0x01>;
1027 dma-names = "rx";
1028 status = "disabled";
1029 };
1030 };
1031
1032 dma1: dma-controller@48000000 {
1033 compatible = "st,stm32-dma";
1034 reg = <0x48000000 0x400>;
1035 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1038 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1039 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1040 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1041 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
1042 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1043 clocks = <&rcc DMA1>;
1044 resets = <&rcc DMA1_R>;
1045 #dma-cells = <4>;
1046 st,mem2mem;
1047 dma-requests = <8>;
1048 };
1049
1050 dma2: dma-controller@48001000 {
1051 compatible = "st,stm32-dma";
1052 reg = <0x48001000 0x400>;
1053 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1054 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1055 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1056 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1057 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1058 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1059 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1060 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1061 clocks = <&rcc DMA2>;
1062 resets = <&rcc DMA2_R>;
1063 #dma-cells = <4>;
1064 st,mem2mem;
1065 dma-requests = <8>;
1066 };
1067
1068 dmamux1: dma-router@48002000 {
1069 compatible = "st,stm32h7-dmamux";
1070 reg = <0x48002000 0x40>;
1071 #dma-cells = <3>;
1072 dma-requests = <128>;
1073 dma-masters = <&dma1 &dma2>;
1074 dma-channels = <16>;
1075 clocks = <&rcc DMAMUX>;
1076 resets = <&rcc DMAMUX_R>;
1077 };
1078
1079 adc: adc@48003000 {
1080 compatible = "st,stm32mp1-adc-core";
1081 reg = <0x48003000 0x400>;
1082 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1083 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1084 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1085 clock-names = "bus", "adc";
1086 interrupt-controller;
1087 st,syscfg = <&syscfg>;
1088 #interrupt-cells = <1>;
1089 #address-cells = <1>;
1090 #size-cells = <0>;
1091 status = "disabled";
1092
1093 adc1: adc@0 {
1094 compatible = "st,stm32mp1-adc";
1095 #io-channel-cells = <1>;
1096 #address-cells = <1>;
1097 #size-cells = <0>;
1098 reg = <0x0>;
1099 interrupt-parent = <&adc>;
1100 interrupts = <0>;
1101 dmas = <&dmamux1 9 0x400 0x01>;
1102 dma-names = "rx";
1103 status = "disabled";
1104 };
1105
1106 adc2: adc@100 {
1107 compatible = "st,stm32mp1-adc";
1108 #io-channel-cells = <1>;
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1111 reg = <0x100>;
1112 interrupt-parent = <&adc>;
1113 interrupts = <1>;
1114 dmas = <&dmamux1 10 0x400 0x01>;
1115 dma-names = "rx";
1116 nvmem-cells = <&vrefint>;
1117 nvmem-cell-names = "vrefint";
1118 status = "disabled";
1119 channel@13 {
1120 reg = <13>;
1121 label = "vrefint";
1122 };
1123 channel@14 {
1124 reg = <14>;
1125 label = "vddcore";
1126 };
1127 };
1128 };
1129
1130 sdmmc3: mmc@48004000 {
1131 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1132 arm,primecell-periphid = <0x00253180>;
1133 reg = <0x48004000 0x400>;
1134 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1135 clocks = <&rcc SDMMC3_K>;
1136 clock-names = "apb_pclk";
1137 resets = <&rcc SDMMC3_R>;
1138 cap-sd-highspeed;
1139 cap-mmc-highspeed;
1140 max-frequency = <120000000>;
1141 status = "disabled";
1142 };
1143
1144 usbotg_hs: usb-otg@49000000 {
1145 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1146 reg = <0x49000000 0x10000>;
1147 clocks = <&rcc USBO_K>, <&usbphyc>;
1148 clock-names = "otg", "utmi";
1149 resets = <&rcc USBO_R>;
1150 reset-names = "dwc2";
1151 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1152 g-rx-fifo-size = <512>;
1153 g-np-tx-fifo-size = <32>;
1154 g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
1155 dr_mode = "otg";
1156 otg-rev = <0x200>;
1157 usb33d-supply = <&usb33>;
1158 status = "disabled";
1159 };
1160
1161 ipcc: mailbox@4c001000 {
1162 compatible = "st,stm32mp1-ipcc";
1163 #mbox-cells = <1>;
1164 reg = <0x4c001000 0x400>;
1165 st,proc-id = <0>;
1166 interrupts-extended =
1167 <&exti 61 1>,
1168 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1169 interrupt-names = "rx", "tx";
1170 clocks = <&rcc IPCC>;
1171 wakeup-source;
1172 status = "disabled";
1173 };
1174
1175 dcmi: dcmi@4c006000 {
1176 compatible = "st,stm32-dcmi";
1177 reg = <0x4c006000 0x400>;
1178 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1179 resets = <&rcc CAMITF_R>;
1180 clocks = <&rcc DCMI>;
1181 clock-names = "mclk";
1182 dmas = <&dmamux1 75 0x400 0x01>;
1183 dma-names = "tx";
1184 status = "disabled";
1185 };
1186
1187 rcc: rcc@50000000 {
1188 compatible = "st,stm32mp1-rcc", "syscon";
1189 reg = <0x50000000 0x1000>;
1190 #clock-cells = <1>;
1191 #reset-cells = <1>;
1192 };
1193
1194 pwr_regulators: pwr@50001000 {
1195 compatible = "st,stm32mp1,pwr-reg";
1196 reg = <0x50001000 0x10>;
1197
1198 reg11: reg11 {
1199 regulator-name = "reg11";
1200 regulator-min-microvolt = <1100000>;
1201 regulator-max-microvolt = <1100000>;
1202 };
1203
1204 reg18: reg18 {
1205 regulator-name = "reg18";
1206 regulator-min-microvolt = <1800000>;
1207 regulator-max-microvolt = <1800000>;
1208 };
1209
1210 usb33: usb33 {
1211 regulator-name = "usb33";
1212 regulator-min-microvolt = <3300000>;
1213 regulator-max-microvolt = <3300000>;
1214 };
1215 };
1216
1217 pwr_mcu: pwr_mcu@50001014 {
1218 compatible = "st,stm32mp151-pwr-mcu", "syscon";
1219 reg = <0x50001014 0x4>;
1220 };
1221
1222 exti: interrupt-controller@5000d000 {
1223 compatible = "st,stm32mp1-exti", "syscon";
1224 interrupt-controller;
1225 #interrupt-cells = <2>;
1226 reg = <0x5000d000 0x400>;
1227 };
1228
1229 syscfg: syscon@50020000 {
1230 compatible = "st,stm32mp157-syscfg", "syscon";
1231 reg = <0x50020000 0x400>;
1232 clocks = <&rcc SYSCFG>;
1233 };
1234
1235 lptimer2: timer@50021000 {
1236 #address-cells = <1>;
1237 #size-cells = <0>;
1238 compatible = "st,stm32-lptimer";
1239 reg = <0x50021000 0x400>;
1240 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1241 clocks = <&rcc LPTIM2_K>;
1242 clock-names = "mux";
1243 wakeup-source;
1244 status = "disabled";
1245
1246 pwm {
1247 compatible = "st,stm32-pwm-lp";
1248 #pwm-cells = <3>;
1249 status = "disabled";
1250 };
1251
1252 trigger@1 {
1253 compatible = "st,stm32-lptimer-trigger";
1254 reg = <1>;
1255 status = "disabled";
1256 };
1257
1258 counter {
1259 compatible = "st,stm32-lptimer-counter";
1260 status = "disabled";
1261 };
1262 };
1263
1264 lptimer3: timer@50022000 {
1265 #address-cells = <1>;
1266 #size-cells = <0>;
1267 compatible = "st,stm32-lptimer";
1268 reg = <0x50022000 0x400>;
1269 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1270 clocks = <&rcc LPTIM3_K>;
1271 clock-names = "mux";
1272 wakeup-source;
1273 status = "disabled";
1274
1275 pwm {
1276 compatible = "st,stm32-pwm-lp";
1277 #pwm-cells = <3>;
1278 status = "disabled";
1279 };
1280
1281 trigger@2 {
1282 compatible = "st,stm32-lptimer-trigger";
1283 reg = <2>;
1284 status = "disabled";
1285 };
1286 };
1287
1288 lptimer4: timer@50023000 {
1289 compatible = "st,stm32-lptimer";
1290 reg = <0x50023000 0x400>;
1291 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1292 clocks = <&rcc LPTIM4_K>;
1293 clock-names = "mux";
1294 wakeup-source;
1295 status = "disabled";
1296
1297 pwm {
1298 compatible = "st,stm32-pwm-lp";
1299 #pwm-cells = <3>;
1300 status = "disabled";
1301 };
1302 };
1303
1304 lptimer5: timer@50024000 {
1305 compatible = "st,stm32-lptimer";
1306 reg = <0x50024000 0x400>;
1307 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1308 clocks = <&rcc LPTIM5_K>;
1309 clock-names = "mux";
1310 wakeup-source;
1311 status = "disabled";
1312
1313 pwm {
1314 compatible = "st,stm32-pwm-lp";
1315 #pwm-cells = <3>;
1316 status = "disabled";
1317 };
1318 };
1319
1320 vrefbuf: vrefbuf@50025000 {
1321 compatible = "st,stm32-vrefbuf";
1322 reg = <0x50025000 0x8>;
1323 regulator-min-microvolt = <1500000>;
1324 regulator-max-microvolt = <2500000>;
1325 clocks = <&rcc VREF>;
1326 status = "disabled";
1327 };
1328
1329 sai4: sai@50027000 {
1330 compatible = "st,stm32h7-sai";
1331 #address-cells = <1>;
1332 #size-cells = <1>;
1333 ranges = <0 0x50027000 0x400>;
1334 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1335 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1336 resets = <&rcc SAI4_R>;
1337 status = "disabled";
1338
1339 sai4a: audio-controller@50027004 {
1340 #sound-dai-cells = <0>;
1341 compatible = "st,stm32-sai-sub-a";
1342 reg = <0x04 0x20>;
1343 clocks = <&rcc SAI4_K>;
1344 clock-names = "sai_ck";
1345 dmas = <&dmamux1 99 0x400 0x01>;
1346 status = "disabled";
1347 };
1348
1349 sai4b: audio-controller@50027024 {
1350 #sound-dai-cells = <0>;
1351 compatible = "st,stm32-sai-sub-b";
1352 reg = <0x24 0x20>;
1353 clocks = <&rcc SAI4_K>;
1354 clock-names = "sai_ck";
1355 dmas = <&dmamux1 100 0x400 0x01>;
1356 status = "disabled";
1357 };
1358 };
1359
1360 dts: thermal@50028000 {
1361 compatible = "st,stm32-thermal";
1362 reg = <0x50028000 0x100>;
1363 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1364 clocks = <&rcc TMPSENS>;
1365 clock-names = "pclk";
1366 #thermal-sensor-cells = <0>;
1367 status = "disabled";
1368 };
1369
1370 hash1: hash@54002000 {
1371 compatible = "st,stm32f756-hash";
1372 reg = <0x54002000 0x400>;
1373 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1374 clocks = <&rcc HASH1>;
1375 resets = <&rcc HASH1_R>;
1376 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
1377 dma-names = "in";
1378 dma-maxburst = <2>;
1379 status = "disabled";
1380 };
1381
1382 rng1: rng@54003000 {
1383 compatible = "st,stm32-rng";
1384 reg = <0x54003000 0x400>;
1385 clocks = <&rcc RNG1_K>;
1386 resets = <&rcc RNG1_R>;
1387 status = "disabled";
1388 };
1389
1390 mdma1: dma-controller@58000000 {
1391 compatible = "st,stm32h7-mdma";
1392 reg = <0x58000000 0x1000>;
1393 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1394 clocks = <&rcc MDMA>;
1395 resets = <&rcc MDMA_R>;
1396 #dma-cells = <5>;
1397 dma-channels = <32>;
1398 dma-requests = <48>;
1399 };
1400
1401 fmc: memory-controller@58002000 {
1402 #address-cells = <2>;
1403 #size-cells = <1>;
1404 compatible = "st,stm32mp1-fmc2-ebi";
1405 reg = <0x58002000 0x1000>;
1406 clocks = <&rcc FMC_K>;
1407 resets = <&rcc FMC_R>;
1408 status = "disabled";
1409
1410 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1411 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1412 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1413 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1414 <4 0 0x80000000 0x10000000>; /* NAND */
1415
1416 nand-controller@4,0 {
1417 #address-cells = <1>;
1418 #size-cells = <0>;
1419 compatible = "st,stm32mp1-fmc2-nfc";
1420 reg = <4 0x00000000 0x1000>,
1421 <4 0x08010000 0x1000>,
1422 <4 0x08020000 0x1000>,
1423 <4 0x01000000 0x1000>,
1424 <4 0x09010000 0x1000>,
1425 <4 0x09020000 0x1000>;
1426 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1427 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
1428 <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
1429 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
1430 dma-names = "tx", "rx", "ecc";
1431 status = "disabled";
1432 };
1433 };
1434
1435 qspi: spi@58003000 {
1436 compatible = "st,stm32f469-qspi";
1437 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1438 reg-names = "qspi", "qspi_mm";
1439 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1440 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
1441 <&mdma1 22 0x2 0x10100008 0x0 0x0>;
1442 dma-names = "tx", "rx";
1443 clocks = <&rcc QSPI_K>;
1444 resets = <&rcc QSPI_R>;
1445 #address-cells = <1>;
1446 #size-cells = <0>;
1447 status = "disabled";
1448 };
1449
1450 sdmmc1: mmc@58005000 {
1451 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1452 arm,primecell-periphid = <0x00253180>;
1453 reg = <0x58005000 0x1000>;
1454 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1455 clocks = <&rcc SDMMC1_K>;
1456 clock-names = "apb_pclk";
1457 resets = <&rcc SDMMC1_R>;
1458 cap-sd-highspeed;
1459 cap-mmc-highspeed;
1460 max-frequency = <120000000>;
1461 status = "disabled";
1462 };
1463
1464 sdmmc2: mmc@58007000 {
1465 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1466 arm,primecell-periphid = <0x00253180>;
1467 reg = <0x58007000 0x1000>;
1468 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1469 clocks = <&rcc SDMMC2_K>;
1470 clock-names = "apb_pclk";
1471 resets = <&rcc SDMMC2_R>;
1472 cap-sd-highspeed;
1473 cap-mmc-highspeed;
1474 max-frequency = <120000000>;
1475 status = "disabled";
1476 };
1477
1478 crc1: crc@58009000 {
1479 compatible = "st,stm32f7-crc";
1480 reg = <0x58009000 0x400>;
1481 clocks = <&rcc CRC1>;
1482 status = "disabled";
1483 };
1484
1485 ethernet0: ethernet@5800a000 {
1486 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1487 reg = <0x5800a000 0x2000>;
1488 reg-names = "stmmaceth";
1489 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1490 interrupt-names = "macirq";
1491 clock-names = "stmmaceth",
1492 "mac-clk-tx",
1493 "mac-clk-rx",
1494 "eth-ck",
1495 "ptp_ref",
1496 "ethstp";
1497 clocks = <&rcc ETHMAC>,
1498 <&rcc ETHTX>,
1499 <&rcc ETHRX>,
1500 <&rcc ETHCK_K>,
1501 <&rcc ETHPTP_K>,
1502 <&rcc ETHSTP>;
1503 st,syscon = <&syscfg 0x4>;
1504 snps,mixed-burst;
1505 snps,pbl = <2>;
1506 snps,en-tx-lpi-clockgating;
1507 snps,axi-config = <&stmmac_axi_config_0>;
1508 snps,tso;
1509 status = "disabled";
1510
1511 stmmac_axi_config_0: stmmac-axi-config {
1512 snps,wr_osr_lmt = <0x7>;
1513 snps,rd_osr_lmt = <0x7>;
1514 snps,blen = <0 0 0 0 16 8 4>;
1515 };
1516 };
1517
1518 usbh_ohci: usb@5800c000 {
1519 compatible = "generic-ohci";
1520 reg = <0x5800c000 0x1000>;
1521 clocks = <&usbphyc>, <&rcc USBH>;
1522 resets = <&rcc USBH_R>;
1523 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1524 phys = <&usbphyc_port0>;
1525 phy-names = "usb";
1526 status = "disabled";
1527 };
1528
1529 usbh_ehci: usb@5800d000 {
1530 compatible = "generic-ehci";
1531 reg = <0x5800d000 0x1000>;
1532 clocks = <&usbphyc>, <&rcc USBH>;
1533 resets = <&rcc USBH_R>;
1534 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1535 companion = <&usbh_ohci>;
1536 phys = <&usbphyc_port0>;
1537 phy-names = "usb";
1538 status = "disabled";
1539 };
1540
1541 ltdc: display-controller@5a001000 {
1542 compatible = "st,stm32-ltdc";
1543 reg = <0x5a001000 0x400>;
1544 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1545 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1546 clocks = <&rcc LTDC_PX>;
1547 clock-names = "lcd";
1548 resets = <&rcc LTDC_R>;
1549 status = "disabled";
1550 };
1551
1552 iwdg2: watchdog@5a002000 {
1553 compatible = "st,stm32mp1-iwdg";
1554 reg = <0x5a002000 0x400>;
1555 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1556 clock-names = "pclk", "lsi";
1557 status = "disabled";
1558 };
1559
1560 usbphyc: usbphyc@5a006000 {
1561 #address-cells = <1>;
1562 #size-cells = <0>;
1563 #clock-cells = <0>;
1564 compatible = "st,stm32mp1-usbphyc";
1565 reg = <0x5a006000 0x1000>;
1566 clocks = <&rcc USBPHY_K>;
1567 resets = <&rcc USBPHY_R>;
1568 vdda1v1-supply = <&reg11>;
1569 vdda1v8-supply = <&reg18>;
1570 status = "disabled";
1571
1572 usbphyc_port0: usb-phy@0 {
1573 #phy-cells = <0>;
1574 reg = <0>;
1575 };
1576
1577 usbphyc_port1: usb-phy@1 {
1578 #phy-cells = <1>;
1579 reg = <1>;
1580 };
1581 };
1582
1583 usart1: serial@5c000000 {
1584 compatible = "st,stm32h7-uart";
1585 reg = <0x5c000000 0x400>;
1586 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
1587 clocks = <&rcc USART1_K>;
1588 wakeup-source;
1589 status = "disabled";
1590 };
1591
1592 spi6: spi@5c001000 {
1593 #address-cells = <1>;
1594 #size-cells = <0>;
1595 compatible = "st,stm32h7-spi";
1596 reg = <0x5c001000 0x400>;
1597 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1598 clocks = <&rcc SPI6_K>;
1599 resets = <&rcc SPI6_R>;
1600 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1601 <&mdma1 35 0x0 0x40002 0x0 0x0>;
1602 dma-names = "rx", "tx";
1603 status = "disabled";
1604 };
1605
1606 i2c4: i2c@5c002000 {
1607 compatible = "st,stm32mp15-i2c";
1608 reg = <0x5c002000 0x400>;
1609 interrupt-names = "event", "error";
1610 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1611 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1612 clocks = <&rcc I2C4_K>;
1613 resets = <&rcc I2C4_R>;
1614 #address-cells = <1>;
1615 #size-cells = <0>;
1616 st,syscfg-fmp = <&syscfg 0x4 0x8>;
1617 wakeup-source;
1618 i2c-analog-filter;
1619 status = "disabled";
1620 };
1621
1622 rtc: rtc@5c004000 {
1623 compatible = "st,stm32mp1-rtc";
1624 reg = <0x5c004000 0x400>;
1625 clocks = <&rcc RTCAPB>, <&rcc RTC>;
1626 clock-names = "pclk", "rtc_ck";
1627 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
1628 status = "disabled";
1629 };
1630
1631 bsec: efuse@5c005000 {
1632 compatible = "st,stm32mp15-bsec";
1633 reg = <0x5c005000 0x400>;
1634 #address-cells = <1>;
1635 #size-cells = <1>;
1636 part_number_otp: part-number-otp@4 {
1637 reg = <0x4 0x1>;
1638 };
1639 vrefint: vrefin-cal@52 {
1640 reg = <0x52 0x2>;
1641 };
1642 ts_cal1: calib@5c {
1643 reg = <0x5c 0x2>;
1644 };
1645 ts_cal2: calib@5e {
1646 reg = <0x5e 0x2>;
1647 };
1648 };
1649
1650 i2c6: i2c@5c009000 {
1651 compatible = "st,stm32mp15-i2c";
1652 reg = <0x5c009000 0x400>;
1653 interrupt-names = "event", "error";
1654 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1655 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1656 clocks = <&rcc I2C6_K>;
1657 resets = <&rcc I2C6_R>;
1658 #address-cells = <1>;
1659 #size-cells = <0>;
1660 st,syscfg-fmp = <&syscfg 0x4 0x20>;
1661 wakeup-source;
1662 i2c-analog-filter;
1663 status = "disabled";
1664 };
1665
1666 tamp: tamp@5c00a000 {
1667 compatible = "st,stm32-tamp", "syscon", "simple-mfd";
1668 reg = <0x5c00a000 0x400>;
1669 };
1670
1671 /*
1672 * Break node order to solve dependency probe issue between
1673 * pinctrl and exti.
1674 */
1675 pinctrl: pinctrl@50002000 {
1676 #address-cells = <1>;
1677 #size-cells = <1>;
1678 compatible = "st,stm32mp157-pinctrl";
1679 ranges = <0 0x50002000 0xa400>;
1680 interrupt-parent = <&exti>;
1681 st,syscfg = <&exti 0x60 0xff>;
1682
1683 gpioa: gpio@50002000 {
1684 gpio-controller;
1685 #gpio-cells = <2>;
1686 interrupt-controller;
1687 #interrupt-cells = <2>;
1688 reg = <0x0 0x400>;
1689 clocks = <&rcc GPIOA>;
1690 st,bank-name = "GPIOA";
1691 status = "disabled";
1692 };
1693
1694 gpiob: gpio@50003000 {
1695 gpio-controller;
1696 #gpio-cells = <2>;
1697 interrupt-controller;
1698 #interrupt-cells = <2>;
1699 reg = <0x1000 0x400>;
1700 clocks = <&rcc GPIOB>;
1701 st,bank-name = "GPIOB";
1702 status = "disabled";
1703 };
1704
1705 gpioc: gpio@50004000 {
1706 gpio-controller;
1707 #gpio-cells = <2>;
1708 interrupt-controller;
1709 #interrupt-cells = <2>;
1710 reg = <0x2000 0x400>;
1711 clocks = <&rcc GPIOC>;
1712 st,bank-name = "GPIOC";
1713 status = "disabled";
1714 };
1715
1716 gpiod: gpio@50005000 {
1717 gpio-controller;
1718 #gpio-cells = <2>;
1719 interrupt-controller;
1720 #interrupt-cells = <2>;
1721 reg = <0x3000 0x400>;
1722 clocks = <&rcc GPIOD>;
1723 st,bank-name = "GPIOD";
1724 status = "disabled";
1725 };
1726
1727 gpioe: gpio@50006000 {
1728 gpio-controller;
1729 #gpio-cells = <2>;
1730 interrupt-controller;
1731 #interrupt-cells = <2>;
1732 reg = <0x4000 0x400>;
1733 clocks = <&rcc GPIOE>;
1734 st,bank-name = "GPIOE";
1735 status = "disabled";
1736 };
1737
1738 gpiof: gpio@50007000 {
1739 gpio-controller;
1740 #gpio-cells = <2>;
1741 interrupt-controller;
1742 #interrupt-cells = <2>;
1743 reg = <0x5000 0x400>;
1744 clocks = <&rcc GPIOF>;
1745 st,bank-name = "GPIOF";
1746 status = "disabled";
1747 };
1748
1749 gpiog: gpio@50008000 {
1750 gpio-controller;
1751 #gpio-cells = <2>;
1752 interrupt-controller;
1753 #interrupt-cells = <2>;
1754 reg = <0x6000 0x400>;
1755 clocks = <&rcc GPIOG>;
1756 st,bank-name = "GPIOG";
1757 status = "disabled";
1758 };
1759
1760 gpioh: gpio@50009000 {
1761 gpio-controller;
1762 #gpio-cells = <2>;
1763 interrupt-controller;
1764 #interrupt-cells = <2>;
1765 reg = <0x7000 0x400>;
1766 clocks = <&rcc GPIOH>;
1767 st,bank-name = "GPIOH";
1768 status = "disabled";
1769 };
1770
1771 gpioi: gpio@5000a000 {
1772 gpio-controller;
1773 #gpio-cells = <2>;
1774 interrupt-controller;
1775 #interrupt-cells = <2>;
1776 reg = <0x8000 0x400>;
1777 clocks = <&rcc GPIOI>;
1778 st,bank-name = "GPIOI";
1779 status = "disabled";
1780 };
1781
1782 gpioj: gpio@5000b000 {
1783 gpio-controller;
1784 #gpio-cells = <2>;
1785 interrupt-controller;
1786 #interrupt-cells = <2>;
1787 reg = <0x9000 0x400>;
1788 clocks = <&rcc GPIOJ>;
1789 st,bank-name = "GPIOJ";
1790 status = "disabled";
1791 };
1792
1793 gpiok: gpio@5000c000 {
1794 gpio-controller;
1795 #gpio-cells = <2>;
1796 interrupt-controller;
1797 #interrupt-cells = <2>;
1798 reg = <0xa000 0x400>;
1799 clocks = <&rcc GPIOK>;
1800 st,bank-name = "GPIOK";
1801 status = "disabled";
1802 };
1803 };
1804
1805 pinctrl_z: pinctrl@54004000 {
1806 #address-cells = <1>;
1807 #size-cells = <1>;
1808 compatible = "st,stm32mp157-z-pinctrl";
1809 ranges = <0 0x54004000 0x400>;
1810 interrupt-parent = <&exti>;
1811 st,syscfg = <&exti 0x60 0xff>;
1812
1813 gpioz: gpio@54004000 {
1814 gpio-controller;
1815 #gpio-cells = <2>;
1816 interrupt-controller;
1817 #interrupt-cells = <2>;
1818 reg = <0 0x400>;
1819 clocks = <&rcc GPIOZ>;
1820 st,bank-name = "GPIOZ";
1821 st,bank-ioport = <11>;
1822 status = "disabled";
1823 };
1824 };
1825 };
1826
1827 mlahb: ahb {
1828 compatible = "st,mlahb", "simple-bus";
1829 #address-cells = <1>;
1830 #size-cells = <1>;
1831 ranges;
1832 dma-ranges = <0x00000000 0x38000000 0x10000>,
1833 <0x10000000 0x10000000 0x60000>,
1834 <0x30000000 0x30000000 0x60000>;
1835
1836 m4_rproc: m4@10000000 {
1837 compatible = "st,stm32mp1-m4";
1838 reg = <0x10000000 0x40000>,
1839 <0x30000000 0x40000>,
1840 <0x38000000 0x10000>;
1841 resets = <&rcc MCU_R>;
1842 reset-names = "mcu_rst";
1843 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1844 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
1845 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
1846 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
1847 status = "disabled";
1848 };
1849 };
1850 };
"Das U-Boot" Source Tree